- Merge from trunk up to r45543
[reactos.git] / boot / armllb / hw / versatile / hwuart.c
1 /*
2 * PROJECT: ReactOS Boot Loader
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: boot/armllb/hw/versatile/hwuart.c
5 * PURPOSE: LLB UART Initialization Routines for Versatile
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 #include "precomp.h"
10
11 //
12 // UART Registers
13 //
14 #define UART_PL01x_DR (LlbHwVersaUartBase + 0x00)
15 #define UART_PL01x_RSR (LlbHwVersaUartBase + 0x04)
16 #define UART_PL01x_ECR (LlbHwVersaUartBase + 0x04)
17 #define UART_PL01x_FR (LlbHwVersaUartBase + 0x18)
18 #define UART_PL011_IBRD (LlbHwVersaUartBase + 0x24)
19 #define UART_PL011_FBRD (LlbHwVersaUartBase + 0x28)
20 #define UART_PL011_LCRH (LlbHwVersaUartBase + 0x2C)
21 #define UART_PL011_CR (LlbHwVersaUartBase + 0x30)
22 #define UART_PL011_IMSC (LlbHwVersaUartBase + 0x38)
23
24 //
25 // LCR Values
26 //
27 #define UART_PL011_LCRH_WLEN_8 0x60
28 #define UART_PL011_LCRH_FEN 0x10
29
30 //
31 // FCR Values
32 //
33 #define UART_PL011_CR_UARTEN 0x01
34 #define UART_PL011_CR_TXE 0x100
35 #define UART_PL011_CR_RXE 0x200
36
37 //
38 // LSR Values
39 //
40 #define UART_PL01x_FR_RXFE 0x10
41 #define UART_PL01x_FR_TXFF 0x20
42
43 static const ULONG LlbHwVersaUartBase = 0x101F1000;
44
45 /* FUNCTIONS ******************************************************************/
46
47 VOID
48 NTAPI
49 LlbHwVersaUartInitialize(VOID)
50 {
51 ULONG Divider, Remainder, Fraction, ClockRate, Baudrate;
52
53 /* Query peripheral rate, hardcore baudrate */
54 ClockRate = LlbHwGetPClk();
55 Baudrate = 115200;
56
57 /* Calculate baudrate clock divider and remainder */
58 Divider = ClockRate / (16 * Baudrate);
59 Remainder = ClockRate % (16 * Baudrate);
60
61 /* Calculate the fractional part */
62 Fraction = (8 * Remainder / Baudrate) >> 1;
63 Fraction += (8 * Remainder / Baudrate) & 1;
64
65 /* Disable interrupts */
66 WRITE_REGISTER_ULONG(UART_PL011_CR, 0);
67
68 /* Set the baud rate to 115200 bps */
69 WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider);
70 WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction);
71
72 /* Set 8 bits for data, 1 stop bit, no parity, FIFO enabled */
73 WRITE_REGISTER_ULONG(UART_PL011_LCRH,
74 UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN);
75
76 /* Clear and enable FIFO */
77 WRITE_REGISTER_ULONG(UART_PL011_CR,
78 UART_PL011_CR_UARTEN |
79 UART_PL011_CR_TXE |
80 UART_PL011_CR_RXE);
81 }
82
83 VOID
84 NTAPI
85 LlbHwUartSendChar(IN CHAR Char)
86 {
87 /* Send the character */
88 WRITE_REGISTER_ULONG(UART_PL01x_DR, Char);
89 }
90
91 BOOLEAN
92 NTAPI
93 LlbHwUartTxReady(VOID)
94 {
95 /* TX output buffer is ready? */
96 return ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF) == 0);
97 }
98
99 ULONG
100 NTAPI
101 LlbHwGetUartBase(IN ULONG Port)
102 {
103 if (Port == 0)
104 {
105 return 0x101F1000;
106 }
107 else if (Port == 1)
108 {
109 return 0x101F2000;
110 }
111
112 return 0;
113 }
114
115 /* EOF */