drivers/base/kdrosdbg/arm/kdbg.c

   1 /*
   2  * PROJECT:         ReactOS Kernel
   3  * LICENSE:         BSD - See COPYING.ARM in the top level directory
   4  * FILE:            drivers/base/kdcom/arm/kdbg.c
   5  * PURPOSE:         Serial Port Kernel Debugging Transport Library
   6  * PROGRAMMERS:     ReactOS Portable Systems Group
   7  */
   8
   9 /* INCLUDES *******************************************************************/
  10
  11 #define NOEXTAPI
  12 #include <ntifs.h>
  13 #include <arc/arc.h>
  14 #include <halfuncs.h>
  15 #include <windbgkd.h>
  16 #include <ioaccess.h> /* port intrinsics */
  17 #include <cportlib/cportlib.h>
  18 #include <arm/peripherals/pl011.h>
  19 #include <stdio.h>
  20
  21 #define NDEBUG
  22 #include <debug.h>
  23
  24 /* GLOBALS ********************************************************************/
  25
  26 CPPORT DefaultPort = {0, 0, 0};
  27
  28 //
  29 // We need to build this in the configuration root and use KeFindConfigurationEntry
  30 // to recover it later.
  31 //
  32 #define HACK 24000000
  33
  34 /* REACTOS FUNCTIONS **********************************************************/
  35
  36 BOOLEAN
  37 NTAPI
  38 KdPortInitializeEx(IN PCPPORT PortInformation,
  39                    IN ULONG ComPortNumber)
  40 {
  41     ULONG Divider, Remainder, Fraction;
  42     ULONG Baudrate = PortInformation->BaudRate;
  43
  44     //
  45     // Calculate baudrate clock divider and remainder
  46     //
  47     Divider   = HACK / (16 * Baudrate);
  48     Remainder = HACK % (16 * Baudrate);
  49
  50     //
  51     // Calculate the fractional part
  52     //
  53     Fraction  = (8 * Remainder / Baudrate) >> 1;
  54     Fraction += (8 * Remainder / Baudrate) & 1;
  55
  56     //
  57     // Disable interrupts
  58     //
  59     WRITE_REGISTER_ULONG(UART_PL011_CR, 0);
  60
  61     //
  62     // Set the baud rate
  63     //
  64     WRITE_REGISTER_ULONG(UART_PL011_IBRD, Divider);
  65     WRITE_REGISTER_ULONG(UART_PL011_FBRD, Fraction);
  66
  67     //
  68     // Set 8 bits for data, 1 stop bit, no parity, FIFO enabled
  69     //
  70     WRITE_REGISTER_ULONG(UART_PL011_LCRH,
  71                          UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN);
  72
  73     //
  74     // Clear and enable FIFO
  75     //
  76     WRITE_REGISTER_ULONG(UART_PL011_CR,
  77                          UART_PL011_CR_UARTEN |
  78                          UART_PL011_CR_TXE |
  79                          UART_PL011_CR_RXE);
  80
  81     //
  82     // Done
  83     //
  84     return TRUE;
  85 }
  86
  87 BOOLEAN
  88 NTAPI
  89 KdPortGetByteEx(IN PCPPORT PortInformation,
  90                 OUT PUCHAR ByteReceived)
  91 {
  92     UNIMPLEMENTED;
  93     while (TRUE);
  94     return FALSE;
  95 }
  96
  97 VOID
  98 NTAPI
  99 KdPortPutByteEx(IN PCPPORT PortInformation,
 100                 IN UCHAR ByteToSend)
 101 {
 102     //
 103     // Wait for ready
 104     //
 105     while ((READ_REGISTER_ULONG(UART_PL01x_FR) & UART_PL01x_FR_TXFF) != 0);
 106
 107     //
 108     // Send the character
 109     //
 110     WRITE_REGISTER_ULONG(UART_PL01x_DR, ByteToSend);
 111 }
 112
 113 /* EOF */