1 /*******************************************************************************
3 * Module Name: rsirq - IRQ resource descriptors
5 ******************************************************************************/
7 /******************************************************************************
11 * Some or all of this work - Copyright (c) 1999 - 2014, Intel Corp.
12 * All rights reserved.
16 * 2.1. This is your license from Intel Corp. under its intellectual property
17 * rights. You may have additional license terms from the party that provided
18 * you this software, covering your right to use that party's intellectual
21 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
22 * copy of the source code appearing in this file ("Covered Code") an
23 * irrevocable, perpetual, worldwide license under Intel's copyrights in the
24 * base code distributed originally by Intel ("Original Intel Code") to copy,
25 * make derivatives, distribute, use and display any portion of the Covered
26 * Code in any form, with the right to sublicense such rights; and
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
29 * license (with the right to sublicense), under only those claims of Intel
30 * patents that are infringed by the Original Intel Code, to make, use, sell,
31 * offer to sell, and import the Covered Code and derivative works thereof
32 * solely to the minimum extent necessary to exercise the above copyright
33 * license, and in no event shall the patent license extend to any additions
34 * to or modifications of the Original Intel Code. No other license or right
35 * is granted directly or by implication, estoppel or otherwise;
37 * The above copyright and patent license is granted only if the following
42 * 3.1. Redistribution of Source with Rights to Further Distribute Source.
43 * Redistribution of source code of any substantial portion of the Covered
44 * Code or modification with rights to further distribute source must include
45 * the above Copyright Notice, the above License, this list of Conditions,
46 * and the following Disclaimer and Export Compliance provision. In addition,
47 * Licensee must cause all Covered Code to which Licensee contributes to
48 * contain a file documenting the changes Licensee made to create that Covered
49 * Code and the date of any change. Licensee must include in that file the
50 * documentation of any changes made by any predecessor Licensee. Licensee
51 * must include a prominent statement that the modification is derived,
52 * directly or indirectly, from Original Intel Code.
54 * 3.2. Redistribution of Source with no Rights to Further Distribute Source.
55 * Redistribution of source code of any substantial portion of the Covered
56 * Code or modification without rights to further distribute source must
57 * include the following Disclaimer and Export Compliance provision in the
58 * documentation and/or other materials provided with distribution. In
59 * addition, Licensee may not authorize further sublicense of source of any
60 * portion of the Covered Code, and must include terms to the effect that the
61 * license from Licensee to its licensee is limited to the intellectual
62 * property embodied in the software Licensee provides to its licensee, and
63 * not to intellectual property embodied in modifications its licensee may
66 * 3.3. Redistribution of Executable. Redistribution in executable form of any
67 * substantial portion of the Covered Code or modification must reproduce the
68 * above Copyright Notice, and the following Disclaimer and Export Compliance
69 * provision in the documentation and/or other materials provided with the
72 * 3.4. Intel retains all right, title, and interest in and to the Original
75 * 3.5. Neither the name Intel nor any other trademark owned or controlled by
76 * Intel shall be used in advertising or otherwise to promote the sale, use or
77 * other dealings in products derived from or relating to the Covered Code
78 * without prior written authorization from Intel.
80 * 4. Disclaimer and Export Compliance
82 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
83 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
84 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
85 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
86 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
87 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
90 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
91 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
92 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
93 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
94 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
95 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
96 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
99 * 4.3. Licensee shall not export, either directly or indirectly, any of this
100 * software or system incorporating such software without first obtaining any
101 * required license or other approval from the U. S. Department of Commerce or
102 * any other agency or department of the United States Government. In the
103 * event Licensee exports any such software from the United States or
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
106 * compliance with all laws, regulations, orders, or other restrictions of the
107 * U.S. Export Administration Regulations. Licensee agrees that neither it nor
108 * any of its subsidiaries will export/re-export any technical data, process,
109 * software, or service, directly or indirectly, to any country for which the
110 * United States government or any agency thereof requires an export license,
111 * other governmental approval, or letter of assurance, without first obtaining
112 * such license, approval or letter.
114 *****************************************************************************/
119 #include "accommon.h"
122 #define _COMPONENT ACPI_RESOURCES
123 ACPI_MODULE_NAME ("rsirq")
126 /*******************************************************************************
130 ******************************************************************************/
132 ACPI_RSCONVERT_INFO AcpiRsGetIrq
[9] =
134 {ACPI_RSC_INITGET
, ACPI_RESOURCE_TYPE_IRQ
,
135 ACPI_RS_SIZE (ACPI_RESOURCE_IRQ
),
136 ACPI_RSC_TABLE_SIZE (AcpiRsGetIrq
)},
138 /* Get the IRQ mask (bytes 1:2) */
140 {ACPI_RSC_BITMASK16
,ACPI_RS_OFFSET (Data
.Irq
.Interrupts
[0]),
141 AML_OFFSET (Irq
.IrqMask
),
142 ACPI_RS_OFFSET (Data
.Irq
.InterruptCount
)},
144 /* Set default flags (others are zero) */
146 {ACPI_RSC_SET8
, ACPI_RS_OFFSET (Data
.Irq
.Triggering
),
150 /* Get the descriptor length (2 or 3 for IRQ descriptor) */
152 {ACPI_RSC_2BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.DescriptorLength
),
153 AML_OFFSET (Irq
.DescriptorType
),
156 /* All done if no flag byte present in descriptor */
158 {ACPI_RSC_EXIT_NE
, ACPI_RSC_COMPARE_AML_LENGTH
, 0, 3},
160 /* Get flags: Triggering[0], Polarity[3], Sharing[4], Wake[5] */
162 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.Triggering
),
163 AML_OFFSET (Irq
.Flags
),
166 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.Polarity
),
167 AML_OFFSET (Irq
.Flags
),
170 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.Sharable
),
171 AML_OFFSET (Irq
.Flags
),
174 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.WakeCapable
),
175 AML_OFFSET (Irq
.Flags
),
180 /*******************************************************************************
184 ******************************************************************************/
186 ACPI_RSCONVERT_INFO AcpiRsSetIrq
[14] =
188 /* Start with a default descriptor of length 3 */
190 {ACPI_RSC_INITSET
, ACPI_RESOURCE_NAME_IRQ
,
191 sizeof (AML_RESOURCE_IRQ
),
192 ACPI_RSC_TABLE_SIZE (AcpiRsSetIrq
)},
194 /* Convert interrupt list to 16-bit IRQ bitmask */
196 {ACPI_RSC_BITMASK16
,ACPI_RS_OFFSET (Data
.Irq
.Interrupts
[0]),
197 AML_OFFSET (Irq
.IrqMask
),
198 ACPI_RS_OFFSET (Data
.Irq
.InterruptCount
)},
200 /* Set flags: Triggering[0], Polarity[3], Sharing[4], Wake[5] */
202 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.Triggering
),
203 AML_OFFSET (Irq
.Flags
),
206 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.Polarity
),
207 AML_OFFSET (Irq
.Flags
),
210 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.Sharable
),
211 AML_OFFSET (Irq
.Flags
),
214 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Irq
.WakeCapable
),
215 AML_OFFSET (Irq
.Flags
),
219 * All done if the output descriptor length is required to be 3
220 * (i.e., optimization to 2 bytes cannot be attempted)
222 {ACPI_RSC_EXIT_EQ
, ACPI_RSC_COMPARE_VALUE
,
223 ACPI_RS_OFFSET(Data
.Irq
.DescriptorLength
),
226 /* Set length to 2 bytes (no flags byte) */
228 {ACPI_RSC_LENGTH
, 0, 0, sizeof (AML_RESOURCE_IRQ_NOFLAGS
)},
231 * All done if the output descriptor length is required to be 2.
233 * TBD: Perhaps we should check for error if input flags are not
234 * compatible with a 2-byte descriptor.
236 {ACPI_RSC_EXIT_EQ
, ACPI_RSC_COMPARE_VALUE
,
237 ACPI_RS_OFFSET(Data
.Irq
.DescriptorLength
),
240 /* Reset length to 3 bytes (descriptor with flags byte) */
242 {ACPI_RSC_LENGTH
, 0, 0, sizeof (AML_RESOURCE_IRQ
)},
245 * Check if the flags byte is necessary. Not needed if the flags are:
246 * ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_HIGH, ACPI_EXCLUSIVE
248 {ACPI_RSC_EXIT_NE
, ACPI_RSC_COMPARE_VALUE
,
249 ACPI_RS_OFFSET (Data
.Irq
.Triggering
),
250 ACPI_EDGE_SENSITIVE
},
252 {ACPI_RSC_EXIT_NE
, ACPI_RSC_COMPARE_VALUE
,
253 ACPI_RS_OFFSET (Data
.Irq
.Polarity
),
256 {ACPI_RSC_EXIT_NE
, ACPI_RSC_COMPARE_VALUE
,
257 ACPI_RS_OFFSET (Data
.Irq
.Sharable
),
260 /* We can optimize to a 2-byte IrqNoFlags() descriptor */
262 {ACPI_RSC_LENGTH
, 0, 0, sizeof (AML_RESOURCE_IRQ_NOFLAGS
)}
266 /*******************************************************************************
268 * AcpiRsConvertExtIrq
270 ******************************************************************************/
272 ACPI_RSCONVERT_INFO AcpiRsConvertExtIrq
[10] =
274 {ACPI_RSC_INITGET
, ACPI_RESOURCE_TYPE_EXTENDED_IRQ
,
275 ACPI_RS_SIZE (ACPI_RESOURCE_EXTENDED_IRQ
),
276 ACPI_RSC_TABLE_SIZE (AcpiRsConvertExtIrq
)},
278 {ACPI_RSC_INITSET
, ACPI_RESOURCE_NAME_EXTENDED_IRQ
,
279 sizeof (AML_RESOURCE_EXTENDED_IRQ
),
283 * Flags: Producer/Consumer[0], Triggering[1], Polarity[2],
284 * Sharing[3], Wake[4]
286 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.ProducerConsumer
),
287 AML_OFFSET (ExtendedIrq
.Flags
),
290 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.Triggering
),
291 AML_OFFSET (ExtendedIrq
.Flags
),
294 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.Polarity
),
295 AML_OFFSET (ExtendedIrq
.Flags
),
298 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.Sharable
),
299 AML_OFFSET (ExtendedIrq
.Flags
),
302 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.WakeCapable
),
303 AML_OFFSET (ExtendedIrq
.Flags
),
306 /* IRQ Table length (Byte4) */
308 {ACPI_RSC_COUNT
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.InterruptCount
),
309 AML_OFFSET (ExtendedIrq
.InterruptCount
),
312 /* Copy every IRQ in the table, each is 32 bits */
314 {ACPI_RSC_MOVE32
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.Interrupts
[0]),
315 AML_OFFSET (ExtendedIrq
.Interrupts
[0]),
318 /* Optional ResourceSource (Index and String) */
320 {ACPI_RSC_SOURCEX
, ACPI_RS_OFFSET (Data
.ExtendedIrq
.ResourceSource
),
321 ACPI_RS_OFFSET (Data
.ExtendedIrq
.Interrupts
[0]),
322 sizeof (AML_RESOURCE_EXTENDED_IRQ
)}
326 /*******************************************************************************
330 ******************************************************************************/
332 ACPI_RSCONVERT_INFO AcpiRsConvertDma
[6] =
334 {ACPI_RSC_INITGET
, ACPI_RESOURCE_TYPE_DMA
,
335 ACPI_RS_SIZE (ACPI_RESOURCE_DMA
),
336 ACPI_RSC_TABLE_SIZE (AcpiRsConvertDma
)},
338 {ACPI_RSC_INITSET
, ACPI_RESOURCE_NAME_DMA
,
339 sizeof (AML_RESOURCE_DMA
),
342 /* Flags: transfer preference, bus mastering, channel speed */
344 {ACPI_RSC_2BITFLAG
, ACPI_RS_OFFSET (Data
.Dma
.Transfer
),
345 AML_OFFSET (Dma
.Flags
),
348 {ACPI_RSC_1BITFLAG
, ACPI_RS_OFFSET (Data
.Dma
.BusMaster
),
349 AML_OFFSET (Dma
.Flags
),
352 {ACPI_RSC_2BITFLAG
, ACPI_RS_OFFSET (Data
.Dma
.Type
),
353 AML_OFFSET (Dma
.Flags
),
356 /* DMA channel mask bits */
358 {ACPI_RSC_BITMASK
, ACPI_RS_OFFSET (Data
.Dma
.Channels
[0]),
359 AML_OFFSET (Dma
.DmaChannelMask
),
360 ACPI_RS_OFFSET (Data
.Dma
.ChannelCount
)}
364 /*******************************************************************************
366 * AcpiRsConvertFixedDma
368 ******************************************************************************/
370 ACPI_RSCONVERT_INFO AcpiRsConvertFixedDma
[4] =
372 {ACPI_RSC_INITGET
, ACPI_RESOURCE_TYPE_FIXED_DMA
,
373 ACPI_RS_SIZE (ACPI_RESOURCE_FIXED_DMA
),
374 ACPI_RSC_TABLE_SIZE (AcpiRsConvertFixedDma
)},
376 {ACPI_RSC_INITSET
, ACPI_RESOURCE_NAME_FIXED_DMA
,
377 sizeof (AML_RESOURCE_FIXED_DMA
),
381 * These fields are contiguous in both the source and destination:
385 {ACPI_RSC_MOVE16
, ACPI_RS_OFFSET (Data
.FixedDma
.RequestLines
),
386 AML_OFFSET (FixedDma
.RequestLines
),
389 {ACPI_RSC_MOVE8
, ACPI_RS_OFFSET (Data
.FixedDma
.Width
),
390 AML_OFFSET (FixedDma
.Width
),