drivers/bus/isapnp/isapnp.h

   1 #ifndef __ISAPNP_H
   2 #define __ISAPNP_H
   3
   4 #include <ntddk.h>
   5
   6 #ifdef __cplusplus
   7 extern "C" {
   8 #endif
   9
  10 #define TAG_ISAPNP 'PNPI'
  11
  12 #define IO_RESOURCE_REQUIRED  0x00  //ROS Extension
  13
  14 #define ISAPNP_ADDRESS_PORT   0x0279    // ADDRESS (W)
  15 #define ISAPNP_WRITE_PORT     0x0A79    // WRITE_DATA (W)
  16 #define ISAPNP_MIN_READ_PORT  0x0203    // READ_DATA (R)
  17 #define ISAPNP_MAX_READ_PORT  0x03FF    // READ_DATA (R)
  18
  19 // Card control registers
  20 #define ISAPNP_CARD_READ_DATA_PORT   0x00  // Set READ_DATA port
  21 #define ISAPNP_CARD_ISOLATION        0x01  // Isolation
  22 #define ISAPNP_CARD_CONFIG_COTROL    0x02  // Configuration control
  23 #define ISAPNP_CARD_WAKECSN          0x03  // Wake[CSN]
  24 #define ISAPNP_CARD_RESOUCE_DATA     0x04  // Resource data port
  25 #define ISAPNP_CARD_STATUS           0x05  // Status port
  26 #define ISAPNP_CARD_CSN              0x06  // Card Select Number port
  27 #define ISAPNP_CARD_LOG_DEVICE_NUM   0x07  // Logical Device Number
  28 #define ISAPNP_CARD_RESERVED         0x08  // Card level reserved
  29 #define ISAPNP_CARD_VENDOR_DEFINED   0x20  // Vendor defined
  30
  31 // Logical device control registers
  32 #define ISAPNP_CONTROL_ACTIVATE         0x30  // Activate logical device
  33 #define ISAPNP_CONTROL_IO_RANGE_CHECK   0x31  // I/O range conflict check
  34 #define ISAPNP_CONTROL_LDC_RESERVED     0x32  // Logical Device Control reserved
  35 #define ISAPNP_CONTROL_LDCV_RESERVED    0x38  // Logical Device Control Vendor reserved
  36
  37 // Logical device configuration registers
  38 #define ISAPNP_CONFIG_MEMORY_BASE2    0x00  // Memory base address bits 23-16
  39 #define ISAPNP_CONFIG_MEMORY_BASE1    0x01  // Memory base address bits 15-8
  40 #define ISAPNP_CONFIG_MEMORY_CONTROL  0x02  // Memory control
  41 #define ISAPNP_CONFIG_MEMORY_LIMIT2   0x03  // Memory limit bits 23-16
  42 #define ISAPNP_CONFIG_MEMORY_LIMIT1   0x04  // Memory limit bits 15-8
  43
  44 #define ISAPNP_CONFIG_MEMORY_DESC0    0x40  // Memory descriptor 0
  45 #define ISAPNP_CONFIG_MEMORY_DESC1    0x48  // Memory descriptor 1
  46 #define ISAPNP_CONFIG_MEMORY_DESC2    0x50  // Memory descriptor 2
  47 #define ISAPNP_CONFIG_MEMORY_DESC3    0x58  // Memory descriptor 3
  48
  49 #define ISAPNP_CONFIG_MEMORY32_BASE3    0x00  // 32-bit memory base address bits 31-24
  50 #define ISAPNP_CONFIG_MEMORY32_BASE2    0x01  // 32-bit memory base address bits 23-16
  51 #define ISAPNP_CONFIG_MEMORY32_BASE1    0x01  // 32-bit memory base address bits 15-8
  52 #define ISAPNP_CONFIG_MEMORY32_CONTROL  0x02  // 32-bit memory control
  53 #define ISAPNP_CONFIG_MEMORY32_LIMIT3   0x03  // 32-bit memory limit bits 31-24
  54 #define ISAPNP_CONFIG_MEMORY32_LIMIT2   0x04  // 32-bit memory limit bits 23-16
  55 #define ISAPNP_CONFIG_MEMORY32_LIMIT1   0x05  // 32-bit memory limit bits 15-8
  56
  57 #define ISAPNP_CONFIG_MEMORY32_DESC0  0x76  // 32-bit memory descriptor 0
  58 #define ISAPNP_CONFIG_MEMORY32_DESC1  0x80  // 32-bit memory descriptor 1
  59 #define ISAPNP_CONFIG_MEMORY32_DESC2  0x90  // 32-bit memory descriptor 2
  60 #define ISAPNP_CONFIG_MEMORY32_DESC3  0xA0  // 32-bit memory descriptor 3
  61
  62 #define ISAPNP_CONFIG_IO_BASE1        0x00  // I/O port base address bits 15-8
  63 #define ISAPNP_CONFIG_IO_BASE0        0x01  // I/O port base address bits 7-0
  64
  65 #define ISAPNP_CONFIG_IO_DESC0    0x60  // I/O port descriptor 0
  66 #define ISAPNP_CONFIG_IO_DESC1    0x62  // I/O port descriptor 1
  67 #define ISAPNP_CONFIG_IO_DESC2    0x64  // I/O port descriptor 2
  68 #define ISAPNP_CONFIG_IO_DESC3    0x66  // I/O port descriptor 3
  69 #define ISAPNP_CONFIG_IO_DESC4    0x68  // I/O port descriptor 4
  70 #define ISAPNP_CONFIG_IO_DESC5    0x6A  // I/O port descriptor 5
  71 #define ISAPNP_CONFIG_IO_DESC6    0x6C  // I/O port descriptor 6
  72 #define ISAPNP_CONFIG_IO_DESC7    0x6E  // I/O port descriptor 7
  73
  74 #define ISAPNP_CONFIG_IRQ_LEVEL0    0x70  // Interupt level for descriptor 0
  75 #define ISAPNP_CONFIG_IRQ_TYPE0     0x71  // Type level for descriptor 0
  76 #define ISAPNP_CONFIG_IRQ_LEVEL1    0x72  // Interupt level for descriptor 1
  77 #define ISAPNP_CONFIG_IRQ_TYPE1     0x73  // Type level for descriptor 1
  78
  79 #define ISAPNP_CONFIG_DMA_CHANNEL0    0x74  // DMA channel for descriptor 0
  80 #define ISAPNP_CONFIG_DMA_CHANNEL1    0x75  // DMA channel for descriptor 1
  81
  82
  83 typedef struct _PNPISA_SERIAL_ID
  84 {
  85   UCHAR VendorId[4];    // Vendor Identifier
  86   UCHAR SerialId[4];    // Serial number
  87   UCHAR Checksum;       // Checksum
  88 } PNPISA_SERIAL_ID, *PPNPISA_SERIAL_ID;
  89
  90
  91 #define ISAPNP_RES_PRIORITY_PREFERRED   0
  92 #define ISAPNP_RES_PRIORITY_ACCEPTABLE  1
  93 #define ISAPNP_RES_PRIORITY_FUNCTIONAL  2
  94 #define ISAPNP_RES_PRIORITY_INVALID         65535
  95
  96
  97 #define ISAPNP_RESOURCE_ITEM_TYPE   0x80      // 0 = small, 1 = large
  98
  99 // Small Resource Item Names (SRINs)
 100 #define ISAPNP_SRIN_VERSION           0x1   // PnP version number
 101 #define ISAPNP_SRIN_LDEVICE_ID        0x2   // Logical device id
 102 #define ISAPNP_SRIN_CDEVICE_ID        0x3   // Compatible device id
 103 #define ISAPNP_SRIN_IRQ_FORMAT        0x4   // IRQ format
 104 #define ISAPNP_SRIN_DMA_FORMAT        0x5   // DMA format
 105 #define ISAPNP_SRIN_START_DFUNCTION   0x6   // Start dependant function
 106 #define ISAPNP_SRIN_END_DFUNCTION     0x7   // End dependant function
 107 #define ISAPNP_SRIN_IO_DESCRIPTOR     0x8   // I/O port descriptor
 108 #define ISAPNP_SRIN_FL_IO_DESCRIPOTOR 0x9   // Fixed location I/O port descriptor
 109 #define ISAPNP_SRIN_VENDOR_DEFINED    0xE   // Vendor defined
 110 #define ISAPNP_SRIN_END_TAG           0xF   // End tag
 111
 112 typedef struct _ISAPNP_SRI_VERSION
 113 {
 114   UCHAR Header;
 115   UCHAR Version;        // Packed BCD format version number
 116   UCHAR VendorVersion;  // Vendor specific version number
 117 } ISAPNP_SRI_VERSION, *PISAPNP_SRI_VERSION;
 118
 119 typedef struct _ISAPNP_SRI_LDEVICE_ID
 120 {
 121   UCHAR Header;
 122   USHORT DeviceId;    // Logical device id
 123   USHORT VendorId;    // Manufacturer id
 124   UCHAR Flags;        // Flags
 125 } ISAPNP_SRI_LDEVICE_ID, *PISAPNP_SRI_LDEVICE_ID;
 126
 127 typedef struct _ISAPNP_SRI_CDEVICE_ID
 128 {
 129   UCHAR Header;
 130   USHORT DeviceId;    // Logical device id
 131   USHORT VendorId;    // Manufacturer id
 132 } ISAPNP_SRI_CDEVICE_ID, *PISAPNP_SRI_CDEVICE_ID;
 133
 134 typedef struct _ISAPNP_SRI_IRQ_FORMAT
 135 {
 136   UCHAR Header;
 137   USHORT Mask;          // IRQ mask (bit 0 = irq 0, etc.)
 138   UCHAR Information;    // IRQ information
 139 } ISAPNP_SRI_IRQ_FORMAT, *PISAPNP_SRI_IRQ_FORMAT;
 140
 141 typedef struct _ISAPNP_SRI_DMA_FORMAT
 142 {
 143   UCHAR Header;
 144   USHORT Mask;          // DMA channel mask (bit 0 = channel 0, etc.)
 145   UCHAR  Information;   // DMA information
 146 } ISAPNP_SRI_DMA_FORMAT, *PISAPNP_SRI_DMA_FORMAT;
 147
 148 typedef struct _ISAPNP_SRI_START_DFUNCTION
 149 {
 150   UCHAR Header;
 151 } ISAPNP_SRI_START_DFUNCTION, *PISAPNP_SRI_START_DFUNCTION;
 152
 153 typedef struct _ISAPNP_SRI_END_DFUNCTION
 154 {
 155   UCHAR Header;
 156 } ISAPNP_SRI_END_DFUNCTION, *PISAPNP_SRI_END_DFUNCTION;
 157
 158 typedef struct _ISAPNP_SRI_IO_DESCRIPTOR
 159 {
 160   UCHAR Header;
 161   UCHAR Information;    // Information
 162   USHORT RangeMinBase;  // Minimum base address
 163   USHORT RangeMaxBase;  // Maximum base address
 164   UCHAR Alignment;      // Base alignment
 165   UCHAR RangeLength;    // Length of range
 166 } ISAPNP_SRI_IO_DESCRIPTOR, *PISAPNP_SRI_IO_DESCRIPTOR;
 167
 168 typedef struct _ISAPNP_SRI_FL_IO_DESCRIPTOR
 169 {
 170   UCHAR Header;
 171   USHORT RangeBase;     // Range base address
 172   UCHAR RangeLength;    // Length of range
 173 } ISAPNP_SRI_FL_IO_DESCRIPTOR, *PISAPNP_SRI_FL_IO_DESCRIPTOR;
 174
 175 typedef struct _PISAPNP_SRI_VENDOR_DEFINED
 176 {
 177   UCHAR Header;
 178   UCHAR Reserved[0];  // Vendor defined
 179 } ISAPNP_SRI_VENDOR_DEFINED, *PISAPNP_SRI_VENDOR_DEFINED;
 180
 181 typedef struct _ISAPNP_SRI_END_TAG
 182 {
 183   UCHAR Header;
 184   UCHAR Checksum;   // Checksum
 185 } ISAPNP_SRI_END_TAG, *PISAPNP_SRI_END_TAG;
 186
 187
 188 typedef struct _ISAPNP_LRI
 189 {
 190   UCHAR Header;
 191   USHORT Length;    // Length of data items
 192 } ISAPNP_LRI, *PISAPNP_LRI;
 193
 194 // Large Resource Item Names (LRINs)
 195 #define ISAPNP_LRIN_MEMORY_RANGE      0x1   // Memory range descriptor
 196 #define ISAPNP_LRIN_ID_STRING_ANSI    0x2   // Identifier string (ANSI)
 197 #define ISAPNP_LRIN_ID_STRING_UNICODE 0x3   // Identifier string (UNICODE)
 198 #define ISAPNP_LRIN_VENDOR_DEFINED    0x4   // Vendor defined
 199 #define ISAPNP_LRIN_MEMORY_RANGE32    0x5   // 32-bit memory range descriptor
 200 #define ISAPNP_LRIN_FL_MEMORY_RANGE32 0x6   // 32-bit fixed location memory range descriptor
 201
 202 typedef struct _ISAPNP_LRI_MEMORY_RANGE
 203 {
 204   UCHAR Header;
 205   USHORT Length;        // Length of data items
 206   UCHAR Information;    // Information
 207   USHORT RangeMinBase;  // Minimum base address
 208   USHORT RangeMaxBase;  // Maximum base address
 209   USHORT Alignment;     // Base alignment
 210   USHORT RangeLength;   // Length of range
 211 } ISAPNP_LRI_MEMORY_RANGE, *PISAPNP_LRI_MEMORY_RANGE;
 212
 213 typedef struct _ISAPNP_LRI_ID_STRING_ANSI
 214 {
 215   UCHAR Header;
 216   USHORT Length;        // Length of data items
 217   UCHAR String[0];      // Identifier string
 218 } ISAPNP_LRI_ID_STRING_ANSI, *PISAPNP_LRI_ID_STRING_ANSI;
 219
 220 typedef struct _ISAPNP_LRI_ID_STRING_UNICODE
 221 {
 222   UCHAR Header;
 223   USHORT Length;        // Length of data items
 224   USHORT CountryId;     // Country identifier
 225   USHORT String[0];     // Identifier string
 226 } ISAPNP_LRI_ID_STRING_UNICODE, *PISAPNP_LRI_ID_STRING_UNICODE;
 227
 228 typedef struct _PISAPNP_LRI_VENDOR_DEFINED
 229 {
 230   UCHAR Header;
 231   USHORT Length;        // Length of data items
 232   UCHAR Reserved[0];    // Vendor defined
 233 } ISAPNP_LRI_VENDOR_DEFINED, *PISAPNP_LRI_VENDOR_DEFINED;
 234
 235 typedef struct _ISAPNP_LRI_MEMORY_RANGE32
 236 {
 237   UCHAR Header;
 238   USHORT Length;        // Length of data items
 239   UCHAR Information;    // Information
 240   ULONG RangeMinBase;   // Minimum base address
 241   ULONG RangeMaxBase;   // Maximum base address
 242   ULONG Alignment;      // Base alignment
 243   ULONG RangeLength;    // Length of range
 244 } ISAPNP_LRI_MEMORY_RANGE32, *PISAPNP_LRI_MEMORY_RANGE32;
 245
 246 typedef struct _ISAPNP_LRI_FL_MEMORY_RANGE32
 247 {
 248   UCHAR Header;
 249   USHORT Length;        // Length of data items
 250   UCHAR Information;    // Information
 251   ULONG RangeMinBase;   // Minimum base address
 252   ULONG RangeMaxBase;   // Maximum base address
 253   ULONG RangeLength;    // Length of range
 254 } ISAPNP_LRI_FL_MEMORY_RANGE32, *PISAPNP_LRI_FL_MEMORY_RANGE32;
 255
 256 typedef struct _ISAPNP_CARD
 257 {
 258   LIST_ENTRY ListEntry;
 259   USHORT CardId;
 260   USHORT VendorId;
 261   USHORT DeviceId;
 262   ULONG Serial;
 263   UCHAR PNPVersion;
 264   UCHAR ProductVersion;
 265   UNICODE_STRING Name;
 266   LIST_ENTRY LogicalDevices;
 267   KSPIN_LOCK LogicalDevicesLock;
 268 } ISAPNP_CARD, *PISAPNP_CARD;
 269
 270
 271 typedef struct _ISAPNP_DESCRIPTOR
 272 {
 273   LIST_ENTRY ListEntry;
 274   IO_RESOURCE_DESCRIPTOR Descriptor;
 275 } ISAPNP_DESCRIPTOR, *PISAPNP_DESCRIPTOR;
 276
 277 typedef struct _ISAPNP_CONFIGURATION_LIST
 278 {
 279   LIST_ENTRY ListEntry;
 280   ULONG Priority;
 281   LIST_ENTRY ListHead;
 282 } ISAPNP_CONFIGURATION_LIST, *PISAPNP_CONFIGURATION_LIST;
 283
 284
 285 #define MAX_COMPATIBLE_ID   32
 286
 287 typedef struct _ISAPNP_LOGICAL_DEVICE
 288 {
 289   LIST_ENTRY CardListEntry;
 290   LIST_ENTRY DeviceListEntry;
 291   USHORT Number;
 292   USHORT VendorId;
 293   USHORT DeviceId;
 294   USHORT CVendorId[MAX_COMPATIBLE_ID];
 295   USHORT CDeviceId[MAX_COMPATIBLE_ID];
 296   USHORT Regs;
 297   PISAPNP_CARD Card;
 298   UNICODE_STRING Name;
 299   PDEVICE_OBJECT Pdo;
 300   PIO_RESOURCE_REQUIREMENTS_LIST ResourceLists;
 301   LIST_ENTRY Configuration;
 302   ULONG ConfigurationSize;
 303   ULONG DescriptorCount;
 304   ULONG CurrentDescriptorCount;
 305 } ISAPNP_LOGICAL_DEVICE, *PISAPNP_LOGICAL_DEVICE;
 306
 307
 308 typedef enum {
 309   dsStopped,
 310   dsStarted
 311 } ISAPNP_DEVICE_STATE;
 312
 313 typedef struct _ISAPNP_DEVICE_EXTENSION
 314 {
 315   // Physical Device Object
 316   PDEVICE_OBJECT Pdo;
 317   // Lower device object
 318   PDEVICE_OBJECT Ldo;
 319   // List of ISA PnP cards managed by this driver
 320   LIST_ENTRY CardListHead;
 321   // List of devices managed by this driver
 322   LIST_ENTRY DeviceListHead;
 323   // Number of devices managed by this driver
 324   ULONG DeviceListCount;
 325   // Spinlock for the linked lists
 326   KSPIN_LOCK GlobalListLock;
 327   // Current state of the driver
 328   ISAPNP_DEVICE_STATE State;
 329 } ISAPNP_DEVICE_EXTENSION, *PISAPNP_DEVICE_EXTENSION;
 330
 331 NTSTATUS
 332 NTAPI
 333 DriverEntry(
 334   IN PDRIVER_OBJECT DriverObject,
 335   IN PUNICODE_STRING RegistryPath);
 336
 337 #ifdef __cplusplus
 338 }
 339 #endif
 340
 341 #endif  /*  __ISAPNP_H  */