drivers/bus/pci/pcidef.h

   1 /*
   2  *      PCI defines and function prototypes
   3  *      Copyright 1994, Drew Eckhardt
   4  *      Copyright 1997--1999 Martin Mares <mj@suse.cz>
   5  *
   6  *      For more information, please consult the following manuals (look at
   7  *      http://www.pcisig.com/ for how to get them):
   8  *
   9  *      PCI BIOS Specification
  10  *      PCI Local Bus Specification
  11  *      PCI to PCI Bridge Specification
  12  *      PCI System Design Guide
  13  *
  14  *  Ported from linux pci.h to ReactOS by:
  15  *    Casper S. Hornstrup (chorns@users.sourceforge.net)
  16  */
  17
  18 #pragma once
  19
  20 /*
  21  * Under PCI, each device has 256 bytes of configuration address space,
  22  * of which the first 64 bytes are standardized as follows:
  23  */
  24 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  25 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  26 #define PCI_COMMAND             0x04    /* 16 bits */
  27 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  28 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  29 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  30 #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  31 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  32 #define  PCI_COMMAND_VGA_PALETTE 0x20   /* Enable palette snooping */
  33 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  34 #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  35 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  36 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  37
  38 #define PCI_STATUS              0x06    /* 16 bits */
  39 #define  PCI_STATUS_CAP_LIST    0x10    /* Support Capability List */
  40 #define  PCI_STATUS_66MHZ       0x20    /* Support 66 Mhz PCI 2.1 bus */
  41 #define  PCI_STATUS_UDF         0x40    /* Support User Definable Features [obsolete] */
  42 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  43 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  44 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  45 #define  PCI_STATUS_DEVSEL_FAST 0x000
  46 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  47 #define  PCI_STATUS_DEVSEL_SLOW 0x400
  48 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  49 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  50 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  51 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  52 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  53
  54 #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
  55                                            revision */
  56 #define PCI_REVISION_ID         0x08    /* Revision ID */
  57 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  58 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  59
  60 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  61 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  62 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  63 #define  PCI_HEADER_TYPE_NORMAL 0
  64 #define  PCI_HEADER_TYPE_BRIDGE 1
  65 #define  PCI_HEADER_TYPE_CARDBUS 2
  66
  67 #define PCI_BIST                0x0f    /* 8 bits */
  68 #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
  69 #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
  70 #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
  71
  72 /*
  73  * Base addresses specify locations in memory or I/O space.
  74  * Decoded size can be determined by writing a value of
  75  * 0xffffffff to the register, and reading it back.  Only
  76  * 1 bits are decoded.
  77  */
  78 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  79 #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
  80 #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
  81 #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  82 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  83 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
  84 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
  85 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
  86 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  87 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
  88 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
  89 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
  90 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
  91 #define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
  92 #define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
  93 #define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
  94 /* bit 1 is reserved if address_space = 1 */
  95
  96 /* Header type 0 (normal devices) */
  97 #define PCI_CARDBUS_CIS         0x28
  98 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
  99 #define PCI_SUBSYSTEM_ID        0x2e
 100 #define PCI_ROM_ADDRESS         0x30    /* Bits 31..11 are address, 10..1 reserved */
 101 #define  PCI_ROM_ADDRESS_ENABLE 0x01
 102 #define PCI_ROM_ADDRESS_MASK    (~0x7ffUL)
 103
 104 #define PCI_CAPABILITY_LIST     0x34    /* Offset of first capability list entry */
 105
 106 /* 0x35-0x3b are reserved */
 107 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 108 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 109 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 110 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 111
 112 /* Header type 1 (PCI-to-PCI bridges) */
 113 #define PCI_PRIMARY_BUS         0x18    /* Primary bus number */
 114 #define PCI_SECONDARY_BUS       0x19    /* Secondary bus number */
 115 #define PCI_SUBORDINATE_BUS     0x1a    /* Highest bus number behind the bridge */
 116 #define PCI_SEC_LATENCY_TIMER   0x1b    /* Latency timer for secondary interface */
 117 #define PCI_IO_BASE             0x1c    /* I/O range behind the bridge */
 118 #define PCI_IO_LIMIT            0x1d
 119 #define  PCI_IO_RANGE_TYPE_MASK 0x0f    /* I/O bridging type */
 120 #define  PCI_IO_RANGE_TYPE_16   0x00
 121 #define  PCI_IO_RANGE_TYPE_32   0x01
 122 #define  PCI_IO_RANGE_MASK      ~0x0f
 123 #define PCI_SEC_STATUS          0x1e    /* Secondary status register, only bit 14 used */
 124 #define PCI_MEMORY_BASE         0x20    /* Memory range behind */
 125 #define PCI_MEMORY_LIMIT        0x22
 126 #define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
 127 #define  PCI_MEMORY_RANGE_MASK  ~0x0f
 128 #define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
 129 #define PCI_PREF_MEMORY_LIMIT   0x26
 130 #define  PCI_PREF_RANGE_TYPE_MASK 0x0f
 131 #define  PCI_PREF_RANGE_TYPE_32 0x00
 132 #define  PCI_PREF_RANGE_TYPE_64 0x01
 133 #define  PCI_PREF_RANGE_MASK    ~0x0f
 134 #define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
 135 #define PCI_PREF_LIMIT_UPPER32  0x2c
 136 #define PCI_IO_BASE_UPPER16     0x30    /* Upper half of I/O addresses */
 137 #define PCI_IO_LIMIT_UPPER16    0x32
 138 /* 0x34 same as for htype 0 */
 139 /* 0x35-0x3b is reserved */
 140 #define PCI_ROM_ADDRESS1        0x38    /* Same as PCI_ROM_ADDRESS, but for htype 1 */
 141 /* 0x3c-0x3d are same as for htype 0 */
 142 #define PCI_BRIDGE_CONTROL      0x3e
 143 #define  PCI_BRIDGE_CTL_PARITY  0x01    /* Enable parity detection on secondary interface */
 144 #define  PCI_BRIDGE_CTL_SERR    0x02    /* The same for SERR forwarding */
 145 #define  PCI_BRIDGE_CTL_NO_ISA  0x04    /* Disable bridging of ISA ports */
 146 #define  PCI_BRIDGE_CTL_VGA     0x08    /* Forward VGA addresses */
 147 #define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
 148 #define  PCI_BRIDGE_CTL_BUS_RESET 0x40  /* Secondary bus reset */
 149 #define  PCI_BRIDGE_CTL_FAST_BACK 0x80  /* Fast Back2Back enabled on secondary interface */
 150
 151 /* Header type 2 (CardBus bridges) */
 152 #define PCI_CB_CAPABILITY_LIST  0x14
 153 /* 0x15 reserved */
 154 #define PCI_CB_SEC_STATUS       0x16    /* Secondary status */
 155 #define PCI_CB_PRIMARY_BUS      0x18    /* PCI bus number */
 156 #define PCI_CB_CARD_BUS         0x19    /* CardBus bus number */
 157 #define PCI_CB_SUBORDINATE_BUS  0x1a    /* Subordinate bus number */
 158 #define PCI_CB_LATENCY_TIMER    0x1b    /* CardBus latency timer */
 159 #define PCI_CB_MEMORY_BASE_0    0x1c
 160 #define PCI_CB_MEMORY_LIMIT_0   0x20
 161 #define PCI_CB_MEMORY_BASE_1    0x24
 162 #define PCI_CB_MEMORY_LIMIT_1   0x28
 163 #define PCI_CB_IO_BASE_0        0x2c
 164 #define PCI_CB_IO_BASE_0_HI     0x2e
 165 #define PCI_CB_IO_LIMIT_0       0x30
 166 #define PCI_CB_IO_LIMIT_0_HI    0x32
 167 #define PCI_CB_IO_BASE_1        0x34
 168 #define PCI_CB_IO_BASE_1_HI     0x36
 169 #define PCI_CB_IO_LIMIT_1       0x38
 170 #define PCI_CB_IO_LIMIT_1_HI    0x3a
 171 #define  PCI_CB_IO_RANGE_MASK   ~0x03
 172 /* 0x3c-0x3d are same as for htype 0 */
 173 #define PCI_CB_BRIDGE_CONTROL   0x3e
 174 #define  PCI_CB_BRIDGE_CTL_PARITY       0x01    /* Similar to standard bridge control register */
 175 #define  PCI_CB_BRIDGE_CTL_SERR         0x02
 176 #define  PCI_CB_BRIDGE_CTL_ISA          0x04
 177 #define  PCI_CB_BRIDGE_CTL_VGA          0x08
 178 #define  PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
 179 #define  PCI_CB_BRIDGE_CTL_CB_RESET     0x40    /* CardBus reset */
 180 #define  PCI_CB_BRIDGE_CTL_16BIT_INT    0x80    /* Enable interrupt for 16-bit cards */
 181 #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100  /* Prefetch enable for both memory regions */
 182 #define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
 183 #define  PCI_CB_BRIDGE_CTL_POST_WRITES  0x400
 184 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
 185 #define PCI_CB_SUBSYSTEM_ID     0x42
 186 #define PCI_CB_LEGACY_MODE_BASE 0x44    /* 16-bit PC Card legacy mode base address (ExCa) */
 187 /* 0x48-0x7f reserved */
 188
 189 /* Capability lists */
 190
 191 #define PCI_CAP_LIST_ID         0       /* Capability ID */
 192 #define  PCI_CAP_ID_PM          0x01    /* Power Management */
 193 #define  PCI_CAP_ID_AGP         0x02    /* Accelerated Graphics Port */
 194 #define  PCI_CAP_ID_VPD         0x03    /* Vital Product Data */
 195 #define  PCI_CAP_ID_SLOTID      0x04    /* Slot Identification */
 196 #define  PCI_CAP_ID_MSI         0x05    /* Message Signalled Interrupts */
 197 #define  PCI_CAP_ID_CHSWP       0x06    /* CompactPCI HotSwap */
 198 #define PCI_CAP_LIST_NEXT       1       /* Next capability in the list */
 199 #define PCI_CAP_FLAGS           2       /* Capability defined flags (16 bits) */
 200 #define PCI_CAP_SIZEOF          4
 201
 202 /* Power Management Registers */
 203
 204 #define PCI_PM_PMC              2       /* PM Capabilities Register */
 205 #define  PCI_PM_CAP_VER_MASK    0x0007  /* Version */
 206 #define  PCI_PM_CAP_PME_CLOCK   0x0008  /* PME clock required */
 207 #define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
 208 #define  PCI_PM_CAP_DSI         0x0020  /* Device specific initialization */
 209 #define  PCI_PM_CAP_AUX_POWER   0x01C0  /* Auxilliary power support mask */
 210 #define  PCI_PM_CAP_D1          0x0200  /* D1 power state support */
 211 #define  PCI_PM_CAP_D2          0x0400  /* D2 power state support */
 212 #define  PCI_PM_CAP_PME         0x0800  /* PME pin supported */
 213 #define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
 214 #define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
 215 #define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
 216 #define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
 217 #define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
 218 #define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
 219 #define PCI_PM_CTRL             4       /* PM control and status register */
 220 #define  PCI_PM_CTRL_STATE_MASK 0x0003  /* Current power state (D0 to D3) */
 221 #define  PCI_PM_CTRL_PME_ENABLE 0x0100  /* PME pin enable */
 222 #define  PCI_PM_CTRL_DATA_SEL_MASK      0x1e00  /* Data select (??) */
 223 #define  PCI_PM_CTRL_DATA_SCALE_MASK    0x6000  /* Data scale (??) */
 224 #define  PCI_PM_CTRL_PME_STATUS 0x8000  /* PME pin status */
 225 #define PCI_PM_PPB_EXTENSIONS   6       /* PPB support extensions (??) */
 226 #define  PCI_PM_PPB_B2_B3       0x40    /* Stop clock when in D3hot (??) */
 227 #define  PCI_PM_BPCC_ENABLE     0x80    /* Bus power/clock control enable (??) */
 228 #define PCI_PM_DATA_REGISTER    7       /* (??) */
 229 #define PCI_PM_SIZEOF           8
 230
 231 /* AGP registers */
 232
 233 #define PCI_AGP_VERSION         2       /* BCD version number */
 234 #define PCI_AGP_RFU             3       /* Rest of capability flags */
 235 #define PCI_AGP_STATUS          4       /* Status register */
 236 #define  PCI_AGP_STATUS_RQ_MASK 0xff000000      /* Maximum number of requests - 1 */
 237 #define  PCI_AGP_STATUS_SBA     0x0200  /* Sideband addressing supported */
 238 #define  PCI_AGP_STATUS_64BIT   0x0020  /* 64-bit addressing supported */
 239 #define  PCI_AGP_STATUS_FW      0x0010  /* FW transfers supported */
 240 #define  PCI_AGP_STATUS_RATE4   0x0004  /* 4x transfer rate supported */
 241 #define  PCI_AGP_STATUS_RATE2   0x0002  /* 2x transfer rate supported */
 242 #define  PCI_AGP_STATUS_RATE1   0x0001  /* 1x transfer rate supported */
 243 #define PCI_AGP_COMMAND         8       /* Control register */
 244 #define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
 245 #define  PCI_AGP_COMMAND_SBA    0x0200  /* Sideband addressing enabled */
 246 #define  PCI_AGP_COMMAND_AGP    0x0100  /* Allow processing of AGP transactions */
 247 #define  PCI_AGP_COMMAND_64BIT  0x0020  /* Allow processing of 64-bit addresses */
 248 #define  PCI_AGP_COMMAND_FW     0x0010  /* Force FW transfers */
 249 #define  PCI_AGP_COMMAND_RATE4  0x0004  /* Use 4x rate */
 250 #define  PCI_AGP_COMMAND_RATE2  0x0002  /* Use 4x rate */
 251 #define  PCI_AGP_COMMAND_RATE1  0x0001  /* Use 4x rate */
 252 #define PCI_AGP_SIZEOF          12
 253
 254 /* Slot Identification */
 255
 256 #define PCI_SID_ESR             2       /* Expansion Slot Register */
 257 #define  PCI_SID_ESR_NSLOTS     0x1f    /* Number of expansion slots available */
 258 #define  PCI_SID_ESR_FIC        0x20    /* First In Chassis Flag */
 259 #define PCI_SID_CHASSIS_NR      3       /* Chassis Number */
 260
 261 /* Message Signalled Interrupts registers */
 262
 263 #define PCI_MSI_FLAGS           2       /* Various flags */
 264 #define  PCI_MSI_FLAGS_64BIT    0x80    /* 64-bit addresses allowed */
 265 #define  PCI_MSI_FLAGS_QSIZE    0x70    /* Message queue size configured */
 266 #define  PCI_MSI_FLAGS_QMASK    0x0e    /* Maximum queue size available */
 267 #define  PCI_MSI_FLAGS_ENABLE   0x01    /* MSI feature enabled */
 268 #define PCI_MSI_RFU             3       /* Rest of capability flags */
 269 #define PCI_MSI_ADDRESS_LO      4       /* Lower 32 bits */
 270 #define PCI_MSI_ADDRESS_HI      8       /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
 271 #define PCI_MSI_DATA_32         8       /* 16 bits of data for 32-bit devices */
 272 #define PCI_MSI_DATA_64         12      /* 16 bits of data for 64-bit devices */
 273
 274 /*
 275  * The PCI interface treats multi-function devices as independent
 276  * devices.  The slot/function address of each device is encoded
 277  * in a single byte as follows:
 278  *
 279  *      7:3 = slot
 280  *      2:0 = function
 281  */
 282 #define PCI_DEVFN(slot,func)    ((((slot) & 0x1f) << 3) | ((func) & 0x07))
 283 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
 284 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
 285
 286
 287 /*
 288  *  For PCI devices, the region numbers are assigned this way:
 289  *
 290  *      0-5     standard PCI regions
 291  *      6       expansion ROM
 292  *      7-10    bridges: address space assigned to buses behind the bridge
 293  */
 294
 295 #define PCI_ROM_RESOURCE 6
 296 #define PCI_BRIDGE_RESOURCES 7
 297 #define PCI_NUM_RESOURCES 11
 298
 299 #define PCI_REGION_FLAG_MASK 0x0f       /* These bits of resource flags tell us the PCI region flags */