projects / reactos.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
- Update to r53061
[reactos.git] / drivers / bus / pcix / enum.c
1 /*
2 * PROJECT: ReactOS PCI Bus Driver
3 * LICENSE: BSD - See COPYING.ARM in the top level directory
4 * FILE: drivers/bus/pci/enum.c
5 * PURPOSE: PCI Bus/Device Enumeration
6 * PROGRAMMERS: ReactOS Portable Systems Group
7 */
8
9 /* INCLUDES *******************************************************************/
10
11 #include <pci.h>
12 #define NDEBUG
13 #include <debug.h>
14
15 /* GLOBALS ********************************************************************/
16
17 PIO_RESOURCE_REQUIREMENTS_LIST PciZeroIoResourceRequirements;
18
19 PCI_CONFIGURATOR PciConfigurators[] =
20 {
21 {
22 Device_MassageHeaderForLimitsDetermination,
23 Device_RestoreCurrent,
24 Device_SaveLimits,
25 Device_SaveCurrentSettings,
26 Device_ChangeResourceSettings,
27 Device_GetAdditionalResourceDescriptors,
28 Device_ResetDevice
29 },
30 {
31 PPBridge_MassageHeaderForLimitsDetermination,
32 PPBridge_RestoreCurrent,
33 PPBridge_SaveLimits,
34 PPBridge_SaveCurrentSettings,
35 PPBridge_ChangeResourceSettings,
36 PPBridge_GetAdditionalResourceDescriptors,
37 PPBridge_ResetDevice
38 },
39 {
40 Cardbus_MassageHeaderForLimitsDetermination,
41 Cardbus_RestoreCurrent,
42 Cardbus_SaveLimits,
43 Cardbus_SaveCurrentSettings,
44 Cardbus_ChangeResourceSettings,
45 Cardbus_GetAdditionalResourceDescriptors,
46 Cardbus_ResetDevice
47 }
48 };
49
50 /* FUNCTIONS ******************************************************************/
51
52 BOOLEAN
53 NTAPI
54 PciComputeNewCurrentSettings(IN PPCI_PDO_EXTENSION PdoExtension,
55 IN PCM_RESOURCE_LIST ResourceList)
56 {
57 PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial, InterruptResource;
58 PCM_PARTIAL_RESOURCE_DESCRIPTOR BaseResource, CurrentDescriptor;
59 PCM_PARTIAL_RESOURCE_DESCRIPTOR PreviousDescriptor;
60 CM_PARTIAL_RESOURCE_DESCRIPTOR ResourceArray[7];
61 PCM_FULL_RESOURCE_DESCRIPTOR FullList;
62 BOOLEAN DrainPartial, RangeChange;
63 ULONG i, j;
64 PPCI_FUNCTION_RESOURCES PciResources;
65 PAGED_CODE();
66
67 /* Make sure we have either no resources, or at least one */
68 ASSERT((ResourceList == NULL) || (ResourceList->Count == 1));
69
70 /* Initialize no partial, interrupt descriptor, or range change */
71 Partial = NULL;
72 InterruptResource = NULL;
73 RangeChange = FALSE;
74
75 /* Check if there's not actually any resources */
76 if (!(ResourceList) || !(ResourceList->Count))
77 {
78 /* Then just return the hardware update state */
79 return PdoExtension->UpdateHardware;
80 }
81
82 /* Print the new specified resource list */
83 PciDebugPrintCmResList(ResourceList);
84
85 /* Clear the temporary resource array */
86 for (i = 0; i < 7; i++) ResourceArray[i].Type = CmResourceTypeNull;
87
88 /* Loop the full resource descriptor */
89 FullList = ResourceList->List;
90 for (i = 0; i < ResourceList->Count; i++)
91 {
92 /* Initialize loop variables */
93 DrainPartial = FALSE;
94 BaseResource = NULL;
95
96 /* Loop the partial descriptors */
97 Partial = FullList->PartialResourceList.PartialDescriptors;
98 for (j = 0; j < FullList->PartialResourceList.Count; j++)
99 {
100 /* Check if we were supposed to drain a partial due to device data */
101 if (DrainPartial)
102 {
103 /* Draining complete, move on to the next descriptor then */
104 DrainPartial--;
105 continue;
106 }
107
108 /* Check what kind of descriptor this was */
109 switch (Partial->Type)
110 {
111 /* Base BAR resources */
112 case CmResourceTypePort:
113 case CmResourceTypeMemory:
114
115 /* Set it as the base */
116 ASSERT(BaseResource == NULL);
117 BaseResource = Partial;
118 break;
119
120 /* Interrupt resource */
121 case CmResourceTypeInterrupt:
122
123 /* Make sure it's a compatible (and the only) PCI interrupt */
124 ASSERT(InterruptResource == NULL);
125 ASSERT(Partial->u.Interrupt.Level == Partial->u.Interrupt.Vector);
126 InterruptResource = Partial;
127
128 /* Only 255 interrupts on x86/x64 hardware */
129 if (Partial->u.Interrupt.Level < 256)
130 {
131 /* Use the passed interrupt line */
132 PdoExtension->AdjustedInterruptLine = Partial->u.Interrupt.Level;
133 }
134 else
135 {
136 /* Invalid vector, so ignore it */
137 PdoExtension->AdjustedInterruptLine = 0;
138 }
139
140 break;
141
142 /* Check for specific device data */
143 case CmResourceTypeDevicePrivate:
144
145 /* Check what kind of data this was */
146 switch (Partial->u.DevicePrivate.Data[0])
147 {
148 /* Not used in the driver yet */
149 case 1:
150 UNIMPLEMENTED;
151 while (TRUE);
152 break;
153
154 /* Not used in the driver yet */
155 case 2:
156 UNIMPLEMENTED;
157 while (TRUE);
158 break;
159
160 /* A drain request */
161 case 3:
162 /* Shouldn't be a base resource, this is a drain */
163 ASSERT(BaseResource == NULL);
164 DrainPartial = Partial->u.DevicePrivate.Data[1];
165 ASSERT(DrainPartial == TRUE);
166 break;
167 }
168 break;
169 }
170
171 /* Move to the next descriptor */
172 Partial = PciNextPartialDescriptor(Partial);
173 }
174
175 /* We should be starting a new list now */
176 ASSERT(BaseResource == NULL);
177 FullList = (PVOID)Partial;
178 }
179
180 /* Check the current assigned PCI resources */
181 PciResources = PdoExtension->Resources;
182 if (!PciResources) return FALSE;
183
184 //if... // MISSING CODE
185 UNIMPLEMENTED;
186 DPRINT1("Missing sanity checking code!\n");
187
188 /* Loop all the PCI function resources */
189 for (i = 0; i < 7; i++)
190 {
191 /* Get the current function resource descriptor, and the new one */
192 CurrentDescriptor = &PciResources->Current[i];
193 Partial = &ResourceArray[i];
194
195 /* Previous is current during the first loop iteration */
196 PreviousDescriptor = &PciResources->Current[(i == 0) ? (0) : (i - 1)];
197
198 /* Check if this new descriptor is different than the old one */
199 if (((Partial->Type != CurrentDescriptor->Type) ||
200 (Partial->Type != CmResourceTypeNull)) &&
201 ((Partial->u.Generic.Start.QuadPart !=
202 CurrentDescriptor->u.Generic.Start.QuadPart) ||
203 (Partial->u.Generic.Length != CurrentDescriptor->u.Generic.Length)))
204 {
205 /* Record a change */
206 RangeChange = TRUE;
207
208 /* Was there a range before? */
209 if (CurrentDescriptor->Type != CmResourceTypeNull)
210 {
211 /* Print it */
212 DbgPrint(" Old range-\n");
213 PciDebugPrintPartialResource(CurrentDescriptor);
214 }
215 else
216 {
217 /* There was no range */
218 DbgPrint(" Previously unset range\n");
219 }
220
221 /* Print new one */
222 DbgPrint(" changed to\n");
223 PciDebugPrintPartialResource(Partial);
224
225 /* Update to new range */
226 CurrentDescriptor->Type = Partial->Type;
227 PreviousDescriptor->u.Generic.Start = Partial->u.Generic.Start;
228 PreviousDescriptor->u.Generic.Length = Partial->u.Generic.Length;
229 CurrentDescriptor = PreviousDescriptor;
230 }
231 }
232
233 /* Either the hardware was updated, or a resource range changed */
234 return ((RangeChange) || (PdoExtension->UpdateHardware));
235 }
236
237 VOID
238 NTAPI
239 PcipUpdateHardware(IN PVOID Context,
240 IN PVOID Context2)
241 {
242 PPCI_PDO_EXTENSION PdoExtension = Context;
243 PPCI_COMMON_HEADER PciData = Context2;
244
245 /* Check if we're allowed to disable decodes */
246 PciData->Command = PdoExtension->CommandEnables;
247 if (!(PdoExtension->HackFlags & PCI_HACK_PRESERVE_COMMAND))
248 {
249 /* Disable all decodes */
250 PciData->Command &= ~(PCI_ENABLE_IO_SPACE |
251 PCI_ENABLE_MEMORY_SPACE |
252 PCI_ENABLE_BUS_MASTER |
253 PCI_ENABLE_WRITE_AND_INVALIDATE);
254 }
255
256 /* Update the device configuration */
257 PciData->Status = 0;
258 PciWriteDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
259
260 /* Turn decodes back on */
261 PciDecodeEnable(PdoExtension, TRUE, &PdoExtension->CommandEnables);
262 }
263
264 VOID
265 NTAPI
266 PciUpdateHardware(IN PPCI_PDO_EXTENSION PdoExtension,
267 IN PPCI_COMMON_HEADER PciData)
268 {
269 PCI_IPI_CONTEXT Context;
270
271 /* Check for critical devices and PCI Debugging devices */
272 if ((PdoExtension->HackFlags & PCI_HACK_CRITICAL_DEVICE) ||
273 (PdoExtension->OnDebugPath))
274 {
275 /* Build the context and send an IPI */
276 Context.RunCount = 1;
277 Context.Barrier = 1;
278 Context.Context = PciData;
279 Context.Function = PcipUpdateHardware;
280 Context.DeviceExtension = PdoExtension;
281 KeIpiGenericCall(PciExecuteCriticalSystemRoutine, (ULONG_PTR)&Context);
282 }
283 else
284 {
285 /* Just to the update inline */
286 PcipUpdateHardware(PdoExtension, PciData);
287 }
288 }
289
290 PIO_RESOURCE_REQUIREMENTS_LIST
291 NTAPI
292 PciAllocateIoRequirementsList(IN ULONG Count,
293 IN ULONG BusNumber,
294 IN ULONG SlotNumber)
295 {
296 SIZE_T Size;
297 PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList;
298
299 /* Calculate the final size of the list, including each descriptor */
300 Size = sizeof(IO_RESOURCE_REQUIREMENTS_LIST);
301 if (Count > 1) Size = sizeof(IO_RESOURCE_DESCRIPTOR) * (Count - 1) +
302 sizeof(IO_RESOURCE_REQUIREMENTS_LIST);
303
304 /* Allocate the list */
305 RequirementsList = ExAllocatePoolWithTag(PagedPool, Size, 'BicP');
306 if (!RequirementsList) return NULL;
307
308 /* Initialize it */
309 RtlZeroMemory(RequirementsList, Size);
310 RequirementsList->AlternativeLists = 1;
311 RequirementsList->BusNumber = BusNumber;
312 RequirementsList->SlotNumber = SlotNumber;
313 RequirementsList->InterfaceType = PCIBus;
314 RequirementsList->ListSize = Size;
315 RequirementsList->List[0].Count = Count;
316 RequirementsList->List[0].Version = 1;
317 RequirementsList->List[0].Revision = 1;
318
319 /* Return it */
320 return RequirementsList;
321 }
322
323 PCM_RESOURCE_LIST
324 NTAPI
325 PciAllocateCmResourceList(IN ULONG Count,
326 IN ULONG BusNumber)
327 {
328 SIZE_T Size;
329 PCM_RESOURCE_LIST ResourceList;
330
331 /* Calculate the final size of the list, including each descriptor */
332 Size = sizeof(CM_RESOURCE_LIST);
333 if (Count > 1) Size = sizeof(CM_PARTIAL_RESOURCE_DESCRIPTOR) * (Count - 1) +
334 sizeof(CM_RESOURCE_LIST);
335
336 /* Allocate the list */
337 ResourceList = ExAllocatePoolWithTag(PagedPool, Size, 'BicP');
338 if (!ResourceList) return NULL;
339
340 /* Initialize it */
341 RtlZeroMemory(ResourceList, Size);
342 ResourceList->Count = 1;
343 ResourceList->List[0].BusNumber = BusNumber;
344 ResourceList->List[0].InterfaceType = PCIBus;
345 ResourceList->List[0].PartialResourceList.Version = 1;
346 ResourceList->List[0].PartialResourceList.Revision = 1;
347 ResourceList->List[0].PartialResourceList.Count = Count;
348
349 /* Return it */
350 return ResourceList;
351 }
352
353 NTSTATUS
354 NTAPI
355 PciQueryResources(IN PPCI_PDO_EXTENSION PdoExtension,
356 OUT PCM_RESOURCE_LIST *Buffer)
357 {
358 PPCI_FUNCTION_RESOURCES PciResources;
359 BOOLEAN HaveVga, HaveMemSpace, HaveIoSpace;
360 USHORT BridgeControl, PciCommand;
361 ULONG Count, i;
362 PCM_PARTIAL_RESOURCE_DESCRIPTOR Partial, Resource, LastResource;
363 PCM_RESOURCE_LIST ResourceList;
364 UCHAR InterruptLine;
365 PAGED_CODE();
366
367 /* Assume failure */
368 Count = 0;
369 HaveVga = FALSE;
370 *Buffer = NULL;
371
372 /* Make sure there's some resources to query */
373 PciResources = PdoExtension->Resources;
374 if (!PciResources) return STATUS_SUCCESS;
375
376 /* Read the decodes */
377 PciReadDeviceConfig(PdoExtension,
378 &PciCommand,
379 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
380 sizeof(USHORT));
381
382 /* Check which ones are turned on */
383 HaveIoSpace = PciCommand & PCI_ENABLE_IO_SPACE;
384 HaveMemSpace = PciCommand & PCI_ENABLE_MEMORY_SPACE;
385
386 /* Loop maximum possible descriptors */
387 for (i = 0; i < 7; i++)
388 {
389 /* Check if the decode for this descriptor is actually turned on */
390 Partial = &PciResources->Current[i];
391 if (((HaveMemSpace) && (Partial->Type == CmResourceTypeMemory)) ||
392 ((HaveIoSpace) && (Partial->Type == CmResourceTypePort)))
393 {
394 /* One more fully active descriptor */
395 Count++;
396 }
397 }
398
399 /* If there's an interrupt pin associated, check at least one decode is on */
400 if ((PdoExtension->InterruptPin) && ((HaveMemSpace) || (HaveIoSpace)))
401 {
402 /* Read the interrupt line for the pin, add a descriptor if it's valid */
403 InterruptLine = PdoExtension->AdjustedInterruptLine;
404 if ((InterruptLine) && (InterruptLine != -1)) Count++;
405 }
406
407 /* Check for PCI bridge */
408 if (PdoExtension->HeaderType == PCI_BRIDGE_TYPE)
409 {
410 /* Read bridge settings, check if VGA is present */
411 PciReadDeviceConfig(PdoExtension,
412 &BridgeControl,
413 FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.BridgeControl),
414 sizeof(USHORT));
415 if (BridgeControl & PCI_ENABLE_BRIDGE_VGA)
416 {
417 /* Remember for later */
418 HaveVga = TRUE;
419
420 /* One memory descriptor for 0xA0000, plus the two I/O port ranges */
421 if (HaveMemSpace) Count++;
422 if (HaveIoSpace) Count += 2;
423 }
424 }
425
426 /* If there's no descriptors in use, there's no resources, so return */
427 if (!Count) return STATUS_SUCCESS;
428
429 /* Allocate a resource list to hold the resources */
430 ResourceList = PciAllocateCmResourceList(Count,
431 PdoExtension->ParentFdoExtension->BaseBus);
432 if (!ResourceList) return STATUS_INSUFFICIENT_RESOURCES;
433
434 /* This is where the descriptors will be copied into */
435 Resource = ResourceList->List[0].PartialResourceList.PartialDescriptors;
436 LastResource = Resource + Count + 1;
437
438 /* Loop maximum possible descriptors */
439 for (i = 0; i < 7; i++)
440 {
441 /* Check if the decode for this descriptor is actually turned on */
442 Partial = &PciResources->Current[i];
443 if (((HaveMemSpace) && (Partial->Type == CmResourceTypeMemory)) ||
444 ((HaveIoSpace) && (Partial->Type == CmResourceTypePort)))
445 {
446 /* Copy the descriptor into the resource list */
447 *Resource++ = *Partial;
448 }
449 }
450
451 /* Check if earlier the code detected this was a PCI bridge with VGA on it */
452 if (HaveVga)
453 {
454 /* Are the memory decodes enabled? */
455 if (HaveMemSpace)
456 {
457 /* Build a memory descriptor for a 128KB framebuffer at 0xA0000 */
458 Resource->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
459 Resource->u.Generic.Start.HighPart = 0;
460 Resource->Type = CmResourceTypeMemory;
461 Resource->u.Generic.Start.LowPart = 0xA0000;
462 Resource->u.Generic.Length = 0x20000;
463 Resource++;
464 }
465
466 /* Are the I/O decodes enabled? */
467 if (HaveIoSpace)
468 {
469 /* Build an I/O descriptor for the graphic ports at 0x3B0 */
470 Resource->Type = CmResourceTypePort;
471 Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
472 Resource->u.Port.Start.QuadPart = 0x3B0u;
473 Resource->u.Port.Length = 0xC;
474 Resource++;
475
476 /* Build an I/O descriptor for the graphic ports at 0x3C0 */
477 Resource->Type = CmResourceTypePort;
478 Resource->Flags = CM_RESOURCE_PORT_POSITIVE_DECODE | CM_RESOURCE_PORT_10_BIT_DECODE;
479 Resource->u.Port.Start.QuadPart = 0x3C0u;
480 Resource->u.Port.Length = 0x20;
481 Resource++;
482 }
483 }
484
485 /* If there's an interrupt pin associated, check at least one decode is on */
486 if ((PdoExtension->InterruptPin) && ((HaveMemSpace) || (HaveIoSpace)))
487 {
488 /* Read the interrupt line for the pin, check if it's valid */
489 InterruptLine = PdoExtension->AdjustedInterruptLine;
490 if ((InterruptLine) && (InterruptLine != -1))
491 {
492 /* Make sure there's still space */
493 ASSERT(Resource < LastResource);
494
495 /* Add the interrupt descriptor */
496 Resource->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
497 Resource->Type = CmResourceTypeInterrupt;
498 Resource->ShareDisposition = CmResourceShareShared;
499 Resource->u.Interrupt.Affinity = -1;
500 Resource->u.Interrupt.Level = InterruptLine;
501 Resource->u.Interrupt.Vector = InterruptLine;
502 }
503 }
504
505 /* Return the resouce list */
506 *Buffer = ResourceList;
507 return STATUS_SUCCESS;
508 }
509
510 NTSTATUS
511 NTAPI
512 PciQueryTargetDeviceRelations(IN PPCI_PDO_EXTENSION PdoExtension,
513 IN OUT PDEVICE_RELATIONS *pDeviceRelations)
514 {
515 PDEVICE_RELATIONS DeviceRelations;
516 PAGED_CODE();
517
518 /* If there were existing relations, free them */
519 if (*pDeviceRelations) ExFreePoolWithTag(*pDeviceRelations, 0);
520
521 /* Allocate a new structure for the relations */
522 DeviceRelations = ExAllocatePoolWithTag(NonPagedPool,
523 sizeof(DEVICE_RELATIONS),
524 'BicP');
525 if (!DeviceRelations) return STATUS_INSUFFICIENT_RESOURCES;
526
527 /* Only one relation: the PDO */
528 DeviceRelations->Count = 1;
529 DeviceRelations->Objects[0] = PdoExtension->PhysicalDeviceObject;
530 ObReferenceObject(DeviceRelations->Objects[0]);
531
532 /* Return the new relations */
533 *pDeviceRelations = DeviceRelations;
534 return STATUS_SUCCESS;
535 }
536
537 NTSTATUS
538 NTAPI
539 PciQueryEjectionRelations(IN PPCI_PDO_EXTENSION PdoExtension,
540 IN OUT PDEVICE_RELATIONS *pDeviceRelations)
541 {
542 /* Not yet implemented */
543 UNIMPLEMENTED;
544 while (TRUE);
545 }
546
547 NTSTATUS
548 NTAPI
549 PciBuildRequirementsList(IN PPCI_PDO_EXTENSION PdoExtension,
550 IN PPCI_COMMON_HEADER PciData,
551 OUT PIO_RESOURCE_REQUIREMENTS_LIST* Buffer)
552 {
553 PIO_RESOURCE_REQUIREMENTS_LIST RequirementsList;
554 {
555 /* There aren't, so use the zero descriptor */
556 RequirementsList = PciZeroIoResourceRequirements;
557
558 /* Does it actually exist yet? */
559 if (!PciZeroIoResourceRequirements)
560 {
561 /* Allocate it, and use it for future use */
562 RequirementsList = PciAllocateIoRequirementsList(0, 0, 0);
563 PciZeroIoResourceRequirements = RequirementsList;
564 if (!PciZeroIoResourceRequirements) return STATUS_INSUFFICIENT_RESOURCES;
565 }
566
567 /* Return the zero requirements list to the caller */
568 *Buffer = RequirementsList;
569 DPRINT1("PCI - build resource reqs - early out, 0 resources\n");
570 return STATUS_SUCCESS;
571 }
572 return STATUS_SUCCESS;
573 }
574
575 NTSTATUS
576 NTAPI
577 PciQueryRequirements(IN PPCI_PDO_EXTENSION PdoExtension,
578 IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *RequirementsList)
579 {
580 NTSTATUS Status;
581 PCI_COMMON_HEADER PciHeader;
582 PAGED_CODE();
583
584 /* Check if the PDO has any resources, or at least an interrupt pin */
585 if ((PdoExtension->Resources) || (PdoExtension->InterruptPin))
586 {
587 /* Read the current PCI header */
588 PciReadDeviceConfig(PdoExtension, &PciHeader, 0, PCI_COMMON_HDR_LENGTH);
589
590 /* Use it to build a list of requirements */
591 Status = PciBuildRequirementsList(PdoExtension, &PciHeader, RequirementsList);
592 if (!NT_SUCCESS(Status)) return Status;
593
594 /* Is this a Compaq PCI Hotplug Controller (r17) on a PAE system ? */
595 if ((PciHeader.VendorID == 0xE11) &&
596 (PciHeader.DeviceID == 0xA0F7) &&
597 (PciHeader.RevisionID == 17) &&
598 (ExIsProcessorFeaturePresent(PF_PAE_ENABLED)))
599 {
600 /* Have not tested this on eVb's machine yet */
601 UNIMPLEMENTED;
602 while (TRUE);
603 }
604
605 /* Check if the requirements are actually the zero list */
606 if (*RequirementsList == PciZeroIoResourceRequirements)
607 {
608 /* A simple NULL will sufficie for the PnP Manager */
609 *RequirementsList = NULL;
610 DPRINT1("Returning NULL requirements list\n");
611 }
612 else
613 {
614 /* Otherwise, print out the requirements list */
615 PciDebugPrintIoResReqList(*RequirementsList);
616 }
617 }
618 else
619 {
620 /* There aren't any resources, so simply return NULL */
621 DPRINT1("PciQueryRequirements returning NULL requirements list\n");
622 *RequirementsList = NULL;
623 }
624
625 /* This call always succeeds (but maybe with no requirements) */
626 return STATUS_SUCCESS;
627 }
628
629 /*
630 * 7. The IO/MEM/Busmaster decodes are disabled for the device.
631 * 8. The PCI bus driver sets the operating mode bits of the Programming
632 * Interface byte to switch the controller to native mode.
633 *
634 * Important: When the controller is set to native mode, it must quiet itself
635 * and must not decode I/O resources or generate interrupts until the operating
636 * system has enabled the ports in the PCI configuration header.
637 * The IO/MEM/BusMaster bits will be disabled before the mode change, but it
638 * is not possible to disable interrupts on the device. The device must not
639 * generate interrupts (either legacy or native mode) while the decodes are
640 * disabled in the command register.
641 *
642 * This operation is expected to be instantaneous and the operating system does
643 * not stall afterward. It is also expected that the interrupt pin register in
644 * the PCI Configuration space for this device is accurate. The operating system
645 * re-reads this data after previously ignoring it.
646 */
647 BOOLEAN
648 NTAPI
649 PciConfigureIdeController(IN PPCI_PDO_EXTENSION PdoExtension,
650 IN PPCI_COMMON_HEADER PciData,
651 IN BOOLEAN Initial)
652 {
653 UCHAR MasterMode, SlaveMode, MasterFixed, SlaveFixed, ProgIf, NewProgIf;
654 BOOLEAN Switched;
655 USHORT Command;
656
657 /* Assume it won't work */
658 Switched = FALSE;
659
660 /* Get master and slave current settings, and programmability flag */
661 ProgIf = PciData->ProgIf;
662 MasterMode = (ProgIf & 1) == 1;
663 MasterFixed = (ProgIf & 2) == 0;
664 SlaveMode = (ProgIf & 4) == 4;
665 SlaveFixed = (ProgIf & 8) == 0;
666
667 /*
668 * [..] In order for Windows XP SP1 and Windows Server 2003 to switch an ATA
669 * ATA controller from compatible mode to native mode, the following must be
670 * true:
671 *
672 * - The controller must indicate in its programming interface that both channels
673 * can be switched to native mode. Windows XP SP1 and Windows Server 2003 do
674 * not support switching only one IDE channel to native mode. See the PCI IDE
675 * Controller Specification Revision 1.0 for details.
676 */
677 if ((MasterMode != SlaveMode) || (MasterFixed != SlaveFixed))
678 {
679 /* Windows does not support this configuration, fail */
680 DPRINT1("PCI: Warning unsupported IDE controller configuration for VEN_%04x&DEV_%04x!",
681 PdoExtension->VendorId,
682 PdoExtension->DeviceId);
683 return Switched;
684 }
685
686 /* Check if the controller is already in native mode */
687 if ((MasterMode) && (SlaveMode))
688 {
689 /* Check if I/O decodes should be disabled */
690 if ((Initial) || (PdoExtension->IoSpaceUnderNativeIdeControl))
691 {
692 /* Read the current command */
693 PciReadDeviceConfig(PdoExtension,
694 &Command,
695 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
696 sizeof(USHORT));
697
698 /* Disable I/O space decode */
699 Command &= ~PCI_ENABLE_IO_SPACE;
700
701 /* Update new command in PCI IDE controller */
702 PciWriteDeviceConfig(PdoExtension,
703 &Command,
704 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
705 sizeof(USHORT));
706
707 /* Save updated command value */
708 PciData->Command = Command;
709 }
710
711 /* The controller is now in native mode */
712 Switched = TRUE;
713 }
714 else if (!(MasterFixed) &&
715 !(SlaveFixed) &&
716 (PdoExtension->BIOSAllowsIDESwitchToNativeMode) &&
717 !(PdoExtension->HackFlags & PCI_HACK_DISABLE_IDE_NATIVE_MODE))
718 {
719 /* Turn off decodes */
720 PciDecodeEnable(PdoExtension, FALSE, NULL);
721
722 /* Update the current command */
723 PciReadDeviceConfig(PdoExtension,
724 &PciData->Command,
725 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
726 sizeof(USHORT));
727
728 /* Enable native mode */
729 ProgIf = PciData->ProgIf | 5;
730 PciWriteDeviceConfig(PdoExtension,
731 &ProgIf,
732 FIELD_OFFSET(PCI_COMMON_HEADER, ProgIf),
733 sizeof(UCHAR));
734
735 /* Verify the setting "stuck" */
736 PciReadDeviceConfig(PdoExtension,
737 &NewProgIf,
738 FIELD_OFFSET(PCI_COMMON_HEADER, ProgIf),
739 sizeof(UCHAR));
740 if (NewProgIf == ProgIf)
741 {
742 /* Update the header and PDO data with the new programming mode */
743 PciData->ProgIf = ProgIf;
744 PdoExtension->ProgIf = NewProgIf;
745
746 /* Clear the first four BARs to reset current BAR setttings */
747 PciData->u.type0.BaseAddresses[0] = 0;
748 PciData->u.type0.BaseAddresses[1] = 0;
749 PciData->u.type0.BaseAddresses[2] = 0;
750 PciData->u.type0.BaseAddresses[3] = 0;
751 PciWriteDeviceConfig(PdoExtension,
752 PciData->u.type0.BaseAddresses,
753 FIELD_OFFSET(PCI_COMMON_HEADER,
754 u.type0.BaseAddresses),
755 4 * sizeof(ULONG));
756
757 /* Re-read the BARs to have the latest data for native mode IDE */
758 PciReadDeviceConfig(PdoExtension,
759 PciData->u.type0.BaseAddresses,
760 FIELD_OFFSET(PCI_COMMON_HEADER,
761 u.type0.BaseAddresses),
762 4 * sizeof(ULONG));
763
764 /* Re-read the interrupt pin used for native mode IDE */
765 PciReadDeviceConfig(PdoExtension,
766 &PciData->u.type0.InterruptPin,
767 FIELD_OFFSET(PCI_COMMON_HEADER,
768 u.type0.InterruptPin),
769 sizeof(UCHAR));
770
771 /* The IDE Controller is now in native mode */
772 Switched = TRUE;
773 }
774 else
775 {
776 /* Settings did not work, fail */
777 DPRINT1("PCI: Warning failed switch to native mode for IDE controller VEN_%04x&DEV_%04x!",
778 PciData->VendorID,
779 PciData->DeviceID);
780 }
781 }
782
783 /* Return whether or not native mode was enabled on the IDE controller */
784 return Switched;
785 }
786
787 VOID
788 NTAPI
789 PciApplyHacks(IN PPCI_FDO_EXTENSION DeviceExtension,
790 IN PPCI_COMMON_HEADER PciData,
791 IN PCI_SLOT_NUMBER SlotNumber,
792 IN ULONG OperationType,
793 PPCI_PDO_EXTENSION PdoExtension)
794 {
795 ULONG LegacyBaseAddress;
796 USHORT Command;
797 UCHAR RegValue;
798
799 /* Check what kind of hack operation this is */
800 switch (OperationType)
801 {
802 /*
803 * This is mostly concerned with fixing up incorrect class data that can
804 * exist on certain PCI hardware before the 2.0 spec was ratified.
805 */
806 case PCI_HACK_FIXUP_BEFORE_CONFIGURATION:
807
808 /* Note that the i82375 PCI/EISA and the i82378 PCI/ISA bridges that
809 * are present on certain DEC/NT Alpha machines are pre-PCI 2.0 devices
810 * and appear as non-classified, so their correct class/subclass data
811 * is written here instead.
812 */
813 if ((PciData->VendorID == 0x8086) &&
814 ((PciData->DeviceID == 0x482) || (PciData->DeviceID == 0x484)))
815 {
816 /* Note that 0x482 is the i82375 (EISA), 0x484 is the i82378 (ISA) */
817 PciData->SubClass = PciData->DeviceID == 0x482 ?
818 PCI_SUBCLASS_BR_EISA : PCI_SUBCLASS_BR_ISA;
819 PciData->BaseClass = PCI_CLASS_BRIDGE_DEV;
820
821 /*
822 * Because the software is modifying the actual header data from
823 * the BIOS, this flag tells the driver to ignore failures when
824 * comparing the original BIOS data with the PCI data.
825 */
826 if (PdoExtension) PdoExtension->ExpectedWritebackFailure = TRUE;
827 }
828
829 /* Note that in this case, an immediate return is issued */
830 return;
831
832 /*
833 * This is concerned with setting up interrupts correctly for native IDE
834 * mode, but will also handle broken VGA decoding on older bridges as
835 * well as a PAE-specific hack for certain Compaq Hot-Plug Controllers.
836 */
837 case PCI_HACK_FIXUP_AFTER_CONFIGURATION:
838
839 /* There should always be a PDO extension passed in */
840 ASSERT(PdoExtension);
841
842 /*
843 * On the OPTi Viper-M IDE controller, Linux doesn't support IDE-DMA
844 * and FreeBSD bug reports indicate that the system crashes when the
845 * feature is enabled (so it's disabled on that OS as well). In the
846 * NT PCI Bus Driver, it seems Microsoft too, completely disables
847 * Native IDE functionality on this controller, so it would seem OPTi
848 * simply frelled up this controller.
849 */
850 if ((PciData->VendorID == 0x1045) && (PciData->DeviceID != 0xC621))
851 {
852 /* Disable native mode */
853 PciData->ProgIf &= ~5;
854 PciData->u.type0.InterruptPin = 0;
855
856 /*
857 * Because the software is modifying the actual header data from
858 * the BIOS, this flag tells the driver to ignore failures when
859 * comparing the original BIOS data with the PCI data.
860 */
861 PdoExtension->ExpectedWritebackFailure = TRUE;
862 }
863 else if ((PciData->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
864 (PciData->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
865 {
866 /* For other IDE controllers, start out in compatible mode */
867 PdoExtension->BIOSAllowsIDESwitchToNativeMode = FALSE;
868
869 /*
870 * Registry must have enabled native mode (typically as a result
871 * of an INF file directive part of the IDE controller's driver)
872 * and the system must not be booted in Safe Mode. If that checks
873 * out, then evaluate the ACPI NATA method to see if the platform
874 * supports this. See the section "BIOS and Platform Prerequisites
875 * for Switching a Native-Mode-Capable Controller" in the Storage
876 * section of the Windows Driver Kit for more details:
877 *
878 * 5. For each ATA controller enumerated, the PCI bus driver checks
879 * the Programming Interface register of the IDE controller to
880 * see if it supports switching both channels to native mode.
881 * 6. The PCI bus driver checks whether the BIOS/platform supports
882 * switching the controller by checking the NATA method described
883 * earlier in this article.
884 *
885 * If an ATA controller does not indicate that it is native
886 * mode-capable, or if the BIOS NATA control method is missing
887 * or does not list that device, the PCI bus driver does not
888 * switch the controller and it is assigned legacy resources.
889 *
890 * If both the controller and the BIOS indicate that the controller
891 * can be switched, the process of switching the controller begins
892 * with the next step.
893 */
894 if ((PciEnableNativeModeATA) &&
895 !(InitSafeBootMode) &&
896 (PciIsSlotPresentInParentMethod(PdoExtension, 'ATAN')))
897 {
898 /* The platform supports it, remember that */
899 PdoExtension->BIOSAllowsIDESwitchToNativeMode = TRUE;
900
901 /*
902 * Now switch the controller into native mode if both channels
903 * support native IDE mode. See "How Windows Switches an ATA
904 * Controller to Native Mode" in the Storage section of the
905 * Windows Driver Kit for more details.
906 */
907 PdoExtension->IDEInNativeMode =
908 PciConfigureIdeController(PdoExtension, PciData, TRUE);
909 }
910
911 /* Is native mode enabled after all? */
912 if ((PciData->ProgIf & 5) != 5)
913 {
914 /* Compatible mode, so force ISA-style IRQ14 and IRQ 15 */
915 PciData->u.type0.InterruptPin = 0;
916 }
917 }
918
919 /* Is this a PCI device with legacy VGA card decodes on the root bus? */
920 if ((PdoExtension->HackFlags & PCI_HACK_VIDEO_LEGACY_DECODE) &&
921 (PCI_IS_ROOT_FDO(DeviceExtension)) &&
922 !(DeviceExtension->BrokenVideoHackApplied))
923 {
924 /* Tell the arbiter to apply a hack for these older devices */
925 ario_ApplyBrokenVideoHack(DeviceExtension);
926 }
927
928 /* Is this a Compaq PCI Hotplug Controller (r17) on a PAE system ? */
929 if ((PciData->VendorID == 0xE11) &&
930 (PciData->DeviceID == 0xA0F7) &&
931 (PciData->RevisionID == 17) &&
932 (ExIsProcessorFeaturePresent(PF_PAE_ENABLED)))
933 {
934 /* Turn off the decodes immediately */
935 PciData->Command &= ~(PCI_ENABLE_IO_SPACE |
936 PCI_ENABLE_MEMORY_SPACE |
937 PCI_ENABLE_BUS_MASTER);
938 PciWriteDeviceConfig(PdoExtension,
939 &PciData->Command,
940 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
941 sizeof(USHORT));
942
943 /* Do not EVER turn them on again, this will blow up the system */
944 PdoExtension->CommandEnables &= ~(PCI_ENABLE_IO_SPACE |
945 PCI_ENABLE_MEMORY_SPACE |
946 PCI_ENABLE_BUS_MASTER);
947 PdoExtension->HackFlags |= PCI_HACK_PRESERVE_COMMAND;
948 }
949 break;
950
951 /*
952 * This is called whenever resources are changed and hardware needs to be
953 * updated. It is concerned with two highly specific erratas on an IBM
954 * hot-plug docking bridge used on the Thinkpad 600 Series and on Intel's
955 * ICH PCI Bridges.
956 */
957 case PCI_HACK_FIXUP_BEFORE_UPDATE:
958
959 /* There should always be a PDO extension passed in */
960 ASSERT(PdoExtension);
961
962 /* Is this an IBM 20H2999 PCI Docking Bridge, used on Thinkpads? */
963 if ((PdoExtension->VendorId == 0x1014) &&
964 (PdoExtension->DeviceId == 0x95))
965 {
966 /* Read the current command */
967 PciReadDeviceConfig(PdoExtension,
968 &Command,
969 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
970 sizeof(USHORT));
971
972 /* Turn off the decodes */
973 PciDecodeEnable(PdoExtension, FALSE, &Command);
974
975 /* Apply the required IBM workaround */
976 PciReadDeviceConfig(PdoExtension, &RegValue, 0xE0, sizeof(UCHAR));
977 RegValue &= ~2;
978 RegValue |= 1;
979 PciWriteDeviceConfig(PdoExtension, &RegValue, 0xE0, sizeof(UCHAR));
980
981 /* Restore the command to its original value */
982 PciWriteDeviceConfig(PdoExtension,
983 &Command,
984 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
985 sizeof(USHORT));
986
987 }
988
989 /*
990 * Check for Intel ICH PCI-to-PCI (i82801) bridges (used on the i810,
991 * i820, i840, i845 Chipsets) that have subtractive decode enabled,
992 * and whose hack flags do not specifiy that this support is broken.
993 */
994 if ((PdoExtension->HeaderType == PCI_BRIDGE_TYPE) &&
995 (PdoExtension->Dependent.type1.SubtractiveDecode) &&
996 ((PdoExtension->VendorId == 0x8086) &&
997 ((PdoExtension->DeviceId == 0x2418) ||
998 (PdoExtension->DeviceId == 0x2428) ||
999 (PdoExtension->DeviceId == 0x244E) ||
1000 (PdoExtension->DeviceId == 0x2448))) &&
1001 !(PdoExtension->HackFlags & PCI_HACK_BROKEN_SUBTRACTIVE_DECODE))
1002 {
1003 /*
1004 * The positive decode window shouldn't be used, these values are
1005 * normally all read-only or initialized to 0 by the BIOS, but
1006 * it appears Intel doesn't do this, so the PCI Bus Driver will
1007 * do it in software instead. Note that this is used to prevent
1008 * certain non-compliant PCI devices from breaking down due to the
1009 * fact that these ICH bridges have a known "quirk" (which Intel
1010 * documents as a known "erratum", although it's not not really
1011 * an ICH bug since the PCI specification does allow for it) in
1012 * that they will sometimes send non-zero addresses during special
1013 * cycles (ie: non-zero data during the address phase). These
1014 * broken PCI cards will mistakenly attempt to claim the special
1015 * cycle and corrupt their I/O and RAM ranges. Again, in Intel's
1016 * defense, the PCI specification only requires stable data, not
1017 * necessarily zero data, during the address phase.
1018 */
1019 PciData->u.type1.MemoryBase = 0xFFFF;
1020 PciData->u.type1.PrefetchBase = 0xFFFF;
1021 PciData->u.type1.IOBase = 0xFF;
1022 PciData->u.type1.IOLimit = 0;
1023 PciData->u.type1.MemoryLimit = 0;
1024 PciData->u.type1.PrefetchLimit = 0;
1025 PciData->u.type1.PrefetchBaseUpper32 = 0;
1026 PciData->u.type1.PrefetchLimitUpper32 = 0;
1027 PciData->u.type1.IOBaseUpper16 = 0;
1028 PciData->u.type1.IOLimitUpper16 = 0;
1029 }
1030 break;
1031
1032 default:
1033 return;
1034 }
1035
1036 /* Finally, also check if this is this a CardBUS device? */
1037 if (PCI_CONFIGURATION_TYPE(PciData) == PCI_CARDBUS_BRIDGE_TYPE)
1038 {
1039 /*
1040 * At offset 44h the LegacyBaseAddress is stored, which is cleared by
1041 * ACPI-aware versions of Windows, to disable legacy-mode I/O access to
1042 * CardBus controllers. For more information, see "Supporting CardBus
1043 * Controllers under ACPI" in the "CardBus Controllers and Windows"
1044 * Whitepaper on WHDC.
1045 */
1046 LegacyBaseAddress = 0;
1047 PciWriteDeviceConfig(PdoExtension,
1048 &LegacyBaseAddress,
1049 sizeof(PCI_COMMON_HEADER) + sizeof(ULONG),
1050 sizeof(ULONG));
1051 }
1052 }
1053
1054 BOOLEAN
1055 NTAPI
1056 PcipIsSameDevice(IN PPCI_PDO_EXTENSION DeviceExtension,
1057 IN PPCI_COMMON_HEADER PciData)
1058 {
1059 BOOLEAN IdMatch, RevMatch, SubsysMatch;
1060 ULONGLONG HackFlags = DeviceExtension->HackFlags;
1061
1062 /* Check if the IDs match */
1063 IdMatch = (PciData->VendorID == DeviceExtension->VendorId) &&
1064 (PciData->DeviceID == DeviceExtension->DeviceId);
1065 if (!IdMatch) return FALSE;
1066
1067 /* If the device has a valid revision, check if it matches */
1068 RevMatch = (HackFlags & PCI_HACK_NO_REVISION_AFTER_D3) ||
1069 (PciData->RevisionID == DeviceExtension->RevisionId);
1070 if (!RevMatch) return FALSE;
1071
1072 /* For multifunction devices, this is enough to assume they're the same */
1073 if (PCI_MULTIFUNCTION_DEVICE(PciData)) return TRUE;
1074
1075 /* For bridge devices, there's also nothing else that can be checked */
1076 if (DeviceExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) return TRUE;
1077
1078 /* Devices, on the other hand, have subsystem data that can be compared */
1079 SubsysMatch = (HackFlags & (PCI_HACK_NO_SUBSYSTEM |
1080 PCI_HACK_NO_SUBSYSTEM_AFTER_D3)) ||
1081 ((DeviceExtension->SubsystemVendorId ==
1082 PciData->u.type0.SubVendorID) &&
1083 (DeviceExtension->SubsystemId ==
1084 PciData->u.type0.SubSystemID));
1085 return SubsysMatch;
1086 }
1087
1088 BOOLEAN
1089 NTAPI
1090 PciSkipThisFunction(IN PPCI_COMMON_HEADER PciData,
1091 IN PCI_SLOT_NUMBER Slot,
1092 IN UCHAR OperationType,
1093 IN ULONGLONG HackFlags)
1094 {
1095 do
1096 {
1097 /* Check if this is device enumeration */
1098 if (OperationType == PCI_SKIP_DEVICE_ENUMERATION)
1099 {
1100 /* Check if there's a hackflag saying not to enumerate this device */
1101 if (HackFlags & PCI_HACK_NO_ENUM_AT_ALL) break;
1102
1103 /* Check if this is the high end of a double decker device */
1104 if ((HackFlags & PCI_HACK_DOUBLE_DECKER) &&
1105 (Slot.u.bits.DeviceNumber >= 16))
1106 {
1107 /* It belongs to the same device, so skip it */
1108 DPRINT1(" Device (Ven %04x Dev %04x (d=0x%x, f=0x%x)) is a ghost.\n",
1109 PciData->VendorID,
1110 PciData->DeviceID,
1111 Slot.u.bits.DeviceNumber,
1112 Slot.u.bits.FunctionNumber);
1113 break;
1114 }
1115 }
1116 else if (OperationType == PCI_SKIP_RESOURCE_ENUMERATION)
1117 {
1118 /* Resource enumeration, check for a hackflag saying not to do it */
1119 if (HackFlags & PCI_HACK_ENUM_NO_RESOURCE) break;
1120 }
1121 else
1122 {
1123 /* Logic error in the driver */
1124 ASSERTMSG(FALSE, "PCI Skip Function - Operation type unknown.");
1125 }
1126
1127 /* Check for legacy bridges during resource enumeration */
1128 if ((PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1129 (PciData->SubClass <= PCI_SUBCLASS_BR_MCA) &&
1130 (OperationType == PCI_SKIP_RESOURCE_ENUMERATION))
1131 {
1132 /* Their resources are not enumerated, only PCI and Cardbus/PCMCIA */
1133 break;
1134 }
1135 else if (PciData->BaseClass == PCI_CLASS_NOT_DEFINED)
1136 {
1137 /* Undefined base class (usually a PCI BIOS/ROM bug) */
1138 DPRINT1(" Vendor %04x, Device %04x has class code of PCI_CLASS_NOT_DEFINED\n",
1139 PciData->VendorID,
1140 PciData->DeviceID);
1141
1142 /*
1143 * The Alder has an Intel Extended Express System Support Controller
1144 * which presents apparently spurious BARs. When the PCI resource
1145 * code tries to reassign these BARs, the second IO-APIC gets
1146 * disabled (with disastrous consequences). The first BAR is the
1147 * actual IO-APIC, the remaining five bars seem to be spurious
1148 * resources, so ignore this device completely.
1149 */
1150 if ((PciData->VendorID == 0x8086) && (PciData->DeviceID == 8)) break;
1151 }
1152
1153 /* Other normal PCI cards and bridges are enumerated */
1154 if (PCI_CONFIGURATION_TYPE(PciData) <= PCI_CARDBUS_BRIDGE_TYPE) return FALSE;
1155 } while (FALSE);
1156
1157 /* Hit one of the known bugs/hackflags, or this is a new kind of PCI unit */
1158 DPRINT1(" Device skipped (not enumerated).\n");
1159 return TRUE;
1160 }
1161
1162 VOID
1163 NTAPI
1164 PciGetEnhancedCapabilities(IN PPCI_PDO_EXTENSION PdoExtension,
1165 IN PPCI_COMMON_HEADER PciData)
1166 {
1167 ULONG HeaderType, CapPtr, TargetAgpCapabilityId;
1168 DEVICE_POWER_STATE WakeLevel;
1169 PCI_CAPABILITIES_HEADER AgpCapability;
1170 PCI_PM_CAPABILITY PowerCapabilities;
1171 PAGED_CODE();
1172
1173 /* Assume no known wake level */
1174 PdoExtension->PowerState.DeviceWakeLevel = PowerDeviceUnspecified;
1175
1176 /* Make sure the device has capabilities */
1177 if (!(PciData->Status & PCI_STATUS_CAPABILITIES_LIST))
1178 {
1179 /* If it doesn't, there will be no power management */
1180 PdoExtension->CapabilitiesPtr = 0;
1181 PdoExtension->HackFlags |= PCI_HACK_NO_PM_CAPS;
1182 }
1183 else
1184 {
1185 /* There's capabilities, need to figure out where to get the offset */
1186 HeaderType = PCI_CONFIGURATION_TYPE(PciData);
1187 if (HeaderType == PCI_CARDBUS_BRIDGE_TYPE)
1188 {
1189 /* Use the bridge's header */
1190 CapPtr = PciData->u.type2.CapabilitiesPtr;
1191 }
1192 else
1193 {
1194 /* Use the device header */
1195 ASSERT(HeaderType <= PCI_CARDBUS_BRIDGE_TYPE);
1196 CapPtr = PciData->u.type0.CapabilitiesPtr;
1197 }
1198
1199 /* Make sure the pointer is spec-aligned and located, and save it */
1200 DPRINT1("Device has capabilities at: %lx\n", CapPtr);
1201 ASSERT(((CapPtr & 0x3) == 0) && (CapPtr >= PCI_COMMON_HDR_LENGTH));
1202 PdoExtension->CapabilitiesPtr = CapPtr;
1203
1204 /* Check for PCI-to-PCI Bridges and AGP bridges */
1205 if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1206 ((PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST) ||
1207 (PdoExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI)))
1208 {
1209 /* Query either the raw AGP capabilitity, or the Target AGP one */
1210 TargetAgpCapabilityId = (PdoExtension->SubClass ==
1211 PCI_SUBCLASS_BR_PCI_TO_PCI) ?
1212 PCI_CAPABILITY_ID_AGP_TARGET :
1213 PCI_CAPABILITY_ID_AGP;
1214 if (PciReadDeviceCapability(PdoExtension,
1215 PdoExtension->CapabilitiesPtr,
1216 TargetAgpCapabilityId,
1217 &AgpCapability,
1218 sizeof(PCI_CAPABILITIES_HEADER)))
1219 {
1220 /* AGP target ID was found, store it */
1221 DPRINT1("AGP ID: %lx\n", TargetAgpCapabilityId);
1222 PdoExtension->TargetAgpCapabilityId = TargetAgpCapabilityId;
1223 }
1224 }
1225
1226 /* Check for devices that are known not to have proper power management */
1227 if (!(PdoExtension->HackFlags & PCI_HACK_NO_PM_CAPS))
1228 {
1229 /* Query if this device supports power management */
1230 if (!PciReadDeviceCapability(PdoExtension,
1231 PdoExtension->CapabilitiesPtr,
1232 PCI_CAPABILITY_ID_POWER_MANAGEMENT,
1233 &PowerCapabilities.Header,
1234 sizeof(PCI_PM_CAPABILITY)))
1235 {
1236 /* No power management, so act as if it had the hackflag set */
1237 DPRINT1("No PM caps, disabling PM\n");
1238 PdoExtension->HackFlags |= PCI_HACK_NO_PM_CAPS;
1239 }
1240 else
1241 {
1242 /* Otherwise, pick the highest wake level that is supported */
1243 WakeLevel = PowerDeviceUnspecified;
1244 if (PowerCapabilities.PMC.Capabilities.Support.PMED0)
1245 WakeLevel = PowerDeviceD0;
1246 if (PowerCapabilities.PMC.Capabilities.Support.PMED1)
1247 WakeLevel = PowerDeviceD1;
1248 if (PowerCapabilities.PMC.Capabilities.Support.PMED2)
1249 WakeLevel = PowerDeviceD2;
1250 if (PowerCapabilities.PMC.Capabilities.Support.PMED3Hot)
1251 WakeLevel = PowerDeviceD3;
1252 if (PowerCapabilities.PMC.Capabilities.Support.PMED3Cold)
1253 WakeLevel = PowerDeviceD3;
1254 PdoExtension->PowerState.DeviceWakeLevel = WakeLevel;
1255
1256 /* Convert the PCI power state to the NT power state */
1257 PdoExtension->PowerState.CurrentDeviceState =
1258 PowerCapabilities.PMCSR.ControlStatus.PowerState + 1;
1259
1260 /* Save all the power capabilities */
1261 PdoExtension->PowerCapabilities = PowerCapabilities.PMC.Capabilities;
1262 DPRINT1("PM Caps Found! Wake Level: %d Power State: %d\n",
1263 WakeLevel, PdoExtension->PowerState.CurrentDeviceState);
1264 }
1265 }
1266 }
1267
1268 /* At the very end of all this, does this device not have power management? */
1269 if (PdoExtension->HackFlags & PCI_HACK_NO_PM_CAPS)
1270 {
1271 /* Then guess the current state based on whether the decodes are on */
1272 PdoExtension->PowerState.CurrentDeviceState =
1273 PciData->Command & (PCI_ENABLE_IO_SPACE |
1274 PCI_ENABLE_MEMORY_SPACE |
1275 PCI_ENABLE_BUS_MASTER) ?
1276 PowerDeviceD0: PowerDeviceD3;
1277 DPRINT1("PM is off, so assumed device is: %d based on enables\n",
1278 PdoExtension->PowerState.CurrentDeviceState);
1279 }
1280 }
1281
1282 VOID
1283 NTAPI
1284 PciWriteLimitsAndRestoreCurrent(IN PVOID Reserved,
1285 IN PVOID Context2)
1286 {
1287 PPCI_CONFIGURATOR_CONTEXT Context = Context2;
1288 PPCI_COMMON_HEADER PciData, Current;
1289 PPCI_PDO_EXTENSION PdoExtension;
1290
1291 /* Grab all parameters from the context */
1292 PdoExtension = Context->PdoExtension;
1293 Current = Context->Current;
1294 PciData = Context->PciData;
1295
1296 /* Write the limit discovery header */
1297 PciWriteDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
1298
1299 /* Now read what the device indicated the limits are */
1300 PciReadDeviceConfig(PdoExtension, PciData, 0, PCI_COMMON_HDR_LENGTH);
1301
1302 /* Then write back the original configuration header */
1303 PciWriteDeviceConfig(PdoExtension, Current, 0, PCI_COMMON_HDR_LENGTH);
1304
1305 /* Copy back the original command that was saved in the context */
1306 Current->Command = Context->Command;
1307 if (Context->Command)
1308 {
1309 /* Program it back into the device */
1310 PciWriteDeviceConfig(PdoExtension,
1311 &Context->Command,
1312 FIELD_OFFSET(PCI_COMMON_HEADER, Command),
1313 sizeof(USHORT));
1314 }
1315
1316 /* Copy back the original status that was saved as well */
1317 Current->Status = Context->Status;
1318
1319 /* Call the configurator to restore any other data that might've changed */
1320 Context->Configurator->RestoreCurrent(Context);
1321 }
1322
1323 NTSTATUS
1324 NTAPI
1325 PcipGetFunctionLimits(IN PPCI_CONFIGURATOR_CONTEXT Context)
1326 {
1327 PPCI_CONFIGURATOR Configurator;
1328 PPCI_COMMON_HEADER PciData, Current;
1329 PPCI_PDO_EXTENSION PdoExtension;
1330 PCI_IPI_CONTEXT IpiContext;
1331 PIO_RESOURCE_DESCRIPTOR IoDescriptor;
1332 ULONG Offset;
1333 PAGED_CODE();
1334
1335 /* Grab all parameters from the context */
1336 PdoExtension = Context->PdoExtension;
1337 Current = Context->Current;
1338 PciData = Context->PciData;
1339
1340 /* Save the current PCI Command and Status word */
1341 Context->Status = Current->Status;
1342 Context->Command = Current->Command;
1343
1344 /* Now that they're saved, clear the status, and disable all decodes */
1345 Current->Status = 0;
1346 Current->Command &= ~(PCI_ENABLE_IO_SPACE |
1347 PCI_ENABLE_MEMORY_SPACE |
1348 PCI_ENABLE_BUS_MASTER);
1349
1350 /* Make a copy of the current PCI configuration header (with decodes off) */
1351 RtlCopyMemory(PciData, Current, PCI_COMMON_HDR_LENGTH);
1352
1353 /* Locate the correct resource configurator for this type of device */
1354 Configurator = &PciConfigurators[PdoExtension->HeaderType];
1355 Context->Configurator = Configurator;
1356
1357 /* Initialize it, which will typically setup the BARs for limit discovery */
1358 Configurator->Initialize(Context);
1359
1360 /* Check for critical devices and PCI Debugging devices */
1361 if ((PdoExtension->HackFlags & PCI_HACK_CRITICAL_DEVICE) ||
1362 (PdoExtension->OnDebugPath))
1363 {
1364 /* Specifically check for a PCI Debugging device */
1365 if (PdoExtension->OnDebugPath)
1366 {
1367 /* Was it enabled for bus mastering? */
1368 if (Context->Command & PCI_ENABLE_BUS_MASTER)
1369 {
1370 /* This decode needs to be re-enabled so debugging can work */
1371 PciData->Command |= PCI_ENABLE_BUS_MASTER;
1372 Current->Command |= PCI_ENABLE_BUS_MASTER;
1373 }
1374
1375 /* Disable the debugger while the discovery is happening */
1376 KdDisableDebugger();
1377 }
1378
1379 /* For these devices, an IPI must be sent to force high-IRQL discovery */
1380 IpiContext.Barrier = 1;
1381 IpiContext.RunCount = 1;
1382 IpiContext.DeviceExtension = PdoExtension;
1383 IpiContext.Function = PciWriteLimitsAndRestoreCurrent;
1384 IpiContext.Context = Context;
1385 KeIpiGenericCall(PciExecuteCriticalSystemRoutine, (ULONG_PTR)&IpiContext);
1386
1387 /* Re-enable the debugger if this was a PCI Debugging Device */
1388 if (PdoExtension->OnDebugPath) KdEnableDebugger();
1389 }
1390 else
1391 {
1392 /* Otherwise, it's safe to do this in-line at low IRQL */
1393 PciWriteLimitsAndRestoreCurrent(PdoExtension, Context);
1394 }
1395
1396 /*
1397 * Check if it's valid to compare the headers to see if limit discovery mode
1398 * has properly exited (the expected case is that the PCI header would now
1399 * be equal to what it was before). In some cases, it is known that this will
1400 * fail, because during PciApplyHacks (among other places), software hacks
1401 * had to be applied to the header, which the hardware-side will not see, and
1402 * thus the headers would appear "different".
1403 */
1404 if (!PdoExtension->ExpectedWritebackFailure)
1405 {
1406 /* Read the current PCI header now, after discovery has completed */
1407 PciReadDeviceConfig(PdoExtension, PciData + 1, 0, PCI_COMMON_HDR_LENGTH);
1408
1409 /* Check if the current header at entry, is equal to the header now */
1410 Offset = RtlCompareMemory(PciData + 1, Current, PCI_COMMON_HDR_LENGTH);
1411 if (Offset != PCI_COMMON_HDR_LENGTH)
1412 {
1413 /* It's not, which means configuration somehow changed, dump this */
1414 DPRINT1("PCI - CFG space write verify failed at offset 0x%x\n", Offset);
1415 PciDebugDumpCommonConfig(PciData + 1);
1416 DPRINT1("----------\n");
1417 PciDebugDumpCommonConfig(Current);
1418 }
1419 }
1420
1421 /* This PDO should not already have resources, since this is only done once */
1422 ASSERT(PdoExtension->Resources == NULL);
1423
1424 /* Allocate the structure that will hold the discovered resources and limits */
1425 PdoExtension->Resources = ExAllocatePoolWithTag(NonPagedPool,
1426 sizeof(PCI_FUNCTION_RESOURCES),
1427 'BicP');
1428 if (!PdoExtension->Resources) return STATUS_INSUFFICIENT_RESOURCES;
1429
1430 /* Clear it out for now */
1431 RtlZeroMemory(PdoExtension->Resources, sizeof(PCI_FUNCTION_RESOURCES));
1432
1433 /* Now call the configurator, which will first store the limits... */
1434 Configurator->SaveLimits(Context);
1435
1436 /* ...and then store the current resources being used */
1437 Configurator->SaveCurrentSettings(Context);
1438
1439 /* Loop all the limit descriptors backwards */
1440 IoDescriptor = &PdoExtension->Resources->Limit[PCI_TYPE0_ADDRESSES + 1];
1441 while (TRUE)
1442 {
1443 /* Keep going until a non-null descriptor is found */
1444 IoDescriptor--;
1445 if (IoDescriptor->Type != CmResourceTypeNull) break;
1446
1447 /* This is a null descriptor, is it the last one? */
1448 if (IoDescriptor == &PdoExtension->Resources->Limit[PCI_TYPE0_ADDRESSES + 1])
1449 {
1450 /* This means the descriptor is NULL, which means discovery failed */
1451 DPRINT1("PCI Resources fail!\n");
1452
1453 /* No resources will be assigned for the device */
1454 ExFreePoolWithTag(PdoExtension->Resources, 0);
1455 PdoExtension->Resources = NULL;
1456 break;
1457 }
1458 }
1459
1460 /* Return success here, even if the device has no assigned resources */
1461 return STATUS_SUCCESS;
1462 }
1463
1464 NTSTATUS
1465 NTAPI
1466 PciGetFunctionLimits(IN PPCI_PDO_EXTENSION PdoExtension,
1467 IN PPCI_COMMON_HEADER Current,
1468 IN ULONGLONG HackFlags)
1469 {
1470 NTSTATUS Status;
1471 PPCI_COMMON_HEADER PciData;
1472 PCI_CONFIGURATOR_CONTEXT Context;
1473 PAGED_CODE();
1474
1475 /* Do the hackflags indicate this device should be skipped? */
1476 if (PciSkipThisFunction(Current,
1477 PdoExtension->Slot,
1478 PCI_SKIP_RESOURCE_ENUMERATION,
1479 HackFlags))
1480 {
1481 /* Do not process its resources */
1482 return STATUS_SUCCESS;
1483 }
1484
1485 /* Allocate a buffer to hold two PCI configuration headers */
1486 PciData = ExAllocatePoolWithTag(0, 2 * PCI_COMMON_HDR_LENGTH, 'BicP');
1487 if (!PciData) return STATUS_INSUFFICIENT_RESOURCES;
1488
1489 /* Set up the context for the resource enumeration, and do it */
1490 Context.Current = Current;
1491 Context.PciData = PciData;
1492 Context.PdoExtension = PdoExtension;
1493 Status = PcipGetFunctionLimits(&Context);
1494
1495 /* Enumeration is completed, free the PCI headers and return the status */
1496 ExFreePoolWithTag(PciData, 0);
1497 return Status;
1498 }
1499
1500 VOID
1501 NTAPI
1502 PciProcessBus(IN PPCI_FDO_EXTENSION DeviceExtension)
1503 {
1504 PPCI_PDO_EXTENSION PdoExtension;
1505 PDEVICE_OBJECT PhysicalDeviceObject;
1506 PAGED_CODE();
1507
1508 /* Get the PDO Extension */
1509 PhysicalDeviceObject = DeviceExtension->PhysicalDeviceObject;
1510 PdoExtension = (PPCI_PDO_EXTENSION)PhysicalDeviceObject->DeviceExtension;
1511
1512 /* Cheeck if this is the root bus */
1513 if (!PCI_IS_ROOT_FDO(DeviceExtension))
1514 {
1515 /* Not really handling this year */
1516 UNIMPLEMENTED;
1517 while (TRUE);
1518
1519 /* Check for PCI bridges with the ISA bit set, or required */
1520 if ((PdoExtension) &&
1521 (PciClassifyDeviceType(PdoExtension) == PciTypePciBridge) &&
1522 ((PdoExtension->Dependent.type1.IsaBitRequired) ||
1523 (PdoExtension->Dependent.type1.IsaBitSet)))
1524 {
1525 /* We'll need to do some legacy support */
1526 UNIMPLEMENTED;
1527 while (TRUE);
1528 }
1529 }
1530 else
1531 {
1532 /* Scan all of the root bus' children bridges */
1533 for (PdoExtension = DeviceExtension->ChildBridgePdoList;
1534 PdoExtension;
1535 PdoExtension = PdoExtension->NextBridge)
1536 {
1537 /* Find any that have the VGA decode bit on */
1538 if (PdoExtension->Dependent.type1.VgaBitSet)
1539 {
1540 /* Again, some more legacy support we'll have to do */
1541 UNIMPLEMENTED;
1542 while (TRUE);
1543 }
1544 }
1545 }
1546
1547 /* Check for ACPI systems where the OS assigns bus numbers */
1548 if (PciAssignBusNumbers)
1549 {
1550 /* Not yet supported */
1551 UNIMPLEMENTED;
1552 while (TRUE);
1553 }
1554 }
1555
1556 NTSTATUS
1557 NTAPI
1558 PciScanBus(IN PPCI_FDO_EXTENSION DeviceExtension)
1559 {
1560 ULONG MaxDevice = PCI_MAX_DEVICES;
1561 BOOLEAN ProcessFlag = FALSE;
1562 ULONG i, j, k, Size;
1563 USHORT CapOffset, TempOffset;
1564 LONGLONG HackFlags;
1565 PDEVICE_OBJECT DeviceObject;
1566 UCHAR Buffer[PCI_COMMON_HDR_LENGTH];
1567 UCHAR BiosBuffer[PCI_COMMON_HDR_LENGTH];
1568 PPCI_COMMON_HEADER PciData = (PVOID)Buffer;
1569 PPCI_COMMON_HEADER BiosData = (PVOID)BiosBuffer;
1570 PCI_SLOT_NUMBER PciSlot;
1571 PCHAR Name;
1572 NTSTATUS Status;
1573 PPCI_PDO_EXTENSION PdoExtension, NewExtension;
1574 PPCI_PDO_EXTENSION* BridgeExtension;
1575 PWCHAR DescriptionText;
1576 USHORT SubVendorId, SubSystemId;
1577 PCI_CAPABILITIES_HEADER CapHeader, PcixCapHeader;
1578 UCHAR SecondaryBus;
1579 DPRINT1("PCI Scan Bus: FDO Extension @ 0x%x, Base Bus = 0x%x\n",
1580 DeviceExtension, DeviceExtension->BaseBus);
1581
1582 /* Is this the root FDO? */
1583 if (!PCI_IS_ROOT_FDO(DeviceExtension))
1584 {
1585 /* Get the PDO for the child bus */
1586 PdoExtension = DeviceExtension->PhysicalDeviceObject->DeviceExtension;
1587 ASSERT_PDO(PdoExtension);
1588
1589 /* Check for hack which only allows bus to have one child device */
1590 if (PdoExtension->HackFlags & PCI_HACK_ONE_CHILD) MaxDevice = 1;
1591
1592 /* Check if the secondary bus number has changed */
1593 PciReadDeviceConfig(PdoExtension,
1594 &SecondaryBus,
1595 FIELD_OFFSET(PCI_COMMON_HEADER, u.type1.SecondaryBus),
1596 sizeof(UCHAR));
1597 if (SecondaryBus != PdoExtension->Dependent.type1.SecondaryBus)
1598 {
1599 DPRINT1("PCI: Bus numbers have been changed! Restoring originals.\n");
1600 UNIMPLEMENTED;
1601 while (TRUE);
1602 }
1603 }
1604
1605 /* Loop every device on the bus */
1606 PciSlot.u.bits.Reserved = 0;
1607 i = DeviceExtension->BaseBus;
1608 for (j = 0; j < MaxDevice; j++)
1609 {
1610 /* Loop every function of each device */
1611 PciSlot.u.bits.DeviceNumber = j;
1612 for (k = 0; k < PCI_MAX_FUNCTION; k++)
1613 {
1614 /* Build the final slot structure */
1615 PciSlot.u.bits.FunctionNumber = k;
1616
1617 /* Read the vendor for this slot */
1618 PciReadSlotConfig(DeviceExtension,
1619 PciSlot,
1620 PciData,
1621 0,
1622 sizeof(USHORT));
1623
1624 /* Skip invalid device */
1625 if (PciData->VendorID == PCI_INVALID_VENDORID) continue;
1626
1627 /* Now read the whole header */
1628 PciReadSlotConfig(DeviceExtension,
1629 PciSlot,
1630 &PciData->DeviceID,
1631 sizeof(USHORT),
1632 PCI_COMMON_HDR_LENGTH - sizeof(USHORT));
1633
1634 /* Apply any hacks before even analyzing the configuration header */
1635 PciApplyHacks(DeviceExtension,
1636 PciData,
1637 PciSlot,
1638 PCI_HACK_FIXUP_BEFORE_CONFIGURATION,
1639 NULL);
1640
1641 /* Dump device that was found */
1642 DPRINT1("Scan Found Device 0x%x (b=0x%x, d=0x%x, f=0x%x)\n",
1643 PciSlot.u.AsULONG,
1644 i,
1645 j,
1646 k);
1647
1648 /* Dump the device's header */
1649 PciDebugDumpCommonConfig(PciData);
1650
1651 /* Find description for this device for the debugger's sake */
1652 DescriptionText = PciGetDeviceDescriptionMessage(PciData->BaseClass,
1653 PciData->SubClass);
1654 DPRINT1("Device Description \"%S\".\n",
1655 DescriptionText ? DescriptionText : L"(NULL)");
1656 if (DescriptionText) ExFreePoolWithTag(DescriptionText, 0);
1657
1658 /* Check if there is an ACPI Watchdog Table */
1659 if (WdTable)
1660 {
1661 /* Check if this PCI device is the ACPI Watchdog Device... */
1662 UNIMPLEMENTED;
1663 while (TRUE);
1664 }
1665
1666 /* Check for non-simple devices */
1667 if ((PCI_MULTIFUNCTION_DEVICE(PciData)) ||
1668 (PciData->BaseClass == PCI_CLASS_BRIDGE_DEV))
1669 {
1670 /* No subsystem data defined for these kinds of bridges */
1671 SubVendorId = 0;
1672 SubSystemId = 0;
1673 }
1674 else
1675 {
1676 /* Read the subsystem information from the PCI header */
1677 SubVendorId = PciData->u.type0.SubVendorID;
1678 SubSystemId = PciData->u.type0.SubSystemID;
1679 }
1680
1681 /* Get any hack flags for this device */
1682 HackFlags = PciGetHackFlags(PciData->VendorID,
1683 PciData->DeviceID,
1684 SubVendorId,
1685 SubSystemId,
1686 PciData->RevisionID);
1687
1688 /* Check if this device is considered critical by the OS */
1689 if (PciIsCriticalDeviceClass(PciData->BaseClass, PciData->SubClass))
1690 {
1691 /* Check if normally the decodes would be disabled */
1692 if (!(HackFlags & PCI_HACK_DONT_DISABLE_DECODES))
1693 {
1694 /* Because this device is critical, don't disable them */
1695 DPRINT1("Not allowing PM Because device is critical\n");
1696 HackFlags |= PCI_HACK_CRITICAL_DEVICE;
1697 }
1698 }
1699
1700 /* PCI bridges with a VGA card are also considered critical */
1701 if ((PciData->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1702 (PciData->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) &&
1703 (PciData->u.type1.BridgeControl & PCI_ENABLE_BRIDGE_VGA) &&
1704 !(HackFlags & PCI_HACK_DONT_DISABLE_DECODES))
1705 {
1706 /* Do not disable their decodes either */
1707 DPRINT1("Not allowing PM because device is VGA\n");
1708 HackFlags |= PCI_HACK_CRITICAL_DEVICE;
1709 }
1710
1711 /* Check if the device should be skipped for whatever reason */
1712 if (PciSkipThisFunction(PciData,
1713 PciSlot,
1714 PCI_SKIP_DEVICE_ENUMERATION,
1715 HackFlags))
1716 {
1717 /* Skip this device */
1718 continue;
1719 }
1720
1721 /* Check if a PDO has already been created for this device */
1722 PdoExtension = PciFindPdoByFunction(DeviceExtension,
1723 PciSlot.u.AsULONG,
1724 PciData);
1725 if (PdoExtension)
1726 {
1727 /* Rescan scenarios are not yet implemented */
1728 UNIMPLEMENTED;
1729 while (TRUE);
1730 }
1731
1732 /* Bus processing will need to happen */
1733 ProcessFlag = TRUE;
1734
1735 /* Create the PDO for this device */
1736 Status = PciPdoCreate(DeviceExtension, PciSlot, &DeviceObject);
1737 ASSERT(NT_SUCCESS(Status));
1738 NewExtension = (PPCI_PDO_EXTENSION)DeviceObject->DeviceExtension;
1739
1740 /* Check for broken devices with wrong/no class codes */
1741 if (HackFlags & PCI_HACK_FAKE_CLASS_CODE)
1742 {
1743 /* Setup a default one */
1744 PciData->BaseClass = PCI_CLASS_BASE_SYSTEM_DEV;
1745 PciData->SubClass = PCI_SUBCLASS_SYS_OTHER;
1746
1747 /* Device will behave erratically when reading back data */
1748 NewExtension->ExpectedWritebackFailure = TRUE;
1749 }
1750
1751 /* Clone all the information from the header */
1752 NewExtension->VendorId = PciData->VendorID;
1753 NewExtension->DeviceId = PciData->DeviceID;
1754 NewExtension->RevisionId = PciData->RevisionID;
1755 NewExtension->ProgIf = PciData->ProgIf;
1756 NewExtension->SubClass = PciData->SubClass;
1757 NewExtension->BaseClass = PciData->BaseClass;
1758 NewExtension->HeaderType = PCI_CONFIGURATION_TYPE(PciData);
1759
1760 /* Check for modern bridge types, which are managed by the driver */
1761 if ((NewExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1762 ((NewExtension->SubClass == PCI_SUBCLASS_BR_PCI_TO_PCI) ||
1763 (NewExtension->SubClass == PCI_SUBCLASS_BR_CARDBUS)))
1764 {
1765 /* Acquire this device's lock */
1766 KeEnterCriticalRegion();
1767 KeWaitForSingleObject(&DeviceExtension->ChildListLock,
1768 Executive,
1769 KernelMode,
1770 FALSE,
1771 NULL);
1772
1773 /* Scan the bridge list until the first free entry */
1774 for (BridgeExtension = &DeviceExtension->ChildBridgePdoList;
1775 *BridgeExtension;
1776 BridgeExtension = &(*BridgeExtension)->NextBridge);
1777
1778 /* Add this PDO as a bridge */
1779 *BridgeExtension = NewExtension;
1780 ASSERT(NewExtension->NextBridge == NULL);
1781
1782 /* Release this device's lock */
1783 KeSetEvent(&DeviceExtension->ChildListLock,
1784 IO_NO_INCREMENT,
1785 FALSE);
1786 KeLeaveCriticalRegion();
1787 }
1788
1789 /* Get the PCI BIOS configuration saved in the registry */
1790 Status = PciGetBiosConfig(NewExtension, BiosData);
1791 if (NT_SUCCESS(Status))
1792 {
1793 /* This path has not yet been fully tested by eVb */
1794 DPRINT1("Have BIOS configuration!\n");
1795 UNIMPLEMENTED;
1796
1797 /* Check if the PCI BIOS configuration has changed */
1798 if (!PcipIsSameDevice(NewExtension, BiosData))
1799 {
1800 /* This is considered failure, and new data will be saved */
1801 Status = STATUS_UNSUCCESSFUL;
1802 }
1803 else
1804 {
1805 /* Data is still correct, check for interrupt line change */
1806 if (BiosData->u.type0.InterruptLine !=
1807 PciData->u.type0.InterruptLine)
1808 {
1809 /* Update the current BIOS with the saved interrupt line */
1810 PciWriteDeviceConfig(NewExtension,
1811 &BiosData->u.type0.InterruptLine,
1812 FIELD_OFFSET(PCI_COMMON_HEADER,
1813 u.type0.InterruptLine),
1814 sizeof(UCHAR));
1815 }
1816
1817 /* Save the BIOS interrupt line and the initial command */
1818 NewExtension->RawInterruptLine = BiosData->u.type0.InterruptLine;
1819 NewExtension->InitialCommand = BiosData->Command;
1820 }
1821 }
1822
1823 /* Check if no saved data was present or if it was a mismatch */
1824 if (!NT_SUCCESS(Status))
1825 {
1826 /* Save the new data */
1827 Status = PciSaveBiosConfig(NewExtension, PciData);
1828 ASSERT(NT_SUCCESS(Status));
1829
1830 /* Save the interrupt line and command from the device */
1831 NewExtension->RawInterruptLine = PciData->u.type0.InterruptLine;
1832 NewExtension->InitialCommand = PciData->Command;
1833 }
1834
1835 /* Save original command from the device and hack flags */
1836 NewExtension->CommandEnables = PciData->Command;
1837 NewExtension->HackFlags = HackFlags;
1838
1839 /* Get power, AGP, and other capability data */
1840 PciGetEnhancedCapabilities(NewExtension, PciData);
1841
1842 /* Now configure the BARs */
1843 Status = PciGetFunctionLimits(NewExtension, PciData, HackFlags);
1844
1845 /* Power up the device */
1846 PciSetPowerManagedDevicePowerState(NewExtension, PowerDeviceD0, FALSE);
1847
1848 /* Apply any device hacks required for enumeration */
1849 PciApplyHacks(DeviceExtension,
1850 PciData,
1851 PciSlot,
1852 PCI_HACK_FIXUP_AFTER_CONFIGURATION,
1853 NewExtension);
1854
1855 /* Save interrupt pin */
1856 NewExtension->InterruptPin = PciData->u.type0.InterruptPin;
1857
1858 /*
1859 * Use either this device's actual IRQ line or, if it's connected on
1860 * a master bus whose IRQ line is actually connected to the host, use
1861 * the HAL to query the bus' IRQ line and store that as the adjusted
1862 * interrupt line instead
1863 */
1864 NewExtension->AdjustedInterruptLine = PciGetAdjustedInterruptLine(NewExtension);
1865
1866 /* Check if this device is used for PCI debugger cards */
1867 NewExtension->OnDebugPath = PciIsDeviceOnDebugPath(NewExtension);
1868
1869 /* Check for devices with invalid/bogus subsystem data */
1870 if (HackFlags & PCI_HACK_NO_SUBSYSTEM)
1871 {
1872 /* Set the subsystem information to zero instead */
1873 NewExtension->SubsystemVendorId = 0;
1874 NewExtension->SubsystemId = 0;
1875 }
1876
1877 /* Scan all capabilities */
1878 CapOffset = NewExtension->CapabilitiesPtr;
1879 while (CapOffset)
1880 {
1881 /* Read this header */
1882 TempOffset = PciReadDeviceCapability(NewExtension,
1883 CapOffset,
1884 0,
1885 &CapHeader,
1886 sizeof(PCI_CAPABILITIES_HEADER));
1887 if (TempOffset != CapOffset)
1888 {
1889 /* This is a strange issue that shouldn't happen normally */
1890 DPRINT1("PCI - Failed to read PCI capability at offset 0x%02x\n",
1891 CapOffset);
1892 ASSERT(TempOffset == CapOffset);
1893 }
1894
1895 /* Check for capabilities that this driver cares about */
1896 switch (CapHeader.CapabilityID)
1897 {
1898 /* Power management capability is heavily used by the bus */
1899 case PCI_CAPABILITY_ID_POWER_MANAGEMENT:
1900
1901 /* Dump the capability */
1902 Name = "POWER";
1903 Size = sizeof(PCI_PM_CAPABILITY);
1904 break;
1905
1906 /* AGP capability is required for AGP bus functionality */
1907 case PCI_CAPABILITY_ID_AGP:
1908
1909 /* Dump the capability */
1910 Name = "AGP";
1911 Size = sizeof(PCI_AGP_CAPABILITY);
1912 break;
1913
1914 /* This driver doesn't really use anything other than that */
1915 default:
1916
1917 /* Windows prints this, we could do a translation later */
1918 Name = "UNKNOWN CAPABILITY";
1919 Size = 0;
1920 break;
1921 }
1922
1923 /* Check if this is a capability that should be dumped */
1924 if (Size)
1925 {
1926 /* Read the whole capability data */
1927 TempOffset = PciReadDeviceCapability(NewExtension,
1928 CapOffset,
1929 CapHeader.CapabilityID,
1930 &CapHeader,
1931 Size);
1932
1933 if (TempOffset != CapOffset)
1934 {
1935 /* Again, a strange issue that shouldn't be seen */
1936 DPRINT1("- Failed to read capability data. ***\n");
1937 ASSERT(TempOffset == CapOffset);
1938 }
1939 }
1940
1941 /* Dump this capability */
1942 DPRINT1("CAP @%02x ID %02x (%s)\n",
1943 CapOffset, CapHeader.CapabilityID, Name);
1944 for (i = 0; i < Size; i += 2)
1945 DPRINT1(" %04x\n", *(PUSHORT)((ULONG_PTR)&CapHeader + i));
1946 DPRINT1("\n");
1947
1948 /* Check the next capability */
1949 CapOffset = CapHeader.Next;
1950 }
1951
1952 /* Check for IDE controllers */
1953 if ((NewExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
1954 (NewExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
1955 {
1956 /* Do not allow them to power down completely */
1957 NewExtension->DisablePowerDown = TRUE;
1958 }
1959
1960 /*
1961 * Check if this is a legacy bridge. Note that the i82375 PCI/EISA
1962 * bridge that is present on certain NT Alpha machines appears as
1963 * non-classified so detect it manually by scanning for its VID/PID.
1964 */
1965 if (((NewExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
1966 ((NewExtension->SubClass == PCI_SUBCLASS_BR_ISA) ||
1967 (NewExtension->SubClass == PCI_SUBCLASS_BR_EISA) ||
1968 (NewExtension->SubClass == PCI_SUBCLASS_BR_MCA))) ||
1969 ((NewExtension->VendorId == 0x8086) &&
1970 (NewExtension->DeviceId == 0x482)))
1971 {
1972 /* Do not allow these legacy bridges to be powered down */
1973 NewExtension->DisablePowerDown = TRUE;
1974 }
1975
1976 /* Check if the BIOS did not configure a cache line size */
1977 if (!PciData->CacheLineSize)
1978 {
1979 /* Check if the device is disabled */
1980 if (!(NewExtension->CommandEnables & (PCI_ENABLE_IO_SPACE |
1981 PCI_ENABLE_MEMORY_SPACE |
1982 PCI_ENABLE_BUS_MASTER)))
1983 {
1984 /* Check if this is a PCI-X device*/
1985 TempOffset = PciReadDeviceCapability(NewExtension,
1986 NewExtension->CapabilitiesPtr,
1987 PCI_CAPABILITY_ID_PCIX,
1988 &PcixCapHeader,
1989 sizeof(PCI_CAPABILITIES_HEADER));
1990
1991 /*
1992 * A device with default cache line size and latency timer
1993 * settings is considered to be unconfigured. Note that on
1994 * PCI-X, the reset value of the latency timer field in the
1995 * header is 64, not 0, hence why the check for PCI-X caps
1996 * was required, and the value used here below.
1997 */
1998 if (!(PciData->LatencyTimer) ||
1999 ((TempOffset) && (PciData->LatencyTimer == 64)))
2000 {
2001 /* Keep track of the fact that it needs configuration */
2002 DPRINT1("PCI - ScanBus, PDOx %x found unconfigured\n",
2003 NewExtension);
2004 NewExtension->NeedsHotPlugConfiguration = TRUE;
2005 }
2006 }
2007 }
2008
2009 /* Save latency and cache size information */
2010 NewExtension->SavedLatencyTimer = PciData->LatencyTimer;
2011 NewExtension->SavedCacheLineSize = PciData->CacheLineSize;
2012
2013 /* The PDO is now ready to go */
2014 DeviceObject->Flags &= ~DO_DEVICE_INITIALIZING;
2015 }
2016 }
2017
2018 /* Enumeration completed, do a final pass now that all devices are found */
2019 if (ProcessFlag) PciProcessBus(DeviceExtension);
2020 return STATUS_SUCCESS;
2021 }
2022
2023 NTSTATUS
2024 NTAPI
2025 PciQueryDeviceRelations(IN PPCI_FDO_EXTENSION DeviceExtension,
2026 IN OUT PDEVICE_RELATIONS *pDeviceRelations)
2027 {
2028 NTSTATUS Status;
2029 PPCI_PDO_EXTENSION PdoExtension;
2030 ULONG PdoCount = 0;
2031 PDEVICE_RELATIONS DeviceRelations, NewRelations;
2032 SIZE_T Size;
2033 PDEVICE_OBJECT DeviceObject, *ObjectArray;
2034 PAGED_CODE();
2035
2036 /* Make sure the FDO is started */
2037 ASSERT(DeviceExtension->DeviceState == PciStarted);
2038
2039 /* Synchronize while we enumerate the bus */
2040 Status = PciBeginStateTransition(DeviceExtension, PciSynchronizedOperation);
2041 if (!NT_SUCCESS(Status)) return Status;
2042
2043 /* Scan all children PDO */
2044 for (PdoExtension = DeviceExtension->ChildPdoList;
2045 PdoExtension;
2046 PdoExtension = PdoExtension->Next)
2047 {
2048 /* Invalidate them */
2049 PdoExtension->NotPresent = TRUE;
2050 }
2051
2052 /* Scan the PCI Bus */
2053 Status = PciScanBus(DeviceExtension);
2054 ASSERT(NT_SUCCESS(Status));
2055
2056 /* Enumerate all children PDO again */
2057 for (PdoExtension = DeviceExtension->ChildPdoList;
2058 PdoExtension;
2059 PdoExtension = PdoExtension->Next)
2060 {
2061 /* Check for PDOs that are still invalidated */
2062 if (PdoExtension->NotPresent)
2063 {
2064 /* This means this PDO existed before, but not anymore */
2065 PdoExtension->ReportedMissing = TRUE;
2066 DPRINT1("PCI - Old device (pdox) %08x not found on rescan.\n",
2067 PdoExtension);
2068 }
2069 else
2070 {
2071 /* Increase count of detected PDOs */
2072 PdoCount++;
2073 }
2074 }
2075
2076 /* Read the current relations and add the newly discovered relations */
2077 DeviceRelations = *pDeviceRelations;
2078 Size = FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
2079 PdoCount * sizeof(PDEVICE_OBJECT);
2080 if (DeviceRelations) Size += sizeof(PDEVICE_OBJECT) * DeviceRelations->Count;
2081
2082 /* Allocate the device relations */
2083 NewRelations = (PDEVICE_RELATIONS)ExAllocatePoolWithTag(0, Size, 'BicP');
2084 if (!NewRelations)
2085 {
2086 /* Out of space, cancel the operation */
2087 PciCancelStateTransition(DeviceExtension, PciSynchronizedOperation);
2088 return STATUS_INSUFFICIENT_RESOURCES;
2089 }
2090
2091 /* Check if there were any older relations */
2092 NewRelations->Count = 0;
2093 if (DeviceRelations)
2094 {
2095 /* Copy the old relations into the new buffer, then free the old one */
2096 RtlCopyMemory(NewRelations,
2097 DeviceRelations,
2098 FIELD_OFFSET(DEVICE_RELATIONS, Objects) +
2099 DeviceRelations->Count * sizeof(PDEVICE_OBJECT));
2100 ExFreePoolWithTag(DeviceRelations, 0);
2101 }
2102
2103 /* Print out that we're ready to dump relations */
2104 DPRINT1("PCI QueryDeviceRelations/BusRelations FDOx %08x (bus 0x%02x)\n",
2105 DeviceExtension,
2106 DeviceExtension->BaseBus);
2107
2108 /* Loop the current PDO children and the device relation object array */
2109 PdoExtension = DeviceExtension->ChildPdoList;
2110 ObjectArray = &NewRelations->Objects[NewRelations->Count];
2111 while (PdoExtension)
2112 {
2113 /* Dump this relation */
2114 DPRINT1(" QDR PDO %08x (x %08x)%s\n",
2115 PdoExtension->PhysicalDeviceObject,
2116 PdoExtension,
2117 PdoExtension->NotPresent ?
2118 "<Omitted, device flaged not present>" : "");
2119
2120 /* Is this PDO present? */
2121 if (!PdoExtension->NotPresent)
2122 {
2123 /* Reference it and add it to the array */
2124 DeviceObject = PdoExtension->PhysicalDeviceObject;
2125 ObfReferenceObject(DeviceObject);
2126 *ObjectArray++ = DeviceObject;
2127 }
2128
2129 /* Go to the next PDO */
2130 PdoExtension = PdoExtension->Next;
2131 }
2132
2133 /* Terminate dumping the relations */
2134 DPRINT1(" QDR Total PDO count = %d (%d already in list)\n",
2135 NewRelations->Count + PdoCount,
2136 NewRelations->Count);
2137
2138 /* Return the final count and the new buffer */
2139 NewRelations->Count += PdoCount;
2140 *pDeviceRelations = NewRelations;
2141 return STATUS_SUCCESS;
2142 }
2143
2144 NTSTATUS
2145 NTAPI
2146 PciSetResources(IN PPCI_PDO_EXTENSION PdoExtension,
2147 IN BOOLEAN DoReset,
2148 IN BOOLEAN SomethingSomethingDarkSide)
2149 {
2150 PPCI_FDO_EXTENSION FdoExtension;
2151 UCHAR NewCacheLineSize, NewLatencyTimer;
2152 PCI_COMMON_HEADER PciData;
2153 BOOLEAN Native;
2154 PPCI_CONFIGURATOR Configurator;
2155
2156 /* Get the FDO and read the configuration data */
2157 FdoExtension = PdoExtension->ParentFdoExtension;
2158 PciReadDeviceConfig(PdoExtension, &PciData, 0, PCI_COMMON_HDR_LENGTH);
2159
2160 /* Make sure this is still the same device */
2161 if (!PcipIsSameDevice(PdoExtension, &PciData))
2162 {
2163 /* Fail */
2164 ASSERTMSG(FALSE, "PCI Set resources - not same device");
2165 return STATUS_DEVICE_DOES_NOT_EXIST;
2166 }
2167
2168 /* Nothing to set for a host bridge */
2169 if ((PdoExtension->BaseClass == PCI_CLASS_BRIDGE_DEV) &&
2170 (PdoExtension->SubClass == PCI_SUBCLASS_BR_HOST))
2171 {
2172 /* Fake success */
2173 return STATUS_SUCCESS;
2174 }
2175
2176 /* Check if an IDE controller is being reset */
2177 if ((DoReset) &&
2178 (PdoExtension->BaseClass == PCI_CLASS_MASS_STORAGE_CTLR) &&
2179 (PdoExtension->SubClass == PCI_SUBCLASS_MSC_IDE_CTLR))
2180 {
2181 /* Turn off native mode */
2182 Native = PciConfigureIdeController(PdoExtension, &PciData, FALSE);
2183 ASSERT(Native == PdoExtension->IDEInNativeMode);
2184 }
2185
2186 /* Check for update of a hotplug device, or first configuration of one */
2187 if ((PdoExtension->NeedsHotPlugConfiguration) &&
2188 (FdoExtension->HotPlugParameters.Acquired))
2189 {
2190 /* Don't have hotplug devices to test with yet, QEMU 0.14 should */
2191 UNIMPLEMENTED;
2192 while (TRUE);
2193 }
2194
2195 /* Locate the correct resource configurator for this type of device */
2196 Configurator = &PciConfigurators[PdoExtension->HeaderType];
2197
2198 /* Apply the settings change */
2199 Configurator->ChangeResourceSettings(PdoExtension, &PciData);
2200
2201 /* Assume no update needed */
2202 PdoExtension->UpdateHardware = FALSE;
2203
2204 /* Check if a reset is needed */
2205 if (DoReset)
2206 {
2207 /* Reset resources */
2208 Configurator->ResetDevice(PdoExtension, &PciData);
2209 PciData.u.type0.InterruptLine = PdoExtension->RawInterruptLine;
2210 }
2211
2212 /* Check if the latency timer changed */
2213 NewLatencyTimer = PdoExtension->SavedLatencyTimer;
2214 if (PciData.LatencyTimer != NewLatencyTimer)
2215 {
2216 /* Debug notification */
2217 DPRINT1("PCI (pdox %08x) changing latency from %02x to %02x.\n",
2218 PdoExtension,
2219 PciData.LatencyTimer,
2220 NewLatencyTimer);
2221 }
2222
2223 /* Check if the cache line changed */
2224 NewCacheLineSize = PdoExtension->SavedCacheLineSize;
2225 if (PciData.CacheLineSize != NewCacheLineSize)
2226 {
2227 /* Debug notification */
2228 DPRINT1("PCI (pdox %08x) changing cache line size from %02x to %02x.\n",
2229 PdoExtension,
2230 PciData.CacheLineSize,
2231 NewCacheLineSize);
2232 }
2233
2234 /* Inherit data from PDO extension */
2235 PciData.LatencyTimer = PdoExtension->SavedLatencyTimer;
2236 PciData.CacheLineSize = PdoExtension->SavedCacheLineSize;
2237 PciData.u.type0.InterruptLine = PdoExtension->RawInterruptLine;
2238
2239 /* Apply any resource hacks required */
2240 PciApplyHacks(FdoExtension,
2241 &PciData,
2242 PdoExtension->Slot,
2243 PCI_HACK_FIXUP_BEFORE_UPDATE,
2244 PdoExtension);
2245
2246 /* Check if I/O space was disabled by administrator or driver */
2247 if (PdoExtension->IoSpaceNotRequired)
2248 {
2249 /* Don't turn on the decode */
2250 PdoExtension->CommandEnables &= ~PCI_ENABLE_IO_SPACE;
2251 }
2252
2253 /* Update the device with the new settings */
2254 PciUpdateHardware(PdoExtension, &PciData);
2255
2256 /* Update complete */
2257 PdoExtension->RawInterruptLine = PciData.u.type0.InterruptLine;
2258 PdoExtension->NeedsHotPlugConfiguration = FALSE;
2259 return STATUS_SUCCESS;
2260 }
2261
2262 /* EOF */
A free Windows-compatible Operating System