drivers/network/dd/e1000/e1000hw.h

   1 /*
   2  * PROJECT:     ReactOS Intel PRO/1000 Driver
   3  * LICENSE:     GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
   4  * PURPOSE:     Intel PRO/1000 driver definitions
   5  * COPYRIGHT:   Copyright 2018 Mark Jansen (mark.jansen@reactos.org)
   6  */
   7
   8 #pragma once
   9
  10 #define IEEE_802_ADDR_LENGTH 6
  11
  12 #define HW_VENDOR_INTEL     0x8086
  13
  14 #define MAX_RESET_ATTEMPTS  10
  15
  16 #define MAX_PHY_REG_ADDRESS         0x1F
  17 #define MAX_PHY_READ_ATTEMPTS       1800
  18
  19 #define MAX_EEPROM_READ_ATTEMPTS    10000
  20
  21
  22 #define MAXIMUM_MULTICAST_ADDRESSES 16
  23
  24
  25 /* Ethernet frame header */
  26 typedef struct _ETH_HEADER {
  27     UCHAR Destination[IEEE_802_ADDR_LENGTH];
  28     UCHAR Source[IEEE_802_ADDR_LENGTH];
  29     USHORT PayloadType;
  30 } ETH_HEADER, *PETH_HEADER;
  31
  32
  33
  34
  35
  36 /* Registers */
  37 #define E1000_REG_CTRL              0x0000      /* Device Control Register, R/W */
  38 #define E1000_REG_STATUS            0x0008      /* Device Status Register, R */
  39 #define E1000_REG_EERD              0x0014      /* EEPROM Read Register, R/W */
  40 #define E1000_REG_MDIC              0x0020      /* MDI Control Register, R/W */
  41 #define E1000_REG_VET               0x0038      /* VLAN Ether Type, R/W */
  42 #define E1000_REG_ICR               0x00C0      /* Interrupt Cause Read, R/clr */
  43
  44 #define E1000_REG_IMS               0x00D0      /* Interrupt Mask Set/Read Register, R/W */
  45 #define E1000_REG_IMC               0x00D8      /* Interrupt Mask Clear, W */
  46 #define E1000_REG_RCTL              0x0100      /* Receive Control, R/W */
  47
  48 #define E1000_REG_RAL               0x5400      /* Receive Address Low, R/W */
  49 #define E1000_REG_RAH               0x5404      /* Receive Address High, R/W */
  50
  51
  52 /* E1000_REG_CTRL */
  53 #define E1000_CTRL_RST              (1 << 26)   /* Device Reset, Self clearing */
  54
  55
  56 /* E1000_REG_STATUS */
  57 #define E1000_STATUS_LU             (1 << 0)    /* Link Up Indication */
  58 #define E1000_STATUS_SPEEDSHIFT     6           /* Link speed setting */
  59 #define E1000_STATUS_SPEEDMASK      (3 << E1000_STATUS_SPEEDSHIFT)
  60
  61
  62 /* E1000_REG_EERD */
  63 #define E1000_EERD_START            (1 << 0)    /* Start Read*/
  64 #define E1000_EERD_DONE             (1 << 4)    /* Read Done */
  65 #define E1000_EERD_ADDR_SHIFT       8
  66 #define E1000_EERD_DATA_SHIFT       16
  67
  68
  69 /* E1000_REG_MDIC */
  70 #define E1000_MDIC_REGADD_SHIFT     16          /* PHY Register Address */
  71 #define E1000_MDIC_PHYADD_SHIFT     21          /* PHY Address (1=Gigabit, 2=PCIe) */
  72 #define E1000_MDIC_PHYADD_GIGABIT   1
  73 #define E1000_MDIC_OP_READ          (2 << 26)   /* Opcode */
  74 #define E1000_MDIC_R                (1 << 28)   /* Ready Bit */
  75 #define E1000_MDIC_E                (1 << 30)   /* Error */
  76
  77
  78 /* E1000_REG_IMS */
  79 #define E1000_IMS_LSC               (1 << 2)    /* Sets mask for Link Status Change */
  80
  81
  82 /* E1000_REG_RCTL */
  83 #define E1000_RCTL_EN               (1 << 1)    /* Receiver Enable */
  84 #define E1000_RCTL_SBP              (1 << 2)    /* Store Bad Packets */
  85 #define E1000_RCTL_UPE              (1 << 3)    /* Unicast Promiscuous Enabled */
  86 #define E1000_RCTL_MPE              (1 << 4)    /* Multicast Promiscuous Enabled */
  87 #define E1000_RCTL_BAM              (1 << 15)   /* Broadcast Accept Mode */
  88 #define E1000_RCTL_PMCF             (1 << 23)   /* Pass MAC Control Frames */
  89
  90 #define E1000_RCTL_FILTER_BITS      (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF)
  91
  92 /* E1000_REG_RAH */
  93 #define E1000_RAH_AV                (1 << 31)   /* Address Valid */
  94
  95
  96
  97
  98 /* NVM */
  99 #define E1000_NVM_REG_CHECKSUM      0x03f
 100 #define NVM_MAGIC_SUM               0xBABA
 101
 102
 103
 104 /* PHY (Read with MDIC) */
 105
 106 #define E1000_PHY_STATUS            0x01
 107 #define E1000_PHY_SPECIFIC_STATUS   0x11
 108
 109
 110 /* E1000_PHY_STATUS */
 111 #define E1000_PS_LINK_STATUS        (1 << 2)
 112
 113
 114
 115 /* E1000_PHY_SPECIFIC_STATUS */
 116 #define E1000_PSS_SPEED_AND_DUPLEX  (1 << 11)   /* Speed and Duplex Resolved */
 117 #define E1000_PSS_SPEEDSHIFT        14
 118 #define E1000_PSS_SPEEDMASK         (3 << E1000_PSS_SPEEDSHIFT)
 119