drivers/network/dd/e1000/e1000hw.h

   1 /*
   2  * PROJECT:     ReactOS Intel PRO/1000 Driver
   3  * LICENSE:     GPL-2.0+ (https://spdx.org/licenses/GPL-2.0+)
   4  * PURPOSE:     Hardware specific definitions
   5  * COPYRIGHT:   2018 Mark Jansen (mark.jansen@reactos.org)
   6  *              2019 Victor Perevertkin (victor.perevertkin@reactos.org)
   7  */
   8
   9 #pragma once
  10
  11 #define IEEE_802_ADDR_LENGTH 6
  12
  13 #define HW_VENDOR_INTEL     0x8086
  14
  15 #define MAX_RESET_ATTEMPTS  10
  16
  17 #define MAX_PHY_REG_ADDRESS         0x1F
  18 #define MAX_PHY_READ_ATTEMPTS       1800
  19
  20 #define MAX_EEPROM_READ_ATTEMPTS    10000
  21
  22
  23 #define MAXIMUM_MULTICAST_ADDRESSES 16
  24
  25
  26 /* Ethernet frame header */
  27 typedef struct _ETH_HEADER {
  28     UCHAR Destination[IEEE_802_ADDR_LENGTH];
  29     UCHAR Source[IEEE_802_ADDR_LENGTH];
  30     USHORT PayloadType;
  31 } ETH_HEADER, *PETH_HEADER;
  32
  33
  34 C_ASSERT(sizeof(ETH_HEADER) == 14);
  35
  36
  37 typedef enum _E1000_RCVBUF_SIZE
  38 {
  39     E1000_RCVBUF_2048 = 0,
  40     E1000_RCVBUF_1024 = 1,
  41     E1000_RCVBUF_512 = 2,
  42     E1000_RCVBUF_256 = 3,
  43
  44     E1000_RCVBUF_INDEXMASK = 3,
  45     E1000_RCVBUF_RESERVED = 4 | 0,
  46
  47     E1000_RCVBUF_16384 = 4 | 1,
  48     E1000_RCVBUF_8192 =  4 | 2,
  49     E1000_RCVBUF_4096 =  4 | 3,
  50 } E1000_RCVBUF_SIZE;
  51
  52
  53
  54 #include <pshpack1.h>
  55
  56
  57 /* 3.2.3 Receive Descriptor Format */
  58
  59 #define E1000_RDESC_STATUS_PIF          (1 << 7)    /* Passed in-exact filter */
  60 #define E1000_RDESC_STATUS_IXSM         (1 << 2)    /* Ignore Checksum Indication */
  61 #define E1000_RDESC_STATUS_EOP          (1 << 1)    /* End of Packet */
  62 #define E1000_RDESC_STATUS_DD           (1 << 0)    /* Descriptor Done */
  63
  64 typedef struct _E1000_RECEIVE_DESCRIPTOR
  65 {
  66     UINT64 Address;
  67
  68     USHORT Length;
  69     USHORT Checksum;
  70     UCHAR Status;
  71     UCHAR Errors;
  72     USHORT Special;
  73
  74 } E1000_RECEIVE_DESCRIPTOR, *PE1000_RECEIVE_DESCRIPTOR;
  75
  76
  77 /* 3.3.3 Legacy Transmit Descriptor Format */
  78
  79 #define E1000_TDESC_CMD_IDE             (1 << 7)    /* Interrupt Delay Enable */
  80 #define E1000_TDESC_CMD_RS              (1 << 3)    /* Report Status */
  81 #define E1000_TDESC_CMD_IFCS            (1 << 1)    /* Insert FCS */
  82 #define E1000_TDESC_CMD_EOP             (1 << 0)    /* End Of Packet */
  83
  84 #define E1000_TDESC_STATUS_DD           (1 << 0)    /* Descriptor Done */
  85
  86 typedef struct _E1000_TRANSMIT_DESCRIPTOR
  87 {
  88     UINT64 Address;
  89
  90     USHORT Length;
  91     UCHAR ChecksumOffset;
  92     UCHAR Command;
  93     UCHAR Status;
  94     UCHAR ChecksumStartField;
  95     USHORT Special;
  96
  97 } E1000_TRANSMIT_DESCRIPTOR, *PE1000_TRANSMIT_DESCRIPTOR;
  98
  99 #include <poppack.h>
 100
 101
 102 C_ASSERT(sizeof(E1000_RECEIVE_DESCRIPTOR) == 16);
 103 C_ASSERT(sizeof(E1000_TRANSMIT_DESCRIPTOR) == 16);
 104
 105
 106 /* Valid Range: 80-256 for 82542 and 82543 gigabit ethernet controllers
 107    Valid Range: 80-4096 for 82544 and newer */
 108 #define NUM_TRANSMIT_DESCRIPTORS        128
 109 #define NUM_RECEIVE_DESCRIPTORS         128
 110
 111
 112
 113 /* Registers */
 114 #define E1000_REG_CTRL              0x0000      /* Device Control Register, R/W */
 115 #define E1000_REG_STATUS            0x0008      /* Device Status Register, R */
 116 #define E1000_REG_EERD              0x0014      /* EEPROM Read Register, R/W */
 117 #define E1000_REG_MDIC              0x0020      /* MDI Control Register, R/W */
 118 #define E1000_REG_VET               0x0038      /* VLAN Ether Type, R/W */
 119 #define E1000_REG_ICR               0x00C0      /* Interrupt Cause Read, R/clr */
 120 #define E1000_REG_ITR               0x00C4      /* Interrupt Throttling Register, R/W */
 121
 122 #define E1000_REG_IMS               0x00D0      /* Interrupt Mask Set/Read Register, R/W */
 123 #define E1000_REG_IMC               0x00D8      /* Interrupt Mask Clear, W */
 124
 125 #define E1000_REG_RCTL              0x0100      /* Receive Control Register, R/W */
 126 #define E1000_REG_TCTL              0x0400      /* Transmit Control Register, R/W */
 127 #define E1000_REG_TIPG              0x0410      /* Transmit IPG Register, R/W */
 128
 129 #define E1000_REG_RDBAL             0x2800      /* Receive Descriptor Base Address Low, R/W */
 130 #define E1000_REG_RDBAH             0x2804      /* Receive Descriptor Base Address High, R/W */
 131 #define E1000_REG_RDLEN             0x2808      /* Receive Descriptor Length, R/W */
 132 #define E1000_REG_RDH               0x2810      /* Receive Descriptor Head, R/W */
 133 #define E1000_REG_RDT               0x2818      /* Receive Descriptor Tail, R/W */
 134 #define E1000_REG_RDTR              0x2820      /* Receive Delay Timer, R/W */
 135 #define E1000_REG_RADV              0x282C      /* Receive Absolute Delay Timer, R/W */
 136
 137 #define E1000_REG_TDBAL             0x3800      /* Transmit Descriptor Base Address Low, R/W */
 138 #define E1000_REG_TDBAH             0x3804      /* Transmit Descriptor Base Address High, R/W */
 139 #define E1000_REG_TDLEN             0x3808      /* Transmit Descriptor Length, R/W */
 140 #define E1000_REG_TDH               0x3810      /* Transmit Descriptor Head, R/W */
 141 #define E1000_REG_TDT               0x3818      /* Transmit Descriptor Tail, R/W */
 142 #define E1000_REG_TIDV              0x3820      /* Transmit Interrupt Delay Value, R/W */
 143 #define E1000_REG_TADV              0x382C      /* Transmit Absolute Delay Timer, R/W */
 144
 145
 146 #define E1000_REG_RAL               0x5400      /* Receive Address Low, R/W */
 147 #define E1000_REG_RAH               0x5404      /* Receive Address High, R/W */
 148
 149
 150 /* E1000_REG_CTRL */
 151 #define E1000_CTRL_LRST             (1 << 3)    /* Link Reset */
 152 #define E1000_CTRL_ASDE             (1 << 5)    /* Auto-Speed Detection Enable */
 153 #define E1000_CTRL_SLU              (1 << 6)    /* Set Link Up */
 154 #define E1000_CTRL_RST              (1 << 26)   /* Device Reset, Self clearing */
 155 #define E1000_CTRL_VME              (1 << 30)   /* VLAN Mode Enable */
 156
 157
 158 /* E1000_REG_STATUS */
 159 #define E1000_STATUS_FD             (1 << 0)    /* Full Duplex Indication */
 160 #define E1000_STATUS_LU             (1 << 1)    /* Link Up Indication */
 161 #define E1000_STATUS_SPEEDSHIFT     6           /* Link speed setting */
 162 #define E1000_STATUS_SPEEDMASK      (3 << E1000_STATUS_SPEEDSHIFT)
 163
 164
 165 /* E1000_REG_EERD */
 166 #define E1000_EERD_START            (1 << 0)    /* Start Read*/
 167 #define E1000_EERD_DONE             (1 << 4)    /* Read Done */
 168 #define E1000_EERD_ADDR_SHIFT       8
 169 #define E1000_EERD_DATA_SHIFT       16
 170
 171
 172 /* E1000_REG_MDIC */
 173 #define E1000_MDIC_REGADD_SHIFT     16          /* PHY Register Address */
 174 #define E1000_MDIC_PHYADD_SHIFT     21          /* PHY Address (1=Gigabit, 2=PCIe) */
 175 #define E1000_MDIC_PHYADD_GIGABIT   1
 176 #define E1000_MDIC_OP_READ          (2 << 26)   /* Opcode */
 177 #define E1000_MDIC_R                (1 << 28)   /* Ready Bit */
 178 #define E1000_MDIC_E                (1 << 30)   /* Error */
 179
 180
 181 /* E1000_REG_IMS */
 182 #define E1000_IMS_TXDW              (1 << 0)    /* Transmit Descriptor Written Back */
 183 #define E1000_IMS_TXQE              (1 << 1)    /* Transmit Queue Empty */
 184 #define E1000_IMS_LSC               (1 << 2)    /* Sets mask for Link Status Change */
 185 #define E1000_IMS_RXDMT0            (1 << 4)    /* Receive Descriptor Minimum Threshold Reached */
 186 #define E1000_IMS_RXT0              (1 << 7)    /* Receiver Timer Interrupt */
 187 #define E1000_IMS_TXD_LOW           (1 << 15)   /* Transmit Descriptor Low Threshold hit */
 188 #define E1000_IMS_SRPD              (1 << 16)   /* Small Receive Packet Detection */
 189
 190
 191 /* E1000_REG_ITR */
 192 #define MAX_INTS_PER_SEC        2000
 193 #define DEFAULT_ITR             1000000000/(MAX_INTS_PER_SEC * 256)
 194
 195
 196 /* E1000_REG_RCTL */
 197 #define E1000_RCTL_EN               (1 << 1)    /* Receiver Enable */
 198 #define E1000_RCTL_SBP              (1 << 2)    /* Store Bad Packets */
 199 #define E1000_RCTL_UPE              (1 << 3)    /* Unicast Promiscuous Enabled */
 200 #define E1000_RCTL_MPE              (1 << 4)    /* Multicast Promiscuous Enabled */
 201 #define E1000_RCTL_BAM              (1 << 15)   /* Broadcast Accept Mode */
 202 #define E1000_RCTL_BSIZE_SHIFT      16
 203 #define E1000_RCTL_PMCF             (1 << 23)   /* Pass MAC Control Frames */
 204 #define E1000_RCTL_BSEX             (1 << 25)   /* Buffer Size Extension */
 205 #define E1000_RCTL_SECRC            (1 << 26)   /* Strip Ethernet CRC from incoming packet */
 206
 207 #define E1000_RCTL_FILTER_BITS      (E1000_RCTL_SBP | E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM | E1000_RCTL_PMCF)
 208
 209
 210 /* E1000_REG_TCTL */
 211 #define E1000_TCTL_EN               (1 << 1)    /* Transmit Enable */
 212 #define E1000_TCTL_PSP              (1 << 3)    /* Pad Short Packets */
 213
 214 /* E1000_REG_TIPG */
 215 #define E1000_TIPG_IPGT_DEF         (10 << 0)   /* IPG Transmit Time */
 216 #define E1000_TIPG_IPGR1_DEF        (10 << 10)  /* IPG Receive Time 1 */
 217 #define E1000_TIPG_IPGR2_DEF        (10 << 20)  /* IPG Receive Time 2 */
 218
 219
 220 /* E1000_REG_RAH */
 221 #define E1000_RAH_AV                (1 << 31)   /* Address Valid */
 222
 223
 224
 225
 226 /* NVM */
 227 #define E1000_NVM_REG_CHECKSUM      0x03f
 228 #define NVM_MAGIC_SUM               0xBABA
 229
 230
 231
 232 /* PHY (Read with MDIC) */
 233
 234 #define E1000_PHY_STATUS            0x01
 235 #define E1000_PHY_SPECIFIC_STATUS   0x11
 236
 237
 238 /* E1000_PHY_STATUS */
 239 #define E1000_PS_LINK_STATUS        (1 << 2)
 240
 241
 242
 243 /* E1000_PHY_SPECIFIC_STATUS */
 244 #define E1000_PSS_SPEED_AND_DUPLEX  (1 << 11)   /* Speed and Duplex Resolved */
 245 #define E1000_PSS_SPEEDSHIFT        14
 246 #define E1000_PSS_SPEEDMASK         (3 << E1000_PSS_SPEEDSHIFT)