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[reactos.git] / drivers / storage / ide / uniata / atapi.h
1 /*++
2
3 Copyright (c) 2002-2005 Alexandr A. Telyatnikov (Alter)
4
5 Module Name:
6 atapi.h
7
8 Abstract:
9 This file contains IDE, ATA, ATAPI and SCSI Miniport definitions
10 and function prototypes.
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 Some definitions were taken from standard ATAPI.SYS sources from NT4 DDK by
34 Mike Glass (MGlass)
35
36 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by
37 Søren Schmidt, Copyright (c) 1998,1999,2000,2001
38
39 Code was changed/updated by
40 Alter, Copyright (c) 2002-2004
41
42
43 --*/
44 #ifndef __GLOBAL_H__
45 #define __GLOBAL_H__
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif //__cplusplus
50
51 #ifndef USER_MODE
52 #include "config.h"
53 #endif //USER_MODE
54
55 #include "scsi.h"
56 #include "stdio.h"
57 #include "string.h"
58
59 #ifdef _DEBUG
60
61
62 #ifndef _DBGNT_
63
64 #ifdef KdPrint
65 #undef KdPrint
66 #endif
67
68 #ifdef USE_DBGPRINT_LOGGER
69 #include "inc\PostDbgMesg.h"
70 #define DbgPrint DbgDump_Printf
71 #define Connect_DbgPrint() {DbgDump_SetAutoReconnect(TRUE); DbgDump_Reconnect();}
72 #else // USE_DBGPRINT_LOGGER
73 #define Connect_DbgPrint() {;}
74 #endif // USE_DBGPRINT_LOGGER
75
76 #ifdef SCSI_PORT_DBG_PRINT
77
78 SCSIPORT_API
79 VOID
80 DDKCDECLAPI
81 ScsiDebugPrint(
82 ULONG DebugPrintLevel,
83 PCCHAR DebugMessage,
84 ...
85 );
86
87 #define PRINT_PREFIX 0,
88
89 #define KdPrint3(_x_) ScsiDebugPrint _x_ {;}
90 #define KdPrint2(_x_) {ScsiDebugPrint("%x: ", PsGetCurrentThread()) ; ScsiDebugPrint _x_ ; }
91 #define KdPrint(_x_) ScsiDebugPrint _x_ {;}
92
93 #else // SCSI_PORT_DBG_PRINT
94
95 //#ifndef USE_DBGPRINT_LOGGER
96 //ULONG
97 //_cdecl
98 //DbgPrint(
99 // PCH Format,
100 // ...
101 // );
102 //#endif // USE_DBGPRINT_LOGGER
103
104 #define PRINT_PREFIX
105
106 // Note, that using DbgPrint on raised IRQL will crash w2k
107 // tis will not happen immediately, so we shall see some logs
108 //#define LOG_ON_RAISED_IRQL_W2K TRUE
109 //#define LOG_ON_RAISED_IRQL_W2K FALSE
110
111 #define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
112 #define KdPrint2(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
113 #define KdPrint(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
114 /*
115 #define PRINT_PREFIX_PTR ((PCHAR)&__tmp__kdprint__buff__)
116 #define PRINT_UPREFIX_PTR ((PWCHAR)&__tmp__kdprint__ubuff__)
117 #define PRINT_PREFIX PRINT_PREFIX_PTR,
118 #define KdPrint2(_x_) \
119 { \
120 WCHAR __tmp__kdprint__ubuff__[256]; \
121 CHAR __tmp__kdprint__buff__[256]; \
122 UNICODE_STRING __tmp__usrt__buff__; \
123 sprintf _x_; \
124 swprintf (PRINT_UPREFIX_PTR, L"%hs", PRINT_PREFIX_PTR); \
125 __tmp__usrt__buff__.Buffer = PRINT_UPREFIX_PTR; \
126 __tmp__usrt__buff__.Length = \
127 __tmp__usrt__buff__.MaximumLength = strlen(PRINT_PREFIX_PTR); \
128 NtDisplayString(&__tmp__usrt__buff__); \
129 };
130 #define KdPrint(_x_) DbgPrint _x_
131 */
132 #endif // SCSI_PORT_DBG_PRINT
133
134 //#define AtapiStallExecution(dt) { KdPrint2((" AtapiStallExecution(%d)\n", dt)); ScsiPortStallExecution(dt); }
135 #define AtapiStallExecution(dt) { ScsiPortStallExecution(dt); }
136
137 #endif // _DBGNT_
138
139 #else // _DEBUG
140
141 #define PRINT_PREFIX "UniATA: "
142
143 //#define KdPrint3(_x_) {if(LOG_ON_RAISED_IRQL_W2K || MajorVersion < 0x05 || KeGetCurrentIrql() <= 2){/*DbgPrint("%x: ", PsGetCurrentThread()) ;*/ DbgPrint _x_ ; if(g_LogToDisplay){ PrintNtConsole _x_ ;} }}
144 #define KdPrint3(_x_) {;}
145 #define KdPrint2(_x_) {;}
146 #define KdPrint(_x_) {;}
147 #define Connect_DbgPrint() {;}
148
149 #define AtapiStallExecution(dt) ScsiPortStallExecution(dt)
150
151 #endif // _DEBUG
152
153 // IDE register definition
154
155 #pragma pack(push, 1)
156
157 typedef union _IDE_REGISTERS_1 {
158 struct _o {
159 UCHAR Data;
160 UCHAR Feature;
161 UCHAR BlockCount;
162 UCHAR BlockNumber;
163 UCHAR CylinderLow;
164 UCHAR CylinderHigh;
165 UCHAR DriveSelect;
166 UCHAR Command;
167 } o;
168
169 struct _i {
170 UCHAR Data;
171 UCHAR Error;
172 UCHAR BlockCount;
173 UCHAR BlockNumber;
174 UCHAR CylinderLow;
175 UCHAR CylinderHigh;
176 UCHAR DriveSelect;
177 UCHAR Status;
178 } i;
179
180 } IDE_REGISTERS_1, *PIDE_REGISTERS_1;
181
182 #define IDX_IO1 0
183 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)
184
185 #define IDX_IO1 0
186 #define IDX_IO1_SZ sizeof(IDE_REGISTERS_1)
187 #define IDX_IO1_i_Data (FIELD_OFFSET(IDE_REGISTERS_1, i.Data )+IDX_IO1)
188 #define IDX_IO1_i_Error (FIELD_OFFSET(IDE_REGISTERS_1, i.Error )+IDX_IO1)
189 #define IDX_IO1_i_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockCount )+IDX_IO1)
190 #define IDX_IO1_i_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, i.BlockNumber )+IDX_IO1)
191 #define IDX_IO1_i_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderLow )+IDX_IO1)
192 #define IDX_IO1_i_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, i.CylinderHigh)+IDX_IO1)
193 #define IDX_IO1_i_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, i.DriveSelect )+IDX_IO1)
194 #define IDX_IO1_i_Status (FIELD_OFFSET(IDE_REGISTERS_1, i.Status )+IDX_IO1)
195
196 #define IDX_IO1_o IDX_IO1_SZ
197 #define IDX_IO1_o_SZ sizeof(IDE_REGISTERS_1)
198
199 #define IDX_IO1_o_Data (FIELD_OFFSET(IDE_REGISTERS_1, o.Data )+IDX_IO1_o)
200 #define IDX_IO1_o_Feature (FIELD_OFFSET(IDE_REGISTERS_1, o.Feature )+IDX_IO1_o)
201 #define IDX_IO1_o_BlockCount (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockCount )+IDX_IO1_o)
202 #define IDX_IO1_o_BlockNumber (FIELD_OFFSET(IDE_REGISTERS_1, o.BlockNumber )+IDX_IO1_o)
203 #define IDX_IO1_o_CylinderLow (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderLow )+IDX_IO1_o)
204 #define IDX_IO1_o_CylinderHigh (FIELD_OFFSET(IDE_REGISTERS_1, o.CylinderHigh)+IDX_IO1_o)
205 #define IDX_IO1_o_DriveSelect (FIELD_OFFSET(IDE_REGISTERS_1, o.DriveSelect )+IDX_IO1_o)
206 #define IDX_IO1_o_Command (FIELD_OFFSET(IDE_REGISTERS_1, o.Command )+IDX_IO1_o)
207
208 typedef struct _IDE_REGISTERS_2 {
209 UCHAR AltStatus;
210 UCHAR DriveAddress;
211 } IDE_REGISTERS_2, *PIDE_REGISTERS_2;
212
213 #define IDX_IO2 (IDX_IO1_o+IDX_IO1_o_SZ)
214 #define IDX_IO2_SZ sizeof(IDE_REGISTERS_2)
215
216 #define IDX_IO2_AltStatus (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2)
217 #define IDX_IO2_DriveAddress (FIELD_OFFSET(IDE_REGISTERS_2, DriveAddress)+IDX_IO2)
218
219 #define IDX_IO2_o (IDX_IO2+IDX_IO2_SZ)
220 #define IDX_IO2_o_SZ sizeof(IDE_REGISTERS_2)
221
222 #define IDX_IO2_o_Control (FIELD_OFFSET(IDE_REGISTERS_2, AltStatus )+IDX_IO2_o)
223 //
224 // Device Extension Device Flags
225 //
226
227 #define DFLAGS_DEVICE_PRESENT 0x0001 // Indicates that some device is present.
228 #define DFLAGS_ATAPI_DEVICE 0x0002 // Indicates whether ATAPI commands can be used.
229 #define DFLAGS_TAPE_DEVICE 0x0004 // Indicates whether this is a tape device.
230 #define DFLAGS_INT_DRQ 0x0008 // Indicates whether device interrupts as DRQ is set after
231 // receiving ATAPI Packet Command
232 #define DFLAGS_REMOVABLE_DRIVE 0x0010 // Indicates that the drive has the 'removable' bit set in
233 // identify data (offset 128)
234 #define DFLAGS_MEDIA_STATUS_ENABLED 0x0020 // Media status notification enabled
235 #define DFLAGS_ATAPI_CHANGER 0x0040 // Indicates atapi 2.5 changer present.
236 #define DFLAGS_SANYO_ATAPI_CHANGER 0x0080 // Indicates multi-platter device, not conforming to the 2.5 spec.
237 #define DFLAGS_CHANGER_INITED 0x0100 // Indicates that the init path for changers has already been done.
238 #define DFLAGS_LBA_ENABLED 0x0200 // Indicates that we should use LBA addressing rather than CHS
239 #define DFLAGS_DWORDIO_ENABLED 0x0400 // Indicates that we should use 32-bit IO
240 #define DFLAGS_WCACHE_ENABLED 0x0800 // Indicates that we use write cache
241 #define DFLAGS_RCACHE_ENABLED 0x1000 // Indicates that we use read cache
242 #define DFLAGS_ORIG_GEOMETRY 0x2000 //
243 #define DFLAGS_REINIT_DMA 0x4000 //
244 #define DFLAGS_HIDDEN 0x8000 // Hidden device, available only with special IOCTLs
245 // via communication virtual device
246 //#define DFLAGS_ 0x10000 //
247 //
248 // Used to disable 'advanced' features.
249 //
250
251 #define MAX_ERRORS 4
252
253 //
254 // ATAPI command definitions
255 //
256
257 #define ATAPI_MODE_SENSE 0x5A
258 #define ATAPI_MODE_SELECT 0x55
259 #define ATAPI_FORMAT_UNIT 0x24
260
261 // ATAPI Command Descriptor Block
262
263 typedef struct _MODE_SENSE_10 {
264 UCHAR OperationCode;
265 UCHAR Reserved1;
266 UCHAR PageCode : 6;
267 UCHAR Pc : 2;
268 UCHAR Reserved2[4];
269 UCHAR ParameterListLengthMsb;
270 UCHAR ParameterListLengthLsb;
271 UCHAR Reserved3[3];
272 } MODE_SENSE_10, *PMODE_SENSE_10;
273
274 typedef struct _MODE_SELECT_10 {
275 UCHAR OperationCode;
276 UCHAR Reserved1 : 4;
277 UCHAR PFBit : 1;
278 UCHAR Reserved2 : 3;
279 UCHAR Reserved3[5];
280 UCHAR ParameterListLengthMsb;
281 UCHAR ParameterListLengthLsb;
282 UCHAR Reserved4[3];
283 } MODE_SELECT_10, *PMODE_SELECT_10;
284
285 typedef struct _MODE_PARAMETER_HEADER_10 {
286 UCHAR ModeDataLengthMsb;
287 UCHAR ModeDataLengthLsb;
288 UCHAR MediumType;
289 UCHAR Reserved[5];
290 }MODE_PARAMETER_HEADER_10, *PMODE_PARAMETER_HEADER_10;
291
292 //
293 // IDE command definitions
294 //
295
296 #define IDE_COMMAND_ATAPI_RESET 0x08
297 #define IDE_COMMAND_RECALIBRATE 0x10
298 #define IDE_COMMAND_READ 0x20
299 #define IDE_COMMAND_READ_NO_RETR 0x21
300 #define IDE_COMMAND_READ48 0x24
301 #define IDE_COMMAND_READ_DMA48 0x25
302 #define IDE_COMMAND_READ_DMA_Q48 0x26
303 #define IDE_COMMAND_READ_NATIVE_SIZE48 0x27
304 #define IDE_COMMAND_READ_MUL48 0x29
305 #define IDE_COMMAND_READ_STREAM_DMA48 0x2A
306 #define IDE_COMMAND_READ_STREAM48 0x2B
307 #define IDE_COMMAND_READ_LOG48 0x2f
308 #define IDE_COMMAND_WRITE 0x30
309 #define IDE_COMMAND_WRITE_NO_RETR 0x31
310 #define IDE_COMMAND_WRITE48 0x34
311 #define IDE_COMMAND_WRITE_DMA48 0x35
312 #define IDE_COMMAND_WRITE_DMA_Q48 0x36
313 #define IDE_COMMAND_SET_NATIVE_SIZE48 0x37
314 #define IDE_COMMAND_WRITE_MUL48 0x39
315 #define IDE_COMMAND_WRITE_STREAM_DMA48 0x3a
316 #define IDE_COMMAND_WRITE_STREAM48 0x3b
317 #define IDE_COMMAND_WRITE_FUA_DMA48 0x3d
318 #define IDE_COMMAND_WRITE_FUA_DMA_Q48 0x3e
319 #define IDE_COMMAND_WRITE_LOG48 0x3f
320 #define IDE_COMMAND_VERIFY 0x40
321 #define IDE_COMMAND_VERIFY48 0x42
322 #define IDE_COMMAND_READ_LOG_DMA48 0x47
323 #define IDE_COMMAND_WRITE_LOG_DMA48 0x57
324 #define IDE_COMMAND_TRUSTED_RCV 0x5c
325 #define IDE_COMMAND_TRUSTED_RCV_DMA 0x5d
326 #define IDE_COMMAND_TRUSTED_SEND 0x5e
327 #define IDE_COMMAND_TRUSTED_SEND_DMA 0x5f
328 #define IDE_COMMAND_SEEK 0x70
329 #define IDE_COMMAND_SET_DRIVE_PARAMETERS 0x91
330 #define IDE_COMMAND_ATAPI_PACKET 0xA0
331 #define IDE_COMMAND_ATAPI_IDENTIFY 0xA1
332 #define IDE_COMMAND_READ_MULTIPLE 0xC4
333 #define IDE_COMMAND_WRITE_MULTIPLE 0xC5
334 #define IDE_COMMAND_SET_MULTIPLE 0xC6
335 #define IDE_COMMAND_READ_DMA_Q 0xC7
336 #define IDE_COMMAND_READ_DMA 0xC8
337 #define IDE_COMMAND_WRITE_DMA 0xCA
338 #define IDE_COMMAND_WRITE_DMA_Q 0xCC
339 #define IDE_COMMAND_WRITE_MUL_FUA48 0xCE
340 #define IDE_COMMAND_GET_MEDIA_STATUS 0xDA
341 #define IDE_COMMAND_DOOR_LOCK 0xDE
342 #define IDE_COMMAND_DOOR_UNLOCK 0xDF
343 #define IDE_COMMAND_STANDBY_IMMED 0xE0 // flush and spin down
344 #define IDE_COMMAND_STANDBY 0xE2 // flush and spin down and enable autopowerdown timer
345 #define IDE_COMMAND_SLEEP 0xE6 // flush, spin down and deactivate interface
346 #define IDE_COMMAND_FLUSH_CACHE 0xE7
347 #define IDE_COMMAND_IDENTIFY 0xEC
348 #define IDE_COMMAND_MEDIA_EJECT 0xED
349 #define IDE_COMMAND_FLUSH_CACHE48 0xEA
350 #define IDE_COMMAND_ENABLE_MEDIA_STATUS 0xEF
351 #define IDE_COMMAND_SET_FEATURES 0xEF /* features command,
352 IDE_COMMAND_ENABLE_MEDIA_STATUS */
353 #define IDE_COMMAND_READ_NATIVE_SIZE 0xF8
354 #define IDE_COMMAND_SET_NATIVE_SIZE 0xF9
355
356 #define SCSIOP_ATA_PASSTHROUGH 0xCC //
357
358 //
359 // IDE status definitions
360 //
361
362 #define IDE_STATUS_SUCCESS 0x00
363 #define IDE_STATUS_ERROR 0x01
364 #define IDE_STATUS_INDEX 0x02
365 #define IDE_STATUS_CORRECTED_ERROR 0x04
366 #define IDE_STATUS_DRQ 0x08
367 #define IDE_STATUS_DSC 0x10
368 //#define IDE_STATUS_DWF 0x10 /* drive write fault */
369 #define IDE_STATUS_DMA 0x20 /* DMA ready */
370 #define IDE_STATUS_DWF 0x20 /* drive write fault */
371 #define IDE_STATUS_DRDY 0x40
372 #define IDE_STATUS_IDLE 0x50
373 #define IDE_STATUS_BUSY 0x80
374
375
376 //
377 // IDE drive select/head definitions
378 //
379
380 #define IDE_DRIVE_SELECT 0xA0
381 #define IDE_DRIVE_1 0x00
382 #define IDE_DRIVE_2 0x10
383 #define IDE_DRIVE_SELECT_1 (IDE_DRIVE_SELECT | IDE_DRIVE_1)
384 #define IDE_DRIVE_SELECT_2 (IDE_DRIVE_SELECT | IDE_DRIVE_2)
385
386 #define IDE_USE_LBA 0x40
387
388 //
389 // IDE drive control definitions
390 //
391
392 #define IDE_DC_DISABLE_INTERRUPTS 0x02
393 #define IDE_DC_RESET_CONTROLLER 0x04
394 #define IDE_DC_A_4BIT 0x80
395 #define IDE_DC_USE_HOB 0x80 // use high-order byte(s)
396 #define IDE_DC_REENABLE_CONTROLLER 0x00
397
398 // IDE error definitions
399 //
400
401 #define IDE_ERROR_ICRC 0x80
402 #define IDE_ERROR_BAD_BLOCK 0x80
403 #define IDE_ERROR_DATA_ERROR 0x40
404 #define IDE_ERROR_MEDIA_CHANGE 0x20
405 #define IDE_ERROR_ID_NOT_FOUND 0x10
406 #define IDE_ERROR_MEDIA_CHANGE_REQ 0x08
407 #define IDE_ERROR_COMMAND_ABORTED 0x04
408 #define IDE_ERROR_END_OF_MEDIA 0x02
409 #define IDE_ERROR_NO_MEDIA 0x02
410 #define IDE_ERROR_ILLEGAL_LENGTH 0x01
411
412 //
413 // ATAPI register definition
414 //
415
416 typedef union _ATAPI_REGISTERS_1 {
417 struct _o {
418 UCHAR Data;
419 UCHAR Feature;
420 UCHAR Unused0;
421 UCHAR Unused1;
422 UCHAR ByteCountLow;
423 UCHAR ByteCountHigh;
424 UCHAR DriveSelect;
425 UCHAR Command;
426 } o;
427
428 struct _i {
429 UCHAR Data;
430 UCHAR Error;
431 UCHAR InterruptReason;
432 UCHAR Unused1;
433 UCHAR ByteCountLow;
434 UCHAR ByteCountHigh;
435 UCHAR DriveSelect;
436 UCHAR Status;
437 } i;
438
439 //IDE_REGISTERS_1 ide;
440
441 } ATAPI_REGISTERS_1, *PATAPI_REGISTERS_1;
442
443 #define IDX_ATAPI_IO1 IDX_IO1
444 #define IDX_ATAPI_IO1_SZ sizeof(ATAPI_REGISTERS_1)
445
446 #define IDX_ATAPI_IO1_i_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Data )+IDX_ATAPI_IO1)
447 #define IDX_ATAPI_IO1_i_Error (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Error )+IDX_ATAPI_IO1)
448 #define IDX_ATAPI_IO1_i_InterruptReason (FIELD_OFFSET(ATAPI_REGISTERS_1, i.InterruptReason)+IDX_ATAPI_IO1)
449 #define IDX_ATAPI_IO1_i_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Unused1 )+IDX_ATAPI_IO1)
450 #define IDX_ATAPI_IO1_i_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountLow )+IDX_ATAPI_IO1)
451 #define IDX_ATAPI_IO1_i_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, i.ByteCountHigh )+IDX_ATAPI_IO1)
452 #define IDX_ATAPI_IO1_i_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, i.DriveSelect )+IDX_ATAPI_IO1)
453 #define IDX_ATAPI_IO1_i_Status (FIELD_OFFSET(ATAPI_REGISTERS_1, i.Status )+IDX_ATAPI_IO1)
454
455 #define IDX_ATAPI_IO1_o_Data (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Data )+IDX_ATAPI_IO1)
456 #define IDX_ATAPI_IO1_o_Feature (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Feature )+IDX_ATAPI_IO1)
457 #define IDX_ATAPI_IO1_o_Unused0 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused0 )+IDX_ATAPI_IO1)
458 #define IDX_ATAPI_IO1_o_Unused1 (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Unused1 )+IDX_ATAPI_IO1)
459 #define IDX_ATAPI_IO1_o_ByteCountLow (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountLow )+IDX_ATAPI_IO1)
460 #define IDX_ATAPI_IO1_o_ByteCountHigh (FIELD_OFFSET(ATAPI_REGISTERS_1, o.ByteCountHigh)+IDX_ATAPI_IO1)
461 #define IDX_ATAPI_IO1_o_DriveSelect (FIELD_OFFSET(ATAPI_REGISTERS_1, o.DriveSelect )+IDX_ATAPI_IO1)
462 #define IDX_ATAPI_IO1_o_Command (FIELD_OFFSET(ATAPI_REGISTERS_1, o.Command )+IDX_ATAPI_IO1)
463
464 /*
465 typedef union _ATAPI_REGISTERS_2 {
466 struct {
467 UCHAR AltStatus;
468 UCHAR DriveAddress;
469 };
470
471 //IDE_REGISTERS_2 ide;
472
473 } ATAPI_REGISTERS_2, *PATAPI_REGISTERS_2;
474
475 #define IDX_ATAPI_IO2 IDX_ATAPI_IO2_SZ
476 #define IDX_ATAPI_IO2_SZ sizeof(ATAPI_REGISTERS_2)
477 */
478
479 //
480 // ATAPI interrupt reasons
481 //
482
483 #define ATAPI_IR_COD 0x01
484 #define ATAPI_IR_IO 0x02
485
486 //
487 // ATA Features
488 //
489
490 #define ATA_F_DMA 0x01 /* enable DMA */
491 #define ATA_F_OVL 0x02 /* enable overlap */
492
493 #define ATA_C_F_SETXFER 0x03 /* set transfer mode */
494
495 #define ATA_C_F_ENAB_WCACHE 0x02 /* enable write cache */
496 #define ATA_C_F_DIS_WCACHE 0x82 /* disable write cache */
497
498 #define ATA_C_F_ENAB_RCACHE 0xaa /* enable readahead cache */
499 #define ATA_C_F_DIS_RCACHE 0x55 /* disable readahead cache */
500
501 #define ATA_C_F_ENAB_RELIRQ 0x5d /* enable release interrupt */
502 #define ATA_C_F_DIS_RELIRQ 0xdd /* disable release interrupt */
503
504 #define ATA_C_F_ENAB_SRVIRQ 0x5e /* enable service interrupt */
505 #define ATA_C_F_DIS_SRVIRQ 0xde /* disable service interrupt */
506
507 #define ATA_C_F_ENAB_MEDIASTAT 0x95 /* enable media status */
508 #define ATA_C_F_DIS_MEDIASTAT 0x31 /* disable media status */
509
510 //
511 // ATAPI interrupt reasons
512 //
513
514 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
515 #define ATA_I_IN 0x02 /* read (1) | write (0) */
516 #define ATA_I_RELEASE 0x04 /* released bus (1) */
517 #define ATA_I_TAGMASK 0xf8 /* tag mask */
518
519 // IDENTIFY data
520 //
521
522 typedef struct _IDENTIFY_DATA {
523 UCHAR AtapiCmdSize:2; // 00 00
524 #define ATAPI_PSIZE_12 0 /* 12 bytes */
525 #define ATAPI_PSIZE_16 1 /* 16 bytes */
526 UCHAR :3;
527 UCHAR DrqType:2; // 00 00
528 #define ATAPI_DRQT_MPROC 0 /* cpu 3 ms delay */
529 #define ATAPI_DRQT_INTR 1 /* intr 10 ms delay */
530 #define ATAPI_DRQT_ACCEL 2 /* accel 50 us delay */
531 UCHAR Removable:1;
532
533 UCHAR DeviceType:5;
534 #define ATAPI_TYPE_DIRECT 0 /* disk/floppy */
535 #define ATAPI_TYPE_TAPE 1 /* streaming tape */
536 #define ATAPI_TYPE_CDROM 5 /* CD-ROM device */
537 #define ATAPI_TYPE_OPTICAL 7 /* optical disk */
538 UCHAR :1;
539 UCHAR CmdProtocol:2; // 00 00
540 #define ATAPI_PROTO_ATAPI 2
541 // USHORT GeneralConfiguration; // 00 00
542
543 USHORT NumberOfCylinders; // 02 1
544 USHORT Reserved1; // 04 2
545 USHORT NumberOfHeads; // 06 3
546 USHORT UnformattedBytesPerTrack; // 08 4 // Now obsolete
547 USHORT UnformattedBytesPerSector; // 0A 5 // Now obsolete
548 USHORT SectorsPerTrack; // 0C 6
549
550 USHORT VendorUnique1[3]; // 0E 7-9
551 UCHAR SerialNumber[20]; // 14 10-19
552
553 USHORT BufferType; // 28 20
554 #define ATA_BT_SINGLEPORTSECTOR 1 /* 1 port, 1 sector buffer */
555 #define ATA_BT_DUALPORTMULTI 2 /* 2 port, mult sector buffer */
556 #define ATA_BT_DUALPORTMULTICACHE 3 /* above plus track cache */
557
558 USHORT BufferSectorSize; // 2A 21
559 USHORT NumberOfEccBytes; // 2C 22
560 USHORT FirmwareRevision[4]; // 2E 23-26
561 USHORT ModelNumber[20]; // 36 27-46
562 UCHAR MaximumBlockTransfer; // 5E 47
563 UCHAR VendorUnique2; // 5F
564
565 USHORT DoubleWordIo; // 60 48
566
567 USHORT Reserved62_0:8; // 62 49
568 USHORT SupportDma:1;
569 USHORT SupportLba:1;
570 USHORT DisableIordy:1;
571 USHORT SupportIordy:1;
572 USHORT SoftReset:1;
573 USHORT StandbyOverlap:1;
574 USHORT SupportQTag:1; /* supports queuing overlap */
575 USHORT SupportIDma:1; /* interleaved DMA supported */
576 /* USHORT Capabilities; // 62 49
577 #define IDENTIFY_CAPABILITIES_SUPPORT_DMA 0x0100
578 #define IDENTIFY_CAPABILITIES_SUPPORT_LBA 0x0200
579 #define IDENTIFY_CAPABILITIES_DISABLE_IORDY 0x0400
580 #define IDENTIFY_CAPABILITIES_SUPPORT_IORDY 0x0800
581 #define IDENTIFY_CAPABILITIES_SOFT_RESET 0x1000
582 #define IDENTIFY_CAPABILITIES_STDBY_OVLP 0x2000
583 #define IDENTIFY_CAPABILITIES_SUPPORT_QTAG 0x4000
584 #define IDENTIFY_CAPABILITIES_SUPPORT_IDMA 0x8000*/
585
586 USHORT DeviceStandbyMin:1; // 64 50
587 USHORT Reserved50_1:13;
588 USHORT DeviceCapability1:1;
589 USHORT DeviceCapability0:1;
590 // USHORT Reserved2;
591
592 UCHAR Vendor51; // 66 51
593 UCHAR PioCycleTimingMode; // 67
594
595 UCHAR Vendor52; // 68 52
596 UCHAR DmaCycleTimingMode; // 69
597
598 USHORT TranslationFieldsValid:1; // 6A 53 /* 54-58 */
599 USHORT PioTimingsValid:1; /* 64-70 */
600 USHORT UdmaModesValid:1; /* 88 */
601 USHORT Reserved3:13;
602
603 USHORT NumberOfCurrentCylinders; // 6C 54 \-
604 USHORT NumberOfCurrentHeads; // 6E 55 \-
605 USHORT CurrentSectorsPerTrack; // 70 56 /- obsolete USHORT[5]
606 ULONG CurrentSectorCapacity; // 72 57-58 /-
607
608 USHORT CurrentMultiSector:8; // 59
609 USHORT CurrentMultiSectorValid:1;
610 USHORT Reserved59_9:7;
611
612 ULONG UserAddressableSectors; // 60-61
613
614 USHORT SingleWordDMASupport : 8; // 62 \- obsolete
615 USHORT SingleWordDMAActive : 8; // /-
616
617 USHORT MultiWordDMASupport : 8; // 63
618 USHORT MultiWordDMAActive : 8;
619
620 USHORT AdvancedPIOModes : 8; // 64
621 USHORT Reserved4 : 8;
622
623 #define AdvancedPIOModes_3 1
624 #define AdvancedPIOModes_4 2
625 #define AdvancedPIOModes_5 4 // non-standard
626
627 USHORT MinimumMWXferCycleTime; // 65
628 USHORT RecommendedMWXferCycleTime; // 66
629 USHORT MinimumPIOCycleTime; // 67
630 USHORT MinimumPIOCycleTimeIORDY; // 68
631
632 USHORT Reserved69_70[2]; // 69-70
633 USHORT ReleaseTimeOverlapped; // 71
634 USHORT ReleaseTimeServiceCommand; // 72
635 USHORT Reserved73_74[2]; // 73-74
636
637 USHORT QueueLength : 5; // 75
638 USHORT Reserved75_6 : 11;
639
640 USHORT SataCapabilities; // 76
641 #define ATA_SATA_GEN1 0x0002
642 #define ATA_SATA_GEN2 0x0004
643 #define ATA_SUPPORT_NCQ 0x0100
644 #define ATA_SUPPORT_IFPWRMNGTRCV 0x0200
645
646 USHORT Reserved77; // 77
647
648 USHORT SataSupport; // 78
649 #define ATA_SUPPORT_NONZERO 0x0002
650 #define ATA_SUPPORT_AUTOACTIVATE 0x0004
651 #define ATA_SUPPORT_IFPWRMNGT 0x0008
652 #define ATA_SUPPORT_INORDERDATA 0x0010
653
654 USHORT SataEnable; // 79
655 USHORT MajorRevision; // 80
656 USHORT MinorRevision; // 81
657
658 struct {
659 USHORT Smart:1; // 82/85
660 USHORT Security:1;
661 USHORT Removable:1;
662 USHORT PowerMngt:1;
663 USHORT Packet:1;
664 USHORT WriteCache:1;
665 USHORT LookAhead:1;
666 USHORT ReleaseDRQ:1;
667 USHORT ServiceDRQ:1;
668 USHORT Reset:1;
669 USHORT Protected:1;
670 USHORT Reserved_82_11:1;
671 USHORT WriteBuffer:1;
672 USHORT ReadBuffer:1;
673 USHORT Nop:1;
674 USHORT Reserved_82_15:1;
675
676 USHORT Microcode:1; // 83/86
677 USHORT Queued:1; //
678 USHORT CFA:1; //
679 USHORT APM:1; //
680 USHORT Notify:1; //
681 USHORT Standby:1; //
682 USHORT Spinup:1; //
683 USHORT Reserver_83_7:1;
684 USHORT MaxSecurity:1; //
685 USHORT AutoAcoustic:1; //
686 USHORT Address48:1; //
687 USHORT ConfigOverlay:1; //
688 USHORT FlushCache:1; //
689 USHORT FlushCache48:1; //
690 USHORT SupportOne:1; //
691 USHORT SupportZero:1; //
692
693 USHORT SmartErrorLog:1; // 84/87
694 USHORT SmartSelfTest:1;
695 USHORT MediaSerialNo:1;
696 USHORT MediaCardPass:1;
697 USHORT Streaming:1;
698 USHORT Logging:1;
699 USHORT Reserver_84_6:8;
700 USHORT ExtendedOne:1; //
701 USHORT ExtendedZero:1; //
702 } FeaturesSupport, FeaturesEnabled;
703
704 USHORT UltraDMASupport : 8; // 88
705 USHORT UltraDMAActive : 8;
706
707 USHORT EraseTime; // 89
708 USHORT EnhancedEraseTime; // 90
709 USHORT CurentAPMLevel; // 91
710
711 USHORT MasterPasswdRevision; // 92
712
713 USHORT HwResMaster : 8; // 93
714 USHORT HwResSlave : 5;
715 USHORT HwResCableId : 1;
716 USHORT HwResValid : 2;
717
718 USHORT CurrentAcoustic : 8; // 94
719 USHORT VendorAcoustic : 8;
720
721 USHORT StreamMinReqSize; // 95
722 USHORT StreamTransferTime; // 96
723 USHORT StreamAccessLatency; // 97
724 ULONG StreamGranularity; // 98-99
725
726 ULONGLONG UserAddressableSectors48; // 100-103
727
728 USHORT Reserved104[2]; // 104-105
729 union {
730 USHORT PhysLogSectorSize; // 106
731 struct {
732 USHORT PLSS_Size:4;
733 USHORT PLSS_Reserved:8;
734 USHORT PLSS_LargeL:1; // =1 if 117-118 are valid
735 USHORT PLSS_LargeP:1;
736 USHORT PLSS_Signature:2; // = 0x01 = 01b
737 };
738 };
739 USHORT Reserved107[10]; // 107-116
740
741 ULONG LargeSectorSize; // 117-118
742
743 USHORT Reserved117[8]; // 119-126
744
745 USHORT RemovableStatus; // 127
746 USHORT SecurityStatus; // 128
747
748 USHORT FeaturesSupport4; // 129
749 USHORT Reserved130[30]; // 130-159
750 USHORT CfAdvPowerMode; // 160
751 USHORT Reserved161[14]; // 161-175
752 USHORT MediaSerial[30]; // 176-205
753 USHORT Reserved206[49]; // 205-254
754 USHORT Integrity; // 255
755 } IDENTIFY_DATA, *PIDENTIFY_DATA;
756
757 //
758 // Identify data without the Reserved4.
759 //
760
761 #define IDENTIFY_DATA2 IDENTIFY_DATA
762 #define PIDENTIFY_DATA2 PIDENTIFY_DATA
763
764 /*typedef struct _IDENTIFY_DATA2 {
765 UCHAR AtapiCmdSize:2; // 00 00
766 UCHAR :3;
767 UCHAR DrqType:2; // 00 00
768 UCHAR Removable:1;
769
770 UCHAR DeviceType:5;
771 UCHAR :1;
772 UCHAR CmdProtocol:2; // 00 00
773 // USHORT GeneralConfiguration; // 00
774
775 USHORT NumberOfCylinders; // 02
776 USHORT Reserved1; // 04
777 USHORT NumberOfHeads; // 06
778 USHORT UnformattedBytesPerTrack; // 08
779 USHORT UnformattedBytesPerSector; // 0A
780 USHORT SectorsPerTrack; // 0C
781 USHORT VendorUnique1[3]; // 0E
782 UCHAR SerialNumber[20]; // 14
783 USHORT BufferType; // 28
784 USHORT BufferSectorSize; // 2A
785 USHORT NumberOfEccBytes; // 2C
786 USHORT FirmwareRevision[4]; // 2E
787 USHORT ModelNumber[20]; // 36
788 UCHAR MaximumBlockTransfer; // 5E
789 UCHAR VendorUnique2; // 5F
790 USHORT DoubleWordIo; // 60
791 USHORT Capabilities; // 62
792 USHORT Reserved2; // 64
793 UCHAR VendorUnique3; // 66
794 UCHAR PioCycleTimingMode; // 67
795 UCHAR VendorUnique4; // 68
796 UCHAR DmaCycleTimingMode; // 69
797 USHORT TranslationFieldsValid:1; // 6A
798 USHORT Reserved3:15;
799 USHORT NumberOfCurrentCylinders; // 6C
800 USHORT NumberOfCurrentHeads; // 6E
801 USHORT CurrentSectorsPerTrack; // 70
802 ULONG CurrentSectorCapacity; // 72
803 } IDENTIFY_DATA2, *PIDENTIFY_DATA2;*/
804
805 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
806
807 // IDENTIFY DMA timing cycle modes.
808 #define IDENTIFY_DMA_CYCLES_MODE_0 0x00
809 #define IDENTIFY_DMA_CYCLES_MODE_1 0x01
810 #define IDENTIFY_DMA_CYCLES_MODE_2 0x02
811 /*
812 #define PCI_DEV_HW_SPEC(idhi, idlo) \
813 { #idlo, 4, #idhi, 4}
814
815 typedef struct _BROKEN_CONTROLLER_INFORMATION {
816 PCHAR VendorId;
817 ULONG VendorIdLength;
818 PCHAR DeviceId;
819 ULONG DeviceIdLength;
820 }BROKEN_CONTROLLER_INFORMATION, *PBROKEN_CONTROLLER_INFORMATION;
821
822 BROKEN_CONTROLLER_INFORMATION const BrokenAdapters[] = {
823 // CMD 640 ATA controller !WARNING! buggy chip data loss possible
824 PCI_DEV_HW_SPEC( 0640, 1095 ), //{ "1095", 4, "0640", 4},
825 // ??
826 PCI_DEV_HW_SPEC( 0601, 1039 ), //{ "1039", 4, "0601", 4}
827 // RZ 100? ATA controller !WARNING! buggy chip data loss possible
828 PCI_DEV_HW_SPEC( 1000, 1042 ),
829 PCI_DEV_HW_SPEC( 1001, 1042 )
830 };
831
832 #define BROKEN_ADAPTERS (sizeof(BrokenAdapters) / sizeof(BROKEN_CONTROLLER_INFORMATION))
833
834 typedef struct _NATIVE_MODE_CONTROLLER_INFORMATION {
835 PCHAR VendorId;
836 ULONG VendorIdLength;
837 PCHAR DeviceId;
838 ULONG DeviceIdLength;
839 }NATIVE_MODE_CONTROLLER_INFORMATION, *PNATIVE_MODE_CONTROLLER_INFORMATION;
840
841 NATIVE_MODE_CONTROLLER_INFORMATION const NativeModeAdapters[] = {
842 PCI_DEV_HW_SPEC( 0105, 10ad ) //{ "10ad", 4, "0105", 4}
843 };
844
845 #define NUM_NATIVE_MODE_ADAPTERS (sizeof(NativeModeAdapters) / sizeof(NATIVE_MODE_CONTROLLER_INFORMATION))
846 */
847 //
848 // Beautification macros
849 //
850
851 #ifndef USER_MODE
852
853 #define GetStatus(chan, Status) \
854 Status = AtapiReadPort1(chan, IDX_IO2_AltStatus);
855
856 #define GetBaseStatus(chan, pStatus) \
857 pStatus = AtapiReadPort1(chan, IDX_IO1_i_Status);
858
859 #define WriteCommand(chan, _Command) \
860 AtapiWritePort1(chan, IDX_IO1_o_Command, _Command);
861
862
863 #define SelectDrive(chan, unit) { \
864 if(chan && chan->lun[unit] && chan->lun[unit]->DeviceFlags & DFLAGS_ATAPI_CHANGER) KdPrint3((" Select %d\n", unit)); \
865 AtapiWritePort1(chan, IDX_IO1_o_DriveSelect, (unit) ? IDE_DRIVE_SELECT_2 : IDE_DRIVE_SELECT_1); \
866 }
867
868
869 #define ReadBuffer(chan, Buffer, Count, timing) \
870 AtapiReadBuffer2(chan, IDX_IO1_i_Data, \
871 Buffer, \
872 Count, \
873 timing);
874
875 #define WriteBuffer(chan, Buffer, Count, timing) \
876 AtapiWriteBuffer2(chan, IDX_IO1_o_Data, \
877 Buffer, \
878 Count, \
879 timing);
880
881 #define ReadBuffer2(chan, Buffer, Count, timing) \
882 AtapiReadBuffer4(chan, IDX_IO1_i_Data, \
883 Buffer, \
884 Count, \
885 timing);
886
887 #define WriteBuffer2(chan, Buffer, Count, timing) \
888 AtapiWriteBuffer4(chan, IDX_IO1_o_Data, \
889 Buffer, \
890 Count, \
891 timing);
892
893 UCHAR
894 DDKFASTAPI
895 WaitOnBusy(
896 IN struct _HW_CHANNEL* chan/*,
897 PIDE_REGISTERS_2 BaseIoAddress*/
898 );
899
900 UCHAR
901 DDKFASTAPI
902 WaitOnBusyLong(
903 IN struct _HW_CHANNEL* chan/*,
904 PIDE_REGISTERS_2 BaseIoAddress*/
905 );
906
907 UCHAR
908 DDKFASTAPI
909 WaitOnBaseBusy(
910 IN struct _HW_CHANNEL* chan/*,
911 PIDE_REGISTERS_1 BaseIoAddress*/
912 );
913
914 UCHAR
915 DDKFASTAPI
916 WaitOnBaseBusyLong(
917 IN struct _HW_CHANNEL* chan/*,
918 PIDE_REGISTERS_1 BaseIoAddress*/
919 );
920
921 UCHAR
922 DDKFASTAPI
923 WaitForDrq(
924 IN struct _HW_CHANNEL* chan/*,
925 PIDE_REGISTERS_2 BaseIoAddress*/
926 );
927
928 UCHAR
929 DDKFASTAPI
930 WaitShortForDrq(
931 IN struct _HW_CHANNEL* chan/*,
932 PIDE_REGISTERS_2 BaseIoAddress*/
933 );
934
935 VOID
936 DDKFASTAPI
937 AtapiSoftReset(
938 IN struct _HW_CHANNEL* chan,/*
939 PIDE_REGISTERS_1 BaseIoAddress*/
940 ULONG DeviceNumber
941 );
942
943 #endif //USER_MODE
944
945 #define IS_RDP(OperationCode)\
946 ((OperationCode == SCSIOP_ERASE)||\
947 (OperationCode == SCSIOP_LOAD_UNLOAD)||\
948 (OperationCode == SCSIOP_LOCATE)||\
949 (OperationCode == SCSIOP_REWIND) ||\
950 (OperationCode == SCSIOP_SPACE)||\
951 (OperationCode == SCSIOP_SEEK)||\
952 /* (OperationCode == SCSIOP_FORMAT_UNIT)||\
953 (OperationCode == SCSIOP_BLANK)||*/ \
954 (OperationCode == SCSIOP_WRITE_FILEMARKS))
955
956 #ifndef USER_MODE
957
958 PSCSI_REQUEST_BLOCK
959 BuildMechanismStatusSrb (
960 IN PVOID HwDeviceExtension,
961 IN PSCSI_REQUEST_BLOCK Srb
962 );
963
964 PSCSI_REQUEST_BLOCK
965 BuildRequestSenseSrb (
966 IN PVOID HwDeviceExtension,
967 IN PSCSI_REQUEST_BLOCK Srb
968 );
969
970 VOID
971 AtapiHwInitializeChanger (
972 IN PVOID HwDeviceExtension,
973 IN ULONG TargetId,
974 IN PMECHANICAL_STATUS_INFORMATION_HEADER MechanismStatus
975 );
976
977 ULONG
978 AtapiSendCommand(
979 IN PVOID HwDeviceExtension,
980 IN PSCSI_REQUEST_BLOCK Srb,
981 IN ULONG CmdAction
982 );
983
984 ULONG
985 IdeSendCommand(
986 IN PVOID HwDeviceExtension,
987 IN PSCSI_REQUEST_BLOCK Srb,
988 IN ULONG CmdAction
989 );
990
991 #define AtapiCopyMemory RtlCopyMemory
992
993 VOID
994 AtapiHexToString (
995 ULONG Value,
996 PCHAR *Buffer
997 );
998
999 #define AtapiStringCmp(s1, s2, n) _strnicmp(s1, s2, n)
1000
1001 BOOLEAN
1002 AtapiInterrupt(
1003 IN PVOID HwDeviceExtension
1004 );
1005
1006 BOOLEAN
1007 AtapiInterrupt__(
1008 IN PVOID HwDeviceExtension,
1009 IN UCHAR c
1010 );
1011
1012 BOOLEAN
1013 AtapiHwInitialize(
1014 IN PVOID HwDeviceExtension
1015 );
1016
1017 ULONG
1018 IdeBuildSenseBuffer(
1019 IN PVOID HwDeviceExtension,
1020 IN PSCSI_REQUEST_BLOCK Srb
1021 );
1022
1023 VOID
1024 IdeMediaStatus(
1025 IN BOOLEAN EnableMSN,
1026 IN PVOID HwDeviceExtension,
1027 IN UCHAR Channel
1028 );
1029
1030 ULONG DDKAPI
1031 AtapiFindController(
1032 IN PVOID HwDeviceExtension,
1033 IN PVOID Context,
1034 IN PVOID BusInformation,
1035 IN PCHAR ArgumentString,
1036 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1037 OUT PBOOLEAN Again
1038 );
1039
1040 ULONG
1041 AtapiParseArgumentString(
1042 IN PCHAR String,
1043 IN PCHAR KeyWord
1044 );
1045
1046 BOOLEAN
1047 IssueIdentify(
1048 IN PVOID HwDeviceExtension,
1049 IN ULONG DeviceNumber,
1050 IN ULONG Channel,
1051 IN UCHAR Command,
1052 IN BOOLEAN NoSetup
1053 );
1054
1055 BOOLEAN
1056 SetDriveParameters(
1057 IN PVOID HwDeviceExtension,
1058 IN ULONG DeviceNumber,
1059 IN ULONG Channel
1060 );
1061
1062 ULONG
1063 CheckDevice(
1064 IN PVOID HwDeviceExtension,
1065 IN ULONG Channel,
1066 IN ULONG deviceNumber,
1067 IN BOOLEAN ResetBus
1068 );
1069
1070 #define UNIATA_FIND_DEV_UNHIDE 0x01
1071
1072 BOOLEAN
1073 FindDevices(
1074 IN PVOID HwDeviceExtension,
1075 IN ULONG Flags,
1076 IN ULONG Channel
1077 );
1078
1079 #endif //USER_MODE
1080
1081 #ifdef __cplusplus
1082 };
1083 #endif //__cplusplus
1084
1085 #ifndef USER_MODE
1086
1087 BOOLEAN
1088 AtapiResetController(
1089 IN PVOID HwDeviceExtension,
1090 IN ULONG PathId
1091 );
1092
1093 BOOLEAN
1094 AtapiStartIo(
1095 IN PVOID HwDeviceExtension,
1096 IN PSCSI_REQUEST_BLOCK Srb
1097 );
1098
1099 BOOLEAN
1100 AtapiStartIo__(
1101 IN PVOID HwDeviceExtension,
1102 IN PSCSI_REQUEST_BLOCK Srb,
1103 IN BOOLEAN TopLevel
1104 );
1105
1106 extern UCHAR
1107 AtaCommand48(
1108 // IN PVOID HwDeviceExtension,
1109 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1110 IN ULONG DeviceNumber,
1111 IN ULONG Channel,
1112 IN UCHAR command,
1113 IN ULONGLONG lba,
1114 IN USHORT count,
1115 IN USHORT feature,
1116 IN ULONG flags
1117 );
1118
1119 extern UCHAR
1120 AtaCommand(
1121 // IN PVOID HwDeviceExtension,
1122 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1123 IN ULONG DeviceNumber,
1124 IN ULONG Channel,
1125 IN UCHAR command,
1126 IN USHORT cylinder,
1127 IN UCHAR head,
1128 IN UCHAR sector,
1129 IN UCHAR count,
1130 IN UCHAR feature,
1131 IN ULONG flags
1132 );
1133
1134 extern LONG
1135 AtaPioMode(PIDENTIFY_DATA2 ident);
1136
1137 extern LONG
1138 AtaWmode(PIDENTIFY_DATA2 ident);
1139
1140 extern LONG
1141 AtaUmode(PIDENTIFY_DATA2 ident);
1142
1143 extern VOID
1144 AtapiDpcDispatch(
1145 IN PKDPC Dpc,
1146 IN PVOID DeferredContext,
1147 IN PVOID SystemArgument1,
1148 IN PVOID SystemArgument2
1149 );
1150
1151
1152 //#define AtaCommand(de, devn, chan, cmd, cyl, hd, sec, cnt, feat, flg)
1153
1154 extern LONG
1155 AtaPio2Mode(LONG pio);
1156
1157 extern LONG
1158 AtaPioMode(PIDENTIFY_DATA2 ident);
1159
1160 extern VOID
1161 AtapiEnableInterrupts(
1162 IN PVOID HwDeviceExtension,
1163 IN ULONG c
1164 );
1165
1166 extern VOID
1167 AtapiDisableInterrupts(
1168 IN PVOID HwDeviceExtension,
1169 IN ULONG c
1170 );
1171
1172 #define CHAN_NOT_SPECIFIED (0xffffffffL)
1173 #define CHAN_NOT_SPECIFIED_CHECK_CABLE (0xfffffffeL)
1174 #define DEVNUM_NOT_SPECIFIED (0xffffffffL)
1175 #define IOMODE_NOT_SPECIFIED (0xffffffffL)
1176
1177 extern ULONG
1178 AtapiRegCheckDevValue(
1179 IN PVOID HwDeviceExtension,
1180 IN ULONG chan,
1181 IN ULONG dev,
1182 IN PWSTR Name,
1183 IN ULONG Default
1184 );
1185
1186 extern ULONG
1187 AtapiRegCheckParameterValue(
1188 IN PVOID HwDeviceExtension,
1189 IN PWSTR PathSuffix,
1190 IN PWSTR Name,
1191 IN ULONG Default
1192 );
1193
1194 extern ULONG g_LogToDisplay;
1195
1196 extern "C"
1197 VOID
1198 _cdecl
1199 _PrintNtConsole(
1200 PCHAR DebugMessage,
1201 ...
1202 );
1203
1204 VOID
1205 UniataInitMapBM(
1206 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1207 IN struct _IDE_BUSMASTER_REGISTERS* BaseIoAddressBM_0,
1208 IN BOOLEAN MemIo
1209 );
1210
1211 VOID
1212 UniataInitMapBase(
1213 IN struct _HW_CHANNEL* chan,
1214 IN PIDE_REGISTERS_1 BaseIoAddress1,
1215 IN PIDE_REGISTERS_2 BaseIoAddress2
1216 );
1217
1218 VOID
1219 UniataInitSyncBaseIO(
1220 IN struct _HW_CHANNEL* chan
1221 );
1222
1223 UCHAR
1224 DDKFASTAPI
1225 UniataIsIdle(
1226 IN struct _HW_DEVICE_EXTENSION* deviceExtension,
1227 IN UCHAR Status
1228 );
1229
1230 VOID
1231 UniataDumpATARegs(
1232 IN struct _HW_CHANNEL* chan
1233 );
1234
1235 ULONG
1236 EncodeVendorStr(
1237 OUT PWCHAR Buffer,
1238 IN PUCHAR Str,
1239 IN ULONG Length
1240 );
1241
1242 ULONGLONG
1243 UniAtaCalculateLBARegsBack(
1244 struct _HW_LU_EXTENSION* LunExt,
1245 ULONGLONG lba
1246 );
1247
1248 BOOLEAN
1249 UniataAnybodyHome(
1250 IN PVOID HwDeviceExtension,
1251 IN ULONG Channel,
1252 IN ULONG deviceNumber
1253 );
1254
1255 #define ATA_CMD_FLAG_LBAIOsupp 0x01
1256 #define ATA_CMD_FLAG_48supp 0x02
1257 #define ATA_CMD_FLAG_48 0x04
1258 #define ATA_CMD_FLAG_DMA 0x08
1259
1260 extern UCHAR AtaCommands48[256];
1261 extern UCHAR AtaCommandFlags[256];
1262
1263 #ifdef _DEBUG
1264 #define PrintNtConsole _PrintNtConsole
1265 #else //_DEBUG
1266 #define PrintNtConsole(x) {;}
1267 #endif //_DEBUG
1268
1269 #endif //USER_MODE
1270
1271 #pragma pack(pop)
1272
1273 #endif // __GLOBAL_H__
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