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[reactos.git] / drivers / storage / ide / uniata / bsmaster.h
1 /*++
2
3 Copyright (c) 2002-2008 Alexandr A. Telyatnikov (Alter)
4
5 Module Name:
6 bsmaster.h
7
8 Abstract:
9 This file contains DMA/UltraDMA and IDE BusMastering related definitions,
10 internal structures and useful macros
11
12 Author:
13 Alexander A. Telyatnikov (Alter)
14
15 Environment:
16 kernel mode only
17
18 Notes:
19
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30
31 Revision History:
32
33 Code was created by
34 Alter, Copyright (c) 2002-2008
35
36 Some definitions were taken from FreeBSD 4.3-4.6 ATA driver by
37 Søren Schmidt, Copyright (c) 1998,1999,2000,2001
38
39 --*/
40
41 #ifndef __IDE_BUSMASTER_H__
42 #define __IDE_BUSMASTER_H__
43
44 #include "config.h"
45
46 #include "tools.h"
47
48 //
49 //
50 //
51 #define ATA_IDLE 0x0
52 #define ATA_IMMEDIATE 0x1
53 #define ATA_WAIT_INTR 0x2
54 #define ATA_WAIT_READY 0x3
55 #define ATA_ACTIVE 0x4
56 #define ATA_ACTIVE_ATA 0x5
57 #define ATA_ACTIVE_ATAPI 0x6
58 #define ATA_REINITING 0x7
59 #define ATA_WAIT_BASE_READY 0x8
60 #define ATA_WAIT_IDLE 0x9
61
62
63 #include "bm_devs.h"
64
65 #include "uata_ctl.h"
66
67 #define MAX_RETRIES 6
68 #define RETRY_UDMA2 1
69 #define RETRY_WDMA 2
70 #define RETRY_PIO 3
71
72
73 #define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */
74 #define IO_WD2 0x170 /* Secondary Fixed Disk Controller */
75 #define IP_PC98_BANK 0x432
76
77 #define PCI_ADDRESS_IOMASK 0xfffffff0
78
79 #define ATA_BM_OFFSET1 0x08
80 #define ATA_IOSIZE 0x08
81 #define ATA_ALTOFFSET 0x206 /* alternate registers offset */
82 #define ATA_PCCARD_ALTOFFSET 0x0e /* do for PCCARD devices */
83 #define ATA_ALTIOSIZE 0x01 /* alternate registers size */
84 #define ATA_BMIOSIZE 0x20
85 #define ATA_PC98_BANKIOSIZE 0x01
86 #define ATA_MAX_LBA28 DEF_U64(0x0fffffff)
87
88 #define ATA_DMA_ENTRIES 256 /* PAGESIZE/2/sizeof(BM_DMA_ENTRY)*/
89 #define ATA_DMA_EOT 0x80000000
90
91 #define DEV_BSIZE 512
92
93 #define ATAPI_MAGIC_LSB 0x14
94 #define ATAPI_MAGIC_MSB 0xeb
95
96 #define AHCI_MAX_PORT 32
97
98 typedef struct _BUSMASTER_CTX {
99 PBUSMASTER_CONTROLLER_INFORMATION* BMListPtr;
100 ULONG* BMListLen;
101 } BUSMASTER_CTX, *PBUSMASTER_CTX;
102
103 #define PCI_DEV_CLASS_STORAGE 0x01
104
105 #define PCI_DEV_SUBCLASS_IDE 0x01
106 #define PCI_DEV_SUBCLASS_RAID 0x04
107 #define PCI_DEV_SUBCLASS_ATA 0x05
108 #define PCI_DEV_SUBCLASS_SATA 0x06
109
110 /* structure for holding DMA address data */
111 typedef struct BM_DMA_ENTRY {
112 ULONG base;
113 ULONG count;
114 } BM_DMA_ENTRY, *PBM_DMA_ENTRY;
115
116 typedef struct _IDE_BUSMASTER_REGISTERS {
117 UCHAR Command;
118 UCHAR DeviceSpecific0;
119 UCHAR Status;
120 UCHAR DeviceSpecific1;
121 ULONG PRD_Table;
122 } IDE_BUSMASTER_REGISTERS, *PIDE_BUSMASTER_REGISTERS;
123
124 #define BM_STATUS_ACTIVE 0x01
125 #define BM_STATUS_ERR 0x02
126 #define BM_STATUS_INTR 0x04
127 #define BM_STATUS_MASK 0x07
128 #define BM_STATUS_DRIVE_0_DMA 0x20
129 #define BM_STATUS_DRIVE_1_DMA 0x40
130 #define BM_STATUS_SIMPLEX_ONLY 0x80
131
132 #define BM_COMMAND_START_STOP 0x01
133 /*#define BM_COMMAND_WRITE 0x08
134 #define BM_COMMAND_READ 0x00*/
135 #define BM_COMMAND_WRITE 0x00
136 #define BM_COMMAND_READ 0x08
137
138 #define BM_DS0_SII_DMA_ENABLE (1 << 0) /* DMA run switch */
139 #define BM_DS0_SII_IRQ (1 << 3) /* ??? */
140 #define BM_DS0_SII_DMA_SATA_IRQ (1 << 4) /* OR of all SATA IRQs */
141 #define BM_DS0_SII_DMA_ERROR (1 << 17) /* PCI bus error */
142 #define BM_DS0_SII_DMA_COMPLETE (1 << 18) /* cmd complete / IRQ pending */
143
144
145 #define IDX_BM_IO (IDX_IO2_o+IDX_IO2_o_SZ)
146 //#define IDX_BM_IO_SZ sizeof(IDE_BUSMASTER_REGISTERS)
147 #define IDX_BM_IO_SZ 5
148
149 #define IDX_BM_Command (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Command )+IDX_BM_IO)
150 #define IDX_BM_DeviceSpecific0 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific0)+IDX_BM_IO)
151 #define IDX_BM_Status (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, Status )+IDX_BM_IO)
152 #define IDX_BM_DeviceSpecific1 (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, DeviceSpecific1)+IDX_BM_IO)
153 #define IDX_BM_PRD_Table (FIELD_OFFSET(IDE_BUSMASTER_REGISTERS, PRD_Table )+IDX_BM_IO)
154
155 typedef struct _IDE_AHCI_REGISTERS {
156 // HBA Capabilities
157 struct {
158 ULONG NOP:5; // number of ports
159 ULONG Reserved5_7:1;
160 ULONG NCS:5; // number of command slots
161 ULONG PSC:1; // partial state capable
162 ULONG SSC:1; // slumber state capable
163 ULONG PMD:1; // PIO multiple DRQ block
164 ULONG Reserved16:1;
165
166 ULONG SPM:1; // port multiplier
167 ULONG SAM:1; // AHCI mode only
168 ULONG SNZO:1; // non-zero DMA offset
169 ULONG ISS:4; // interface speed
170 ULONG SCLO:1; // command list override
171 ULONG SAL:1; // activity LED
172 ULONG SALP:1; // aggressive link power management
173 ULONG SSS:1; // staggered spin-up
174 ULONG SIS:1; // interlock switch
175 ULONG Reserved29:1;
176 ULONG SNCQ:1; // native command queue
177 ULONG S64A:1; // 64bit addr
178 } CAP;
179
180 #define AHCI_CAP_NOP_MASK 0x0000001f
181 #define AHCI_CAP_S64A 0x80000000
182
183 // Global HBA Control
184 struct {
185 ULONG HR:1; // HBA Reset
186 ULONG IE:1; // interrupt enable
187 ULONG Reserved2_30:1;
188 ULONG AE:1; // AHCI enable
189 } GHC;
190
191 #define AHCI_GHC_HR 0x00000001
192 #define AHCI_GHC_IE 0x00000002
193 #define AHCI_GHC_AE 0x80000000
194
195 // Interrupt status (bit mask)
196 ULONG IS;
197 // Ports implemented (bit mask)
198 ULONG PI;
199 // AHCI Version
200 ULONG VS;
201 ULONG Reserved[3];
202
203 UCHAR Reserved2[0x80];
204
205 UCHAR VendorSpec[0x60];
206 } IDE_AHCI_REGISTERS, *PIDE_AHCI_REGISTERS;
207
208 #define IDX_AHCI_CAP (FIELD_OFFSET(IDE_AHCI_REGISTERS, CAP))
209 #define IDX_AHCI_GHC (FIELD_OFFSET(IDE_AHCI_REGISTERS, GHC))
210 #define IDX_AHCI_IS (FIELD_OFFSET(IDE_AHCI_REGISTERS, IS))
211 #define IDX_AHCI_VS (FIELD_OFFSET(IDE_AHCI_REGISTERS, VS))
212 #define IDX_AHCI_PI (FIELD_OFFSET(IDE_AHCI_REGISTERS, PI))
213
214
215 typedef union _SATA_SSTATUS_REG {
216
217 struct {
218 ULONG DET:4; // Device Detection
219
220 #define SStatus_DET_NoDev 0x00
221 #define SStatus_DET_Dev_NoPhy 0x01
222 #define SStatus_DET_Dev_Ok 0x03
223 #define SStatus_DET_Offline 0x04
224
225 ULONG SPD:4; // Current Interface Speed
226
227 #define SStatus_SPD_NoDev 0x00
228 #define SStatus_SPD_Gen1 0x01
229 #define SStatus_SPD_Gen2 0x02
230
231 ULONG IPM:4; // Interface Power Management
232
233 #define SStatus_IPM_NoDev 0x00
234 #define SStatus_IPM_Active 0x01
235 #define SStatus_IPM_Partial 0x02
236 #define SStatus_IPM_Slumber 0x06
237
238 ULONG Reserved:20;
239 };
240 ULONG Reg;
241
242 } SATA_SSTATUS_REG, *PSATA_SSTATUS_REG;
243
244
245 typedef union _SATA_SCONTROL_REG {
246
247 struct {
248 ULONG DET:4; // Device Detection Init
249
250 #define SControl_DET_DoNothing 0x00
251 #define SControl_DET_Idle 0x00
252 #define SControl_DET_Init 0x01
253 #define SControl_DET_Disable 0x04
254
255 ULONG SPD:4; // Speed Allowed
256
257 #define SControl_SPD_NoRestrict 0x00
258 #define SControl_SPD_LimGen1 0x01
259 #define SControl_SPD_LimGen2 0x02
260
261 ULONG IPM:4; // Interface Power Management Transitions Allowed
262
263 #define SControl_IPM_NoRestrict 0x00
264 #define SControl_IPM_NoPartial 0x01
265 #define SControl_IPM_NoSlumber 0x02
266 #define SControl_IPM_NoPartialSlumber 0x03
267
268 ULONG SPM:4; // Select Power Management, unused by AHCI
269 ULONG PMP:4; // Port Multiplier Port, unused by AHCI
270 ULONG Reserved:12;
271 };
272 ULONG Reg;
273
274 } SATA_SCONTROL_REG, *PSATA_SCONTROL_REG;
275
276
277 typedef union _SATA_SERROR_REG {
278
279 struct {
280 struct {
281 UCHAR I:1; // Recovered Data Integrity Error
282 UCHAR M:1; // Recovered Communications Error
283 UCHAR Reserved_2_7:6;
284
285 UCHAR T:1; // Transient Data Integrity Error
286 UCHAR C:1; // Persistent Communication or Data Integrity Error
287 UCHAR P:1; // Protocol Error
288 UCHAR E:1; // Internal Error
289 UCHAR Reserved_12_15:4;
290 } ERR;
291
292 struct {
293 UCHAR N:1; // PhyRdy Change, PIS.PRCS
294 UCHAR I:1; // Phy Internal Error
295 UCHAR W:1; // Comm Wake
296 UCHAR B:1; // 10B to 8B Decode Error
297 UCHAR D:1; // Disparity Error, not used by AHCI
298 UCHAR C:1; // CRC Error
299 UCHAR H:1; // Handshake Error
300 UCHAR S:1; // Link Sequence Error
301
302 UCHAR T:1; // Transport state transition error
303 UCHAR F:1; // Unknown FIS Type
304 UCHAR X:1; // Exchanged
305 UCHAR Reserved_27_31:5;
306 } DIAG;
307 };
308 ULONG Reg;
309
310 } SATA_SERROR_REG, *PSATA_SERROR_REG;
311
312
313 typedef struct _IDE_SATA_REGISTERS {
314 union {
315 SATA_SSTATUS_REG SStatus;
316 ULONG SStatus_Reg;
317 };
318 union {
319 SATA_SERROR_REG SError;
320 ULONG SError_Reg;
321 };
322 union {
323 SATA_SCONTROL_REG SControl;
324 ULONG SControl_Reg;
325 };
326
327 // SATA 1.2
328
329 ULONG SActive;
330 union {
331 ULONG Reg;
332 struct {
333 USHORT PMN; // PM Notify, bitmask
334 USHORT Reserved;
335 };
336 } SNTF;
337 ULONG SReserved[11];
338 } IDE_SATA_REGISTERS, *PIDE_SATA_REGISTERS;
339
340 #define IDX_SATA_IO (IDX_BM_IO+IDX_BM_IO_SZ)
341 //#define IDX_SATA_IO_SZ sizeof(IDE_SATA_REGISTERS)
342 #define IDX_SATA_IO_SZ 5
343
344 #define IDX_SATA_SStatus (0+IDX_SATA_IO)
345 #define IDX_SATA_SError (1+IDX_SATA_IO)
346 #define IDX_SATA_SControl (2+IDX_SATA_IO)
347 #define IDX_SATA_SActive (3+IDX_SATA_IO)
348 #define IDX_SATA_SNTF_PMN (4+IDX_SATA_IO)
349
350 #define IDX_MAX_REG (IDX_SATA_IO+IDX_SATA_IO_SZ)
351
352 typedef union _AHCI_IS_REG {
353 struct {
354 ULONG DHRS:1;// Device to Host Register FIS Interrupt
355 ULONG PSS:1; // PIO Setup FIS Interrupt
356 ULONG DSS:1; // DMA Setup FIS Interrupt
357 ULONG SDBS:1;// Set Device Bits Interrupt
358 ULONG UFS:1; // Unknown FIS Interrupt
359 ULONG DPS:1; // Descriptor Processed
360 ULONG PCS:1; // Port Connect Change Status
361 ULONG DMPS:1;// Device Mechanical Presence Status
362
363 ULONG Reserved_8_21:14;
364 ULONG PRCS:1;// PhyRdy Change Status
365 ULONG IPMS:1;// Incorrect Port Multiplier Status
366
367 ULONG OFS:1; // Overflow Status
368 ULONG Reserved_25:1;
369 ULONG INFS:1;// Interface Non-fatal Error Status
370 ULONG IFS:1; // Interface Fatal Error Status
371 ULONG HBDS:1;// Host Bus Data Error Status
372 ULONG HBFS:1;// Host Bus Fatal Error Status
373 ULONG TFES:1;// Task File Error Status
374 ULONG CPDS:1;// Cold Port Detect Status
375 };
376 ULONG Reg;
377 } AHCI_IS_REG, *PAHCI_IS_REG;
378
379
380 typedef struct _IDE_AHCI_PORT_REGISTERS {
381 union {
382 struct {
383 ULONG CLB; // command list base address
384 ULONG CLBU; // command list base address (upper 32bits)
385 };
386 ULONGLONG CLB64;
387 };
388
389 union {
390 struct {
391 ULONG FB; // FIS base address
392 ULONG FBU; // FIS base address (upper 32bits)
393 };
394 ULONGLONG FB64;
395 };
396
397 union {
398 ULONG IS_Reg; // interrupt status
399 AHCI_IS_REG IS;
400 };
401
402 union {
403 ULONG Reg; // interrupt enable
404 struct {
405 ULONG DHRE:1;// Device to Host Register FIS Interrupt Enable
406 ULONG PSE:1; // PIO Setup FIS Interrupt Enable
407 ULONG DSE:1; // DMA Setup FIS Interrupt Enable
408 ULONG SDBE:1;// Set Device Bits FIS Interrupt Enable
409 ULONG UFE:1; // Unknown FIS Interrupt Enable
410 ULONG DPE:1; // Descriptor Processed Interrupt Enable
411 ULONG PCE:1; // Port Change Interrupt Enable
412 ULONG DPME:1;// Device Mechanical Presence Enable
413
414 ULONG Reserved_8_21:14;
415 ULONG PRCE:1;// PhyRdy Change Interrupt Enable
416 ULONG IPME:1;// Incorrect Port Multiplier Enable
417 ULONG OFE:1; // Overflow Enable
418 ULONG Reserved_25:1;
419 ULONG INFE:1;// Interface Non-fatal Error Enable
420 ULONG IFE:1; // Interface Fatal Error Enable
421 ULONG HBDE:1;// Host Bus Data Error Enable
422 ULONG HBFE:1;// Host Bus Fatal Error Enable
423 ULONG TFEE:1;// Task File Error Enable
424 ULONG CPDE:1;// Cold Port Detect Enable
425 };
426 } IE;
427
428 union {
429 ULONG Reg; // command register
430 struct {
431
432 ULONG ST:1; // Start
433 ULONG SUD:1; // Spin-Up Device
434 ULONG POD:1; // Power On Device
435 ULONG CLO:1; // Command List Override
436 ULONG FRE:1; // FIS Receive Enable
437 ULONG Reserved_5_7:3;
438
439 ULONG CCS:5; // Current Command Slot
440 ULONG MPSS:1;// Mechanical Presence Switch State
441 ULONG FR:1; // FIS Receive Running
442 ULONG CR:1; // Command List Running
443
444 ULONG CPS:1; // Cold Presence State
445 ULONG PMA:1; // Port Multiplier Attached
446 ULONG HPCP:1;// Hot Plug Capable Port
447 ULONG MPSP:1;// Mechanical Presence Switch Attached to Port
448 ULONG CPD:1; // Cold Presence Detection
449 ULONG ESP:1; // External SATA Port
450 ULONG Reserved_22_23:2;
451
452 ULONG ATAPI:1; // Device is ATAPI
453 ULONG DLAE:1;// Drive LED on ATAPI Enable
454 ULONG ALPE:1;// Aggressive Link Power Management Enable
455 ULONG ASP:1; // Aggressive Slumber / Partial
456 ULONG ICC:4; // Interface Communication Control
457
458 #define SATA_CMD_ICC_Idle 0x00
459 #define SATA_CMD_ICC_NoOp 0x00
460 #define SATA_CMD_ICC_Active 0x01
461 #define SATA_CMD_ICC_Partial 0x02
462 #define SATA_CMD_ICC_Slumber 0x06
463 };
464 } CMD;
465
466 ULONG Reserved;
467
468 union {
469 ULONG Reg; // Task File Data
470 struct {
471 struct {
472 UCHAR ERR:1;
473 UCHAR cs1:2;// command-specific
474 UCHAR DRQ:1;
475 UCHAR cs2:3;// command-specific
476 UCHAR BSY:1;
477 } STS;
478 UCHAR ERR; // Contains the latest copy of the task file error register.
479 UCHAR Reserved[2];
480 };
481 } TFD;
482
483 union {
484 ULONG Reg; // signature
485 struct {
486 UCHAR SectorCount;
487 UCHAR LbaLow;
488 UCHAR LbaMid;
489 UCHAR LbaHigh;
490 };
491 } SIG;
492 union {
493 ULONG SStatus; // SCR0
494 SATA_SSTATUS_REG SSTS;
495 };
496 union {
497 ULONG SControl; // SCR2
498 SATA_SCONTROL_REG SCTL;
499 };
500 union {
501 ULONG SError; // SCR1
502 SATA_SERROR_REG SERR;
503 };
504 union {
505 ULONG SACT; // SCR3
506 ULONG SActive; // bitmask
507 };
508 ULONG CI; // Command issue, bitmask
509
510 // AHCI 1.1
511 union {
512 ULONG Reg;
513 struct {
514 USHORT PMN; // PM Notify, bitmask
515 USHORT Reserved;
516 };
517 } SNTF;
518 ULONG FIS_Switching_Reserved[12];
519 UCHAR VendorSpec[16];
520
521 } IDE_AHCI_PORT_REGISTERS, *PIDE_AHCI_PORT_REGISTERS;
522
523 #define IDX_AHCI_P_CLB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CLB))
524 #define IDX_AHCI_P_FB (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, FB))
525 #define IDX_AHCI_P_IS (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, IS))
526 #define IDX_AHCI_P_CI (FIELD_OFFSET(IDE_AHCI_PORT_REGISTERS, CI))
527
528 typedef struct _IDE_AHCI_PRD_ENTRY {
529 union {
530 ULONG base;
531 ULONGLONG base64;
532 struct {
533 ULONG DBA;
534 union {
535 ULONG DBAU;
536 ULONG baseu;
537 };
538 };
539 };
540 ULONG Reserved1;
541
542 ULONG DBC:22;
543 ULONG Reserved2:9;
544 ULONG I:1;
545
546 } IDE_AHCI_PRD_ENTRY, *PIDE_AHCI_PRD_ENTRY;
547
548 #define ATA_AHCI_DMA_ENTRIES (PAGE_SIZE/2/sizeof(IDE_AHCI_PRD_ENTRY)) /* 128 */
549 #define ATA_AHCI_MAX_TAGS 32
550
551 typedef struct _IDE_AHCI_CMD {
552 UCHAR cfis[64];
553 UCHAR acmd[32];
554 UCHAR Reserved[32];
555 IDE_AHCI_PRD_ENTRY prd_tab[ATA_AHCI_DMA_ENTRIES];
556 } IDE_AHCI_CMD, *PIDE_AHCI_CMD;
557
558 typedef struct _IDE_AHCI_CMD_LIST {
559 USHORT cmd_flags;
560 USHORT prd_length; /* PRD entries */
561 ULONG bytecount;
562 ULONGLONG cmd_table_phys; /* 128byte aligned */
563 ULONG Reserved[4];
564 } IDE_AHCI_CMD_LIST, *PIDE_AHCI_CMD_LIST;
565
566 typedef struct _IDE_AHCI_RCV_FIS {
567 UCHAR dsfis[28];
568 UCHAR Reserved1[4];
569 UCHAR psfis[24];
570 UCHAR Reserved2[8];
571 UCHAR rfis[24];
572 UCHAR Reserved3[4];
573 ULONG SDBFIS;
574 UCHAR ufis[64];
575 UCHAR Reserved4[96];
576 } IDE_AHCI_RCV_FIS, *PIDE_AHCI_RCV_FIS;
577
578
579 #define IsBusMaster(pciData) \
580 ( ((pciData)->Command & (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/)) == \
581 (PCI_ENABLE_BUS_MASTER/* | PCI_ENABLE_IO_SPACE*/))
582
583 #define PCI_IDE_PROGIF_NATIVE_1 0x01
584 #define PCI_IDE_PROGIF_NATIVE_2 0x04
585 #define PCI_IDE_PROGIF_NATIVE_ALL 0x05
586
587 #define IsMasterDev(pciData) \
588 ( ((pciData)->ProgIf & 0x80) && \
589 ((pciData)->ProgIf & PCI_IDE_PROGIF_NATIVE_ALL) != PCI_IDE_PROGIF_NATIVE_ALL )
590
591 //#define INT_Q_SIZE 32
592 #define MIN_REQ_TTL 4
593
594 union _ATA_REQ;
595
596 typedef union _ATA_REQ {
597 // ULONG reqId; // serial
598 struct {
599
600 union {
601
602 struct {
603 union _ATA_REQ* next_req;
604 union _ATA_REQ* prev_req;
605
606 PSCSI_REQUEST_BLOCK Srb; // Current request on controller.
607
608 PUSHORT DataBuffer; // Data buffer pointer.
609 ULONG WordsLeft; // Data words left.
610 ULONG TransferLength; // Originally requested transfer length
611 LONGLONG lba;
612 ULONG WordsTransfered;// Data words already transfered.
613 ULONG bcount;
614
615 UCHAR retry;
616 UCHAR ttl;
617 // UCHAR tag;
618 UCHAR Flags;
619 UCHAR ReqState;
620
621 PSCSI_REQUEST_BLOCK OriginalSrb; // Mechanism Status Srb Data
622
623 ULONG dma_entries;
624 union {
625 ULONG dma_base;
626 ULONGLONG ahci_base64; // for AHCI
627 };
628 };
629 UCHAR padding_128b[128];
630 };
631 struct {
632 union {
633 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
634 IDE_AHCI_CMD ahci_cmd; // for AHCI
635 };
636 };
637 };
638
639 UCHAR padding_4kb[PAGE_SIZE];
640
641 } ATA_REQ, *PATA_REQ;
642
643 #define REQ_FLAG_FORCE_DOWNRATE 0x01
644 #define REQ_FLAG_DMA_OPERATION 0x02
645 #define REQ_FLAG_REORDERABLE_CMD 0x04
646 #define REQ_FLAG_RW_MASK 0x08
647 #define REQ_FLAG_READ 0x08
648 #define REQ_FLAG_WRITE 0x00
649 #define REQ_FLAG_FORCE_DOWNRATE_LBA48 0x10
650 #define REQ_FLAG_DMA_DBUF 0x20
651 #define REQ_FLAG_DMA_DBUF_PRD 0x40
652
653 // Request states
654 #define REQ_STATE_NONE 0x00
655 #define REQ_STATE_QUEUED 0x10
656
657 #define REQ_STATE_PREPARE_TO_TRANSFER 0x20
658 #define REQ_STATE_PREPARE_TO_NEXT 0x21
659 #define REQ_STATE_READY_TO_TRANSFER 0x30
660
661 #define REQ_STATE_EXPECTING_INTR 0x40
662 #define REQ_STATE_ATAPI_EXPECTING_CMD_INTR 0x41
663 #define REQ_STATE_ATAPI_EXPECTING_DATA_INTR 0x42
664 #define REQ_STATE_ATAPI_DO_NOTHING_INTR 0x43
665
666 #define REQ_STATE_EARLY_INTR 0x48
667
668 #define REQ_STATE_PROCESSING_INTR 0x50
669
670 #define REQ_STATE_DPC_INTR_REQ 0x51
671 #define REQ_STATE_DPC_RESET_REQ 0x52
672 #define REQ_STATE_DPC_COMPLETE_REQ 0x53
673
674 #define REQ_STATE_DPC_WAIT_BUSY0 0x57
675 #define REQ_STATE_DPC_WAIT_BUSY1 0x58
676 #define REQ_STATE_DPC_WAIT_BUSY 0x59
677 #define REQ_STATE_DPC_WAIT_DRQ 0x5a
678 #define REQ_STATE_DPC_WAIT_DRQ0 0x5b
679 #define REQ_STATE_DPC_WAIT_DRQ_ERR 0x5c
680
681 #define REQ_STATE_TRANSFER_COMPLETE 0x7f
682
683 // Command actions:
684 #define CMD_ACTION_PREPARE 0x01
685 #define CMD_ACTION_EXEC 0x02
686 #define CMD_ACTION_ALL (CMD_ACTION_PREPARE | CMD_ACTION_EXEC)
687
688 // predefined Reorder costs
689 #define REORDER_COST_MAX ((DEF_I64(0x1) << 60) - 1)
690 #define REORDER_COST_TTL (REORDER_COST_MAX - 1)
691 #define REORDER_COST_INTERSECT (REORDER_COST_MAX - 2)
692 #define REORDER_COST_DENIED (REORDER_COST_MAX - 3)
693 #define REORDER_COST_RESELECT (REORDER_COST_MAX/4)
694
695 #define REORDER_COST_SWITCH_RW_CD (REORDER_COST_MAX/8)
696 #define REORDER_MCOST_SWITCH_RW_CD (0)
697 #define REORDER_MCOST_SEEK_BACK_CD (16)
698
699 #define REORDER_COST_SWITCH_RW_HDD (0)
700 #define REORDER_MCOST_SWITCH_RW_HDD (4)
701 #define REORDER_MCOST_SEEK_BACK_HDD (2)
702
703 /*typedef struct _ATA_QUEUE {
704 struct _ATA_REQ* head_req; // index
705 struct _ATA_REQ* tail_req; // index
706 ULONG req_count;
707 ULONG dma_base;
708 BM_DMA_ENTRY dma_tab[ATA_DMA_ENTRIES];
709 } ATA_QUEUE, *PATA_QUEUE;*/
710
711 struct _HW_DEVICE_EXTENSION;
712 struct _HW_LU_EXTENSION;
713
714 typedef struct _IORES {
715 ULONG Addr;
716 ULONG MemIo:1;
717 ULONG Reserved:31;
718 } IORES, *PIORES;
719
720 // Channel extension
721 typedef struct _HW_CHANNEL {
722
723 PATA_REQ cur_req;
724 ULONG cur_cdev;
725 /* PATA_REQ first_req;
726 PATA_REQ last_req;*/
727 ULONG queue_depth;
728 ULONG ChannelSelectWaitCount;
729
730 UCHAR DpcState;
731
732 BOOLEAN ExpectingInterrupt; // Indicates expecting an interrupt
733 BOOLEAN RDP; // Indicate last tape command was DSC Restrictive.
734 // Indicates whether '0x1f0' is the base address. Used
735 // in SMART Ioctl calls.
736 BOOLEAN PrimaryAddress;
737 // Placeholder for the sub-command value of the last
738 // SMART command.
739 UCHAR SmartCommand;
740 // Reorder anabled
741 BOOLEAN UseReorder;
742 // Placeholder for status register after a GET_MEDIA_STATUS command
743 UCHAR ReturningMediaStatus;
744
745 BOOLEAN CopyDmaBuffer;
746 //BOOLEAN MemIo;
747 BOOLEAN AltRegMap;
748
749 //UCHAR Reserved[3];
750
751 MECHANICAL_STATUS_INFORMATION_HEADER MechStatusData;
752 SENSE_DATA MechStatusSense;
753 ULONG MechStatusRetryCount;
754 SCSI_REQUEST_BLOCK InternalSrb;
755
756 ULONG MaxTransferMode; // may differ from Controller's value due to 40-pin cable
757
758 ULONG ChannelCtrlFlags;
759 ULONG ResetInProgress; // flag
760 LONG DisableIntr;
761 LONG CheckIntr;
762
763 ULONG lChannel;
764
765 #define CHECK_INTR_ACTIVE 0x03
766 #define CHECK_INTR_DETECTED 0x02
767 #define CHECK_INTR_CHECK 0x01
768 #define CHECK_INTR_IDLE 0x00
769
770 ULONG NextDpcChan;
771 PHW_TIMER HwScsiTimer;
772 LONGLONG DpcTime;
773 #if 0
774 PHW_TIMER HwScsiTimer1;
775 PHW_TIMER HwScsiTimer2;
776 LONGLONG DpcTime1;
777 // PHW_TIMER CurDpc;
778 // LARGE_INTEGER ActivationTime;
779
780 // KDPC Dpc;
781 // KTIMER Timer;
782 // PHW_TIMER HwScsiTimer;
783 // KSPIN_LOCK QueueSpinLock;
784 // KIRQL QueueOldIrql;
785 #endif
786 struct _HW_DEVICE_EXTENSION* DeviceExtension;
787 struct _HW_LU_EXTENSION* lun[2];
788
789 // Double-buffering support
790 PVOID DB_PRD;
791 ULONG DB_PRD_PhAddr;
792 PVOID DB_IO;
793 ULONG DB_IO_PhAddr;
794
795 PUCHAR DmaBuffer;
796
797 //
798 PIDE_AHCI_CMD_LIST AHCI_CL;
799 ULONGLONG AHCI_CL_PhAddr;
800 PVOID AHCI_FIS; // is not actually used by UniATA now, but is required by AHCI controller
801 ULONGLONG AHCI_FIS_PhAddr;
802 // Note: in contrast to FBSD, we keep PRD and CMD item in AtaReq structure
803
804 #ifdef QUEUE_STATISTICS
805 LONGLONG QueueStat[MAX_QUEUE_STAT];
806 LONGLONG ReorderCount;
807 LONGLONG IntersectCount;
808 LONGLONG TryReorderCount;
809 LONGLONG TryReorderHeadCount;
810 LONGLONG TryReorderTailCount; /* in-order requests */
811 #endif //QUEUE_STATISTICS
812
813 //ULONG BaseMemAddress;
814 //ULONG BaseMemAddressOffset;
815 IORES RegTranslation[IDX_MAX_REG];
816
817 } HW_CHANNEL, *PHW_CHANNEL;
818
819 #define CTRFLAGS_DMA_ACTIVE 0x0001
820 #define CTRFLAGS_DMA_RO 0x0002
821 #define CTRFLAGS_DMA_OPERATION 0x0004
822 #define CTRFLAGS_INTR_DISABLED 0x0008
823 #define CTRFLAGS_DPC_REQ 0x0010
824 #define CTRFLAGS_ENABLE_INTR_REQ 0x0020
825 #define CTRFLAGS_LBA48 0x0040
826 #define CTRFLAGS_DSC_BSY 0x0080
827 #define CTRFLAGS_NO_SLAVE 0x0100
828
829 #define GEOM_AUTO 0xffffffff
830 #define GEOM_STD 0x0000
831 #define GEOM_UNIATA 0x0001
832 #define GEOM_ORIG 0x0002
833 #define GEOM_MANUAL 0x0003
834
835 #define DPC_STATE_NONE 0x00
836 #define DPC_STATE_ISR 0x10
837 #define DPC_STATE_DPC 0x20
838 #define DPC_STATE_TIMER 0x30
839 #define DPC_STATE_COMPLETE 0x40
840
841 // Logical unit extension
842 typedef struct _HW_LU_EXTENSION {
843 IDENTIFY_DATA2 IdentifyData;
844 ULONGLONG NumOfSectors;
845 ULONG DeviceFlags; // Flags word for each possible device. DFLAGS_XXX
846 ULONG DiscsPresent; // Indicates number of platters on changer-ish devices.
847 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
848 UCHAR ReturningMediaStatus;
849
850 UCHAR TransferMode; // current transfer mode
851 UCHAR LimitedTransferMode; // user-defined or IDE cable limitation
852 UCHAR OrigTransferMode; // transfer mode, returned by device IDENTIFY (can be changed via IOCTL)
853
854 UCHAR MaximumBlockXfer;
855 UCHAR Padding0[2]; // padding
856 ULONG ErrorCount; // Count of errors. Used to turn off features.
857 // ATA_QUEUE cmd_queue;
858 LONGLONG ReadCmdCost;
859 LONGLONG WriteCmdCost;
860 LONGLONG OtherCmdCost;
861 LONGLONG RwSwitchCost;
862 LONGLONG RwSwitchMCost;
863 LONGLONG SeekBackMCost;
864 //
865 PATA_REQ first_req;
866 PATA_REQ last_req;
867 ULONG queue_depth;
868 ULONG last_write;
869
870 ULONG LunSelectWaitCount;
871
872 // tuning options
873 ULONG opt_GeomType;
874 ULONG opt_MaxTransferMode;
875 ULONG opt_PreferedTransferMode;
876 BOOLEAN opt_ReadCacheEnable;
877 BOOLEAN opt_WriteCacheEnable;
878 UCHAR opt_ReadOnly;
879 // padding
880 BOOLEAN opt_reserved[1];
881
882 struct _SBadBlockListItem* bbListDescr;
883 struct _SBadBlockRange* arrBadBlocks;
884 ULONG nBadBlocks;
885
886 struct _HW_DEVICE_EXTENSION* DeviceExtension;
887
888 #ifdef IO_STATISTICS
889
890 LONGLONG ModeErrorCount[MAX_RETRIES];
891 LONGLONG RecoverCount[MAX_RETRIES];
892 LONGLONG IoCount;
893
894 #endif//IO_STATISTICS
895 } HW_LU_EXTENSION, *PHW_LU_EXTENSION;
896
897 // Device extension
898 typedef struct _HW_DEVICE_EXTENSION {
899 CHAR Signature[32];
900 //PIDE_REGISTERS_1 BaseIoAddress1[IDE_MAX_CHAN]; // Base register locations
901 //PIDE_REGISTERS_2 BaseIoAddress2[IDE_MAX_CHAN];
902 ULONG BusInterruptLevel; // Interrupt level
903 ULONG InterruptMode; // Interrupt Mode (Level or Edge)
904 ULONG BusInterruptVector;
905 // Number of channels being supported by one instantiation
906 // of the device extension. Normally (and correctly) one, but
907 // with so many broken PCI IDE controllers being sold, we have
908 // to support them.
909 ULONG NumberChannels;
910 ULONG NumberLuns;
911 ULONG FirstChannelToCheck;
912 #if 0
913 HW_LU_EXTENSION lun[IDE_MAX_LUN];
914 HW_CHANNEL chan[AHCI_MAX_PORT/*IDE_MAX_CHAN*/];
915 #else
916 PHW_LU_EXTENSION lun;
917 PHW_CHANNEL chan;
918 #endif
919 UCHAR LastInterruptedChannel;
920 // Indicates the number of blocks transferred per int. according to the
921 // identify data.
922 BOOLEAN DriverMustPoll; // Driver is being used by the crash dump utility or ntldr.
923 BOOLEAN BusMaster;
924 BOOLEAN UseDpc; // Indicates use of DPC on long waits
925 IDENTIFY_DATA FullIdentifyData; // Identify data for device
926 // BusMaster specific data
927 // PBM_DMA_ENTRY dma_tab_0;
928 //KSPIN_LOCK DpcSpinLock;
929
930 ULONG ActiveDpcChan;
931 ULONG FirstDpcChan;
932 /*
933 PHW_TIMER HwScsiTimer1;
934 PHW_TIMER HwScsiTimer2;
935 LONGLONG DpcTime1;
936 LONGLONG DpcTime2;
937 */
938 ULONG queue_depth;
939
940 PDEVICE_OBJECT Isr2DevObj;
941
942 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0;
943 IORES BaseIoAddressBM_0;
944 //PIDE_BUSMASTER_REGISTERS BaseIoAddressBM[IDE_MAX_CHAN];
945
946 // Device identification
947 ULONG DevID;
948 ULONG RevID;
949 ULONG slotNumber;
950 ULONG SystemIoBusNumber;
951 ULONG DevIndex;
952
953 ULONG InitMethod; // vendor specific
954
955 ULONG Channel;
956
957 ULONG HbaCtrlFlags;
958 BOOLEAN simplexOnly;
959 //BOOLEAN MemIo;
960 BOOLEAN AltRegMap;
961 BOOLEAN UnknownDev;
962 BOOLEAN MasterDev;
963 BOOLEAN Host64;
964 BOOLEAN DWordIO; // Indicates use of 32-bit PIO
965 UCHAR Reserved1[2];
966
967 LONG ReCheckIntr;
968
969 ULONG MaxTransferMode; // max transfer mode supported by controller
970 ULONG HwFlags;
971 INTERFACE_TYPE OrigAdapterInterfaceType;
972 INTERFACE_TYPE AdapterInterfaceType;
973 ULONG MaximumDmaTransferLength;
974 ULONG AlignmentMask;
975
976 //ULONG BaseMemAddress;
977
978 //PIDE_SATA_REGISTERS BaseIoAddressSATA_0;
979 IORES BaseIoAddressSATA_0;
980 //PIDE_SATA_REGISTERS BaseIoAddressSATA[IDE_MAX_CHAN];
981
982 IORES BaseIoAHCI_0;
983 //PIDE_AHCI_PORT_REGISTERS BaseIoAHCIPort[AHCI_MAX_PORT];
984
985 BOOLEAN opt_AtapiDmaZeroTransfer; // default FALSE
986 BOOLEAN opt_AtapiDmaControlCmd; // default FALSE
987 BOOLEAN opt_AtapiDmaRawRead; // default TRUE
988 BOOLEAN opt_AtapiDmaReadWrite; // default TRUE
989
990 PCCH FullDevName;
991
992 } HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
993
994 typedef struct _ISR2_DEVICE_EXTENSION {
995 PHW_DEVICE_EXTENSION HwDeviceExtension;
996 ULONG DevIndex;
997 } ISR2_DEVICE_EXTENSION, *PISR2_DEVICE_EXTENSION;
998
999 #define HBAFLAGS_DMA_DISABLED 0x01
1000 #define HBAFLAGS_DMA_DISABLED_LBA48 0x02
1001
1002 extern UCHAR pciBuffer[256];
1003 extern PBUSMASTER_CONTROLLER_INFORMATION BMList;
1004 extern ULONG BMListLen;
1005 extern ULONG IsaCount;
1006 extern ULONG MCACount;
1007
1008 //extern const CHAR retry_Wdma[MAX_RETRIES+1];
1009 //extern const CHAR retry_Udma[MAX_RETRIES+1];
1010
1011 extern VOID
1012 NTAPI
1013 UniataEnumBusMasterController(
1014 IN PVOID DriverObject,
1015 PVOID Argument2
1016 );
1017
1018 extern ULONG NTAPI
1019 UniataFindCompatBusMasterController1(
1020 IN PVOID HwDeviceExtension,
1021 IN PVOID Context,
1022 IN PVOID BusInformation,
1023 IN PCHAR ArgumentString,
1024 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1025 OUT PBOOLEAN Again
1026 );
1027
1028 extern ULONG NTAPI
1029 UniataFindCompatBusMasterController2(
1030 IN PVOID HwDeviceExtension,
1031 IN PVOID Context,
1032 IN PVOID BusInformation,
1033 IN PCHAR ArgumentString,
1034 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1035 OUT PBOOLEAN Again
1036 );
1037
1038 #define UNIATA_ALLOCATE_NEW_LUNS 0x00
1039
1040 extern BOOLEAN
1041 NTAPI
1042 UniataAllocateLunExt(
1043 PHW_DEVICE_EXTENSION deviceExtension,
1044 ULONG NewNumberChannels
1045 );
1046
1047 extern ULONG NTAPI
1048 UniataFindBusMasterController(
1049 IN PVOID HwDeviceExtension,
1050 IN PVOID Context,
1051 IN PVOID BusInformation,
1052 IN PCHAR ArgumentString,
1053 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1054 OUT PBOOLEAN Again
1055 );
1056
1057 extern ULONG NTAPI
1058 UniataFindFakeBusMasterController(
1059 IN PVOID HwDeviceExtension,
1060 IN PVOID Context,
1061 IN PVOID BusInformation,
1062 IN PCHAR ArgumentString,
1063 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1064 OUT PBOOLEAN Again
1065 );
1066
1067 extern NTSTATUS
1068 NTAPI
1069 UniataConnectIntr2(
1070 IN PVOID HwDeviceExtension
1071 );
1072
1073 extern NTSTATUS
1074 NTAPI
1075 UniataDisconnectIntr2(
1076 IN PVOID HwDeviceExtension
1077 );
1078
1079 extern ULONG
1080 NTAPI
1081 ScsiPortGetBusDataByOffset(
1082 IN PVOID HwDeviceExtension,
1083 IN BUS_DATA_TYPE BusDataType,
1084 IN ULONG BusNumber,
1085 IN ULONG SlotNumber,
1086 IN PVOID Buffer,
1087 IN ULONG Offset,
1088 IN ULONG Length
1089 );
1090
1091 #define PCIBUSNUM_NOT_SPECIFIED (0xffffffffL)
1092 #define PCISLOTNUM_NOT_SPECIFIED (0xffffffffL)
1093
1094 extern ULONG
1095 NTAPI
1096 AtapiFindListedDev(
1097 PBUSMASTER_CONTROLLER_INFORMATION BusMasterAdapters,
1098 ULONG lim,
1099 IN PVOID HwDeviceExtension,
1100 IN ULONG BusNumber,
1101 IN ULONG SlotNumber,
1102 OUT PCI_SLOT_NUMBER* _slotData // optional
1103 );
1104
1105 extern ULONG
1106 NTAPI
1107 AtapiFindDev(
1108 IN PVOID HwDeviceExtension,
1109 IN BUS_DATA_TYPE BusDataType,
1110 IN ULONG BusNumber,
1111 IN ULONG SlotNumber,
1112 IN ULONG dev_id,
1113 IN ULONG RevID
1114 );
1115
1116 extern VOID
1117 NTAPI
1118 AtapiDmaAlloc(
1119 IN PVOID HwDeviceExtension,
1120 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1121 IN ULONG lChannel // logical channel,
1122 );
1123
1124 extern BOOLEAN
1125 NTAPI
1126 AtapiDmaSetup(
1127 IN PVOID HwDeviceExtension,
1128 IN ULONG DeviceNumber,
1129 IN ULONG lChannel, // logical channel,
1130 IN PSCSI_REQUEST_BLOCK Srb,
1131 IN PUCHAR data,
1132 IN ULONG count
1133 );
1134
1135 extern BOOLEAN
1136 NTAPI
1137 AtapiDmaPioSync(
1138 PVOID HwDeviceExtension,
1139 PSCSI_REQUEST_BLOCK Srb,
1140 PUCHAR data,
1141 ULONG count
1142 );
1143
1144 extern BOOLEAN
1145 NTAPI
1146 AtapiDmaDBSync(
1147 PHW_CHANNEL chan,
1148 PSCSI_REQUEST_BLOCK Srb
1149 );
1150
1151 extern VOID
1152 NTAPI
1153 AtapiDmaStart(
1154 IN PVOID HwDeviceExtension,
1155 IN ULONG DeviceNumber,
1156 IN ULONG lChannel, // logical channel,
1157 IN PSCSI_REQUEST_BLOCK Srb
1158 );
1159
1160 extern UCHAR
1161 NTAPI
1162 AtapiDmaDone(
1163 IN PVOID HwDeviceExtension,
1164 IN ULONG DeviceNumber,
1165 IN ULONG lChannel, // logical channel,
1166 IN PSCSI_REQUEST_BLOCK Srb
1167 );
1168
1169 extern VOID
1170 NTAPI
1171 AtapiDmaReinit(
1172 IN PHW_DEVICE_EXTENSION deviceExtension,
1173 IN ULONG ldev,
1174 IN PATA_REQ AtaReq
1175 );
1176
1177 extern VOID
1178 NTAPI
1179 AtapiDmaInit__(
1180 IN PHW_DEVICE_EXTENSION deviceExtension,
1181 IN ULONG ldev
1182 );
1183
1184 extern VOID
1185 NTAPI
1186 AtapiDmaInit(
1187 IN PVOID HwDeviceExtension,
1188 IN ULONG DeviceNumber,
1189 IN ULONG lChannel, // logical channel,
1190 // is always 0 except simplex-only controllers
1191 IN SCHAR apiomode,
1192 IN SCHAR wdmamode,
1193 IN SCHAR udmamode
1194 );
1195
1196 extern BOOLEAN NTAPI
1197 AtapiInterrupt2(
1198 IN PKINTERRUPT Interrupt,
1199 IN PVOID HwDeviceExtension
1200 );
1201
1202 extern PDRIVER_OBJECT SavedDriverObject;
1203
1204 extern BOOLEAN
1205 NTAPI
1206 UniataChipDetectChannels(
1207 IN PVOID HwDeviceExtension,
1208 IN PPCI_COMMON_CONFIG pciData, // optional
1209 IN ULONG DeviceNumber,
1210 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
1211 );
1212
1213 extern BOOLEAN
1214 NTAPI
1215 UniataChipDetect(
1216 IN PVOID HwDeviceExtension,
1217 IN PPCI_COMMON_CONFIG pciData, // optional
1218 IN ULONG DeviceNumber,
1219 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1220 IN BOOLEAN* simplexOnly
1221 );
1222
1223 extern BOOLEAN
1224 NTAPI
1225 AtapiChipInit(
1226 IN PVOID HwDeviceExtension,
1227 IN ULONG DeviceNumber,
1228 IN ULONG c
1229 );
1230
1231 extern ULONG
1232 NTAPI
1233 AtapiGetIoRange(
1234 IN PVOID HwDeviceExtension,
1235 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo,
1236 IN PPCI_COMMON_CONFIG pciData,
1237 IN ULONG SystemIoBusNumber,
1238 IN ULONG rid,
1239 IN ULONG offset,
1240 IN ULONG length //range id
1241 );
1242
1243 /****************** 1 *****************/
1244 #define GetPciConfig1(offs, op) { \
1245 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1246 PCIConfiguration, \
1247 SystemIoBusNumber, \
1248 slotNumber, \
1249 &op, \
1250 offs, \
1251 1); \
1252 }
1253
1254 #define SetPciConfig1(offs, op) { \
1255 UCHAR _a = op; \
1256 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1257 PCIConfiguration, \
1258 SystemIoBusNumber, \
1259 slotNumber, \
1260 &_a, \
1261 offs, \
1262 1); \
1263 }
1264
1265 #define ChangePciConfig1(offs, _op) { \
1266 UCHAR a = 0; \
1267 GetPciConfig1(offs, a); \
1268 a = (UCHAR)(_op); \
1269 SetPciConfig1(offs, a); \
1270 }
1271
1272 /****************** 2 *****************/
1273 #define GetPciConfig2(offs, op) { \
1274 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1275 PCIConfiguration, \
1276 SystemIoBusNumber, \
1277 slotNumber, \
1278 &op, \
1279 offs, \
1280 2); \
1281 }
1282
1283 #define SetPciConfig2(offs, op) { \
1284 USHORT _a = op; \
1285 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1286 PCIConfiguration, \
1287 SystemIoBusNumber, \
1288 slotNumber, \
1289 &_a, \
1290 offs, \
1291 2); \
1292 }
1293
1294 #define ChangePciConfig2(offs, _op) { \
1295 USHORT a = 0; \
1296 GetPciConfig2(offs, a); \
1297 a = (USHORT)(_op); \
1298 SetPciConfig2(offs, a); \
1299 }
1300
1301 /****************** 4 *****************/
1302 #define GetPciConfig4(offs, op) { \
1303 ScsiPortGetBusDataByOffset(HwDeviceExtension, \
1304 PCIConfiguration, \
1305 SystemIoBusNumber, \
1306 slotNumber, \
1307 &op, \
1308 offs, \
1309 4); \
1310 }
1311
1312 #define SetPciConfig4(offs, op) { \
1313 ULONG _a = op; \
1314 ScsiPortSetBusDataByOffset(HwDeviceExtension, \
1315 PCIConfiguration, \
1316 SystemIoBusNumber, \
1317 slotNumber, \
1318 &_a, \
1319 offs, \
1320 4); \
1321 }
1322
1323 #define ChangePciConfig4(offs, _op) { \
1324 ULONG a = 0; \
1325 GetPciConfig4(offs, a); \
1326 a = _op; \
1327 SetPciConfig4(offs, a); \
1328 }
1329
1330 #ifndef GetDmaStatus
1331 #define GetDmaStatus(de, c) \
1332 (((de)->BusMaster) ? AtapiReadPort1(&((de)->chan[c]), IDX_BM_Status) : 0)
1333 #endif //GetDmaStatus
1334
1335 #ifdef USE_OWN_DMA
1336 #define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1337 AtapiVirtToPhysAddr_(hwde, srb, phaddr, plen, phaddru);
1338 #else
1339 #define AtapiVirtToPhysAddr(hwde, srb, phaddr, plen, phaddru) \
1340 (ScsiPortConvertPhysicalAddressToUlong/*(ULONG)ScsiPortGetVirtualAddress*/(/*hwde,*/ \
1341 ScsiPortGetPhysicalAddress(hwde, srb, phaddr, plen)))
1342 #endif //USE_OWN_DMA
1343
1344 VOID
1345 DDKFASTAPI
1346 AtapiWritePort4(
1347 IN PHW_CHANNEL chan,
1348 IN ULONG port,
1349 IN ULONG data
1350 );
1351
1352 VOID
1353 DDKFASTAPI
1354 AtapiWritePort2(
1355 IN PHW_CHANNEL chan,
1356 IN ULONG port,
1357 IN USHORT data
1358 );
1359
1360 VOID
1361 DDKFASTAPI
1362 AtapiWritePort1(
1363 IN PHW_CHANNEL chan,
1364 IN ULONG port,
1365 IN UCHAR data
1366 );
1367
1368 VOID
1369 DDKFASTAPI
1370 AtapiWritePortEx4(
1371 IN PHW_CHANNEL chan,
1372 IN ULONG port,
1373 IN ULONG offs,
1374 IN ULONG data
1375 );
1376
1377 VOID
1378 DDKFASTAPI
1379 AtapiWritePortEx1(
1380 IN PHW_CHANNEL chan,
1381 IN ULONG port,
1382 IN ULONG offs,
1383 IN UCHAR data
1384 );
1385
1386 ULONG
1387 DDKFASTAPI
1388 AtapiReadPort4(
1389 IN PHW_CHANNEL chan,
1390 IN ULONG port
1391 );
1392
1393 USHORT
1394 DDKFASTAPI
1395 AtapiReadPort2(
1396 IN PHW_CHANNEL chan,
1397 IN ULONG port
1398 );
1399
1400 UCHAR
1401 DDKFASTAPI
1402 AtapiReadPort1(
1403 IN PHW_CHANNEL chan,
1404 IN ULONG port
1405 );
1406
1407 ULONG
1408 DDKFASTAPI
1409 AtapiReadPortEx4(
1410 IN PHW_CHANNEL chan,
1411 IN ULONG port,
1412 IN ULONG offs
1413 );
1414
1415 UCHAR
1416 DDKFASTAPI
1417 AtapiReadPortEx1(
1418 IN PHW_CHANNEL chan,
1419 IN ULONG port,
1420 IN ULONG offs
1421 );
1422
1423 VOID
1424 DDKFASTAPI
1425 AtapiWriteBuffer4(
1426 IN PHW_CHANNEL chan,
1427 IN ULONG _port,
1428 IN PVOID Buffer,
1429 IN ULONG Count,
1430 IN ULONG Timing
1431 );
1432
1433 VOID
1434 DDKFASTAPI
1435 AtapiWriteBuffer2(
1436 IN PHW_CHANNEL chan,
1437 IN ULONG _port,
1438 IN PVOID Buffer,
1439 IN ULONG Count,
1440 IN ULONG Timing
1441 );
1442
1443 VOID
1444 DDKFASTAPI
1445 AtapiReadBuffer4(
1446 IN PHW_CHANNEL chan,
1447 IN ULONG _port,
1448 IN PVOID Buffer,
1449 IN ULONG Count,
1450 IN ULONG Timing
1451 );
1452
1453 VOID
1454 DDKFASTAPI
1455 AtapiReadBuffer2(
1456 IN PHW_CHANNEL chan,
1457 IN ULONG _port,
1458 IN PVOID Buffer,
1459 IN ULONG Count,
1460 IN ULONG Timing
1461 );
1462
1463 /*#define GET_CHANNEL(Srb) (Srb->TargetId >> 1)
1464 #define GET_LDEV(Srb) (Srb->TargetId)
1465 #define GET_LDEV2(P, T, L) (T)*/
1466
1467 #define GET_CHANNEL(Srb) (Srb->PathId)
1468 #define GET_LDEV(Srb) (Srb->TargetId | (Srb->PathId << 1))
1469 #define GET_LDEV2(P, T, L) (T | ((P)<<1))
1470 #define GET_CDEV(Srb) (Srb->TargetId)
1471
1472 #define AtapiSetupLunPtrs(chan, deviceExtension, c) \
1473 { \
1474 chan->DeviceExtension = deviceExtension; \
1475 chan->lChannel = c; \
1476 chan->lun[0] = &(deviceExtension->lun[c*2+0]); \
1477 chan->lun[1] = &(deviceExtension->lun[c*2+1]); \
1478 chan->AltRegMap = deviceExtension->AltRegMap; \
1479 chan->NextDpcChan = -1; \
1480 chan->lun[0]->DeviceExtension = deviceExtension; \
1481 chan->lun[1]->DeviceExtension = deviceExtension; \
1482 }
1483
1484 BOOLEAN
1485 NTAPI
1486 AtapiReadChipConfig(
1487 IN PVOID HwDeviceExtension,
1488 IN ULONG DeviceNumber,
1489 IN ULONG channel // physical channel
1490 );
1491
1492 VOID
1493 NTAPI
1494 UniataForgetDevice(
1495 PHW_LU_EXTENSION LunExt
1496 );
1497
1498 extern ULONG SkipRaids;
1499 extern ULONG ForceSimplex;
1500
1501 extern BOOLEAN InDriverEntry;
1502
1503 extern BOOLEAN g_opt_Verbose;
1504
1505 extern BOOLEAN WinVer_WDM_Model;
1506
1507 #endif //__IDE_BUSMASTER_H__
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