3 Copyright (c) 2004-2016 Alexandr A. Telyatnikov (Alter)
9 This is the chip-specific init module for ATA/ATAPI IDE controllers
10 with Busmaster DMA and Serial ATA support
13 Alexander A. Telyatnikov (Alter)
20 THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 Some parts of code were taken from FreeBSD 5.1-6.1 ATA driver by
34 Søren Schmidt, Copyright (c) 1998-2007
35 added IT8172 IDE controller support from Linux
36 added VIA 8233/8235 fix from Linux
37 added 80-pin cable detection from Linux for
39 added support for non-standard layout of registers
50 static BUSMASTER_CONTROLLER_INFORMATION_BASE
const AtiSouthAdapters
[] = {
51 PCI_DEV_HW_SPEC_BM( 4385, 1002, 0x00, ATA_MODE_NOT_SPEC
, "ATI South", 0 ),
52 PCI_DEV_HW_SPEC_BM( ffff
, ffff
, 0xff, BMLIST_TERMINATOR
, NULL
, BMLIST_TERMINATOR
)
58 UniataChipDetectChannels(
59 IN PVOID HwDeviceExtension
,
60 IN PPCI_COMMON_CONFIG pciData
, // optional
61 IN ULONG DeviceNumber
,
62 IN PPORT_CONFIGURATION_INFORMATION ConfigInfo
65 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
66 //ULONG slotNumber = deviceExtension->slotNumber;
67 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
68 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
69 //ULONG DeviceID = (deviceExtension->DevID >> 16) & 0xffff;
70 //ULONG RevID = deviceExtension->RevID;
71 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
72 ULONG ChipFlags
= deviceExtension
->HwFlags
& CHIPFLAG_MASK
;
75 KdPrint2((PRINT_PREFIX
"UniataChipDetectChannels:\n" ));
77 deviceExtension
->AHCI_PI_mask
= 0;
79 if(ChipFlags
& (UNIATA_SATA
| UNIATA_AHCI
)) {
80 if(!deviceExtension
->NumberChannels
) {
81 KdPrint2((PRINT_PREFIX
"uninitialized SATA/AHCI port number -> 1\n"));
82 deviceExtension
->NumberChannels
= 1;
84 if(AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"IgnoreAhciPM", 1 /* DEBUG */)) {
85 KdPrint2((PRINT_PREFIX
"SATA/AHCI w/o PM, max luns 1 or 2\n"));
86 deviceExtension
->NumberLuns
= 2; // we may be in Legacy mode
87 //chan->ChannelCtrlFlags |= CTRFLAGS_NO_SLAVE;
89 KdPrint2((PRINT_PREFIX
"SATA/AHCI -> possible PM, max luns %d\n", SATA_MAX_PM_UNITS
));
90 deviceExtension
->NumberLuns
= SATA_MAX_PM_UNITS
;
91 //deviceExtension->NumberLuns = 1;
94 if(deviceExtension
->MasterDev
) {
95 KdPrint2((PRINT_PREFIX
"MasterDev -> 1 chan\n"));
96 deviceExtension
->NumberChannels
= 1;
98 for(n
=0; n
<deviceExtension
->NumberChannels
; n
++) {
99 if(AtapiRegCheckDevValue(deviceExtension
, n
, DEVNUM_NOT_SPECIFIED
, L
"Exclude", 0)) {
100 KdPrint2((PRINT_PREFIX
"Channel %d excluded\n", n
));
101 deviceExtension
->AHCI_PI_mask
&= ~((ULONG
)1 << n
);
103 deviceExtension
->AHCI_PI_mask
|= ((ULONG
)1 << n
);
106 KdPrint2((PRINT_PREFIX
"PortMask %#x\n", deviceExtension
->AHCI_PI_mask
));
107 deviceExtension
->AHCI_PI_mask
=
108 AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"PortMask", (ULONG
)0xffffffff >> (32-deviceExtension
->NumberChannels
) );
109 KdPrint2((PRINT_PREFIX
"Force PortMask %#x\n", deviceExtension
->AHCI_PI_mask
));
111 for(i
=deviceExtension
->AHCI_PI_mask
, n
=0; i
; n
++, i
=i
>>1);
112 KdPrint2((PRINT_PREFIX
"mask -> %d chans\n", n
));
115 case ATA_ACER_LABS_ID
:
116 switch(deviceExtension
->DevID
) {
119 deviceExtension
->NumberChannels
= 4;
120 KdPrint2((PRINT_PREFIX
"Acer 4 chan\n"));
125 if(ChipType
!= PRMIO
) {
128 if(!(ChipFlags
& UNIATA_SATA
)) {
129 deviceExtension
->NumberChannels
= 4;
130 KdPrint2((PRINT_PREFIX
"Promise up to 4 chan\n"));
132 if(ChipFlags
& PRCMBO
) {
133 deviceExtension
->NumberChannels
= 3;
134 KdPrint2((PRINT_PREFIX
"Promise 3 chan\n"));
136 deviceExtension
->NumberChannels
= 4;
137 KdPrint2((PRINT_PREFIX
"Promise 4 chan\n"));
141 KdPrint2((PRINT_PREFIX
"Marvell\n"));
142 /* AHCI part has own DevID-based workaround */
143 switch(deviceExtension
->DevID
) {
145 /* 88SX6101 only have 1 PATA channel */
146 if(BMList
[deviceExtension
->DevIndex
].channel
) {
147 KdPrint2((PRINT_PREFIX
"88SX6101/11 has no 2nd PATA chan\n"));
150 deviceExtension
->NumberChannels
= 1;
151 KdPrint2((PRINT_PREFIX
"88SX6101 PATA 1 chan\n"));
156 KdPrint2((PRINT_PREFIX
"ATI\n"));
157 switch(deviceExtension
->DevID
) {
159 KdPrint2((PRINT_PREFIX
" IXP600\n"));
160 /* IXP600 only have 1 PATA channel */
161 if(BMList
[deviceExtension
->DevIndex
].channel
) {
162 KdPrint2((PRINT_PREFIX
"New ATI no 2nd PATA chan\n"));
165 deviceExtension
->NumberChannels
= 1;
166 KdPrint2((PRINT_PREFIX
"New ATI PATA 1 chan\n"));
169 case ATA_ATI_IXP700
: {
171 PCI_SLOT_NUMBER slotData
;
174 KdPrint2((PRINT_PREFIX
" IXP700\n"));
176 * When "combined mode" is enabled, an additional PATA channel is
177 * emulated with two SATA ports and appears on this device.
178 * This mode can only be detected via SMB controller.
180 j
= AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION_BASE
*)&AtiSouthAdapters
[0], -1, HwDeviceExtension
, SystemIoBusNumber
, PCISLOTNUM_NOT_SPECIFIED
, &slotData
);
181 if(j
!= BMLIST_TERMINATOR
) {
182 slotNumber
= slotData
.u
.AsULONG
;
184 GetPciConfig1(0xad, satacfg
);
185 KdPrint(("SATA controller %s (%s%s channel)\n",
186 (satacfg
& 0x01) == 0 ? "disabled" : "enabled",
187 (satacfg
& 0x08) == 0 ? "" : "combined mode, ",
188 (satacfg
& 0x10) == 0 ? "primary" : "secondary"));
190 * If SATA controller is enabled but combined mode is disabled,
191 * we have only one PATA channel. Ignore a non-existent channel.
193 if ((satacfg
& 0x09) == 0x01) {
194 if(BMList
[deviceExtension
->DevIndex
].channel
) {
195 KdPrint2((PRINT_PREFIX
"New ATI no 2nd PATA chan\n"));
198 deviceExtension
->NumberChannels
= 1;
199 KdPrint2((PRINT_PREFIX
"New ATI PATA 1 chan\n"));
202 KdPrint2((PRINT_PREFIX
"New ATI 2 chan\n"));
203 deviceExtension
->NumberChannels
= 2;
205 if (BMList[deviceExtension->DevIndex].channel != ((satacfg & 0x10) >> 4)) {
216 case ATA_SILICON_IMAGE_ID
:
218 if(ChipFlags
& SIIBUG
) {
219 /* work around errata in early chips */
220 deviceExtension
->DmaSegmentLength
= 15 * DEV_BSIZE
;
221 deviceExtension
->DmaSegmentAlignmentMask
= 8192-1;
223 if(ChipType
!= SIIMIO
) {
230 if(VendorID
== ATA_SILICON_IMAGE_ID
) {
231 KdPrint2((PRINT_PREFIX
"New SII\n"));
233 KdPrint2((PRINT_PREFIX
"ATI SATA\n"));
235 if(deviceExtension
->HwFlags
& SII4CH
) {
236 deviceExtension
->NumberChannels
= 4;
237 KdPrint2((PRINT_PREFIX
"4 chan\n"));
241 if(/*(deviceExtension->DevID == 0x32491106) &&
242 ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo->AccessRanges)[5].RangeStart)*/
243 deviceExtension
->HwFlags
& VIABAR
) {
244 deviceExtension
->NumberChannels
= 3;
245 KdPrint2((PRINT_PREFIX
"VIA 3 chan\n"));
247 if(ChipFlags
& VIASATA
) {
248 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
249 // do nothing, generic PATA INIT
250 KdPrint2((PRINT_PREFIX
"VIA SATA without SATA regs -> no PM\n"));
251 deviceExtension
->NumberLuns
= 1;
255 /* ITE ATA133 controller */
256 if(deviceExtension
->DevID
== 0x82131283) {
257 if(BMList
[deviceExtension
->DevIndex
].channel
) {
258 KdPrint2((PRINT_PREFIX
"New ITE has no 2nd PATA chan\n"));
261 deviceExtension
->NumberChannels
= 1;
262 KdPrint2((PRINT_PREFIX
"New ITE PATA 1 chan\n"));
267 /* New Intel PATA controllers */
268 if(g_opt_VirtualMachine
!= VM_VBOX
&&
269 /*deviceExtension->DevID == 0x27df8086 ||
270 deviceExtension->DevID == 0x269e8086 ||
271 deviceExtension->DevID == ATA_I82801HBM*/
273 if(BMList
[deviceExtension
->DevIndex
].channel
) {
274 KdPrint2((PRINT_PREFIX
"New Intel PATA has no 2nd chan\n"));
277 deviceExtension
->NumberChannels
= 1;
278 KdPrint2((PRINT_PREFIX
"New Intel PATA 1 chan\n"));
281 #endif // this code is removed from newer FreeBSD
283 /* New JMicron PATA controllers */
284 if(deviceExtension
->DevID
== ATA_JMB361
||
285 deviceExtension
->DevID
== ATA_JMB363
||
286 deviceExtension
->DevID
== ATA_JMB368
) {
287 if(BMList
[deviceExtension
->DevIndex
].channel
) {
288 KdPrint2((PRINT_PREFIX
"New JMicron has no 2nd chan\n"));
291 deviceExtension
->NumberChannels
= 1;
292 KdPrint2((PRINT_PREFIX
"New JMicron PATA 1 chan\n"));
296 if(ChipType
== CYRIX_OLD
) {
299 slotNumber
= deviceExtension
->slotNumber
;
300 KdPrint2((PRINT_PREFIX
"Cyrix slot %#x\n", slotNumber
));
301 GetPciConfig1(0x60, tmp8
);
302 if(tmp8
& (1 << BMList
[deviceExtension
->DevIndex
].channel
)) {
303 KdPrint2((PRINT_PREFIX
"Old Cyrix chan %d ok\n", BMList
[deviceExtension
->DevIndex
].channel
));
305 KdPrint2((PRINT_PREFIX
"Old Cyrix no chan %d\n", BMList
[deviceExtension
->DevIndex
].channel
));
310 } // end switch(VendorID)
312 i
= AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"NumberChannels", n
);
316 KdPrint2((PRINT_PREFIX
"reg -> %d chans\n", n
));
318 deviceExtension
->NumberChannels
= min(i
, deviceExtension
->NumberChannels
);
319 if(!deviceExtension
->NumberChannels
) {
320 KdPrint2((PRINT_PREFIX
"all channels blocked\n", n
));
323 deviceExtension
->AHCI_PI_mask
&= (ULONG
)0xffffffff >> (32-deviceExtension
->NumberChannels
);
324 KdPrint2((PRINT_PREFIX
"Final PortMask %#x\n", deviceExtension
->AHCI_PI_mask
));
328 } // end UniataChipDetectChannels()
333 IN PVOID HwDeviceExtension
,
334 IN PPCI_COMMON_CONFIG pciData
, // optional
335 IN ULONG DeviceNumber
,
336 IN OUT PPORT_CONFIGURATION_INFORMATION ConfigInfo
,
337 IN BOOLEAN
* simplexOnly
340 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
341 ULONG slotNumber
= deviceExtension
->slotNumber
;
342 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
343 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
344 ULONG DeviceID
= (deviceExtension
->DevID
>> 16) & 0xffff;
345 ULONG RevID
= deviceExtension
->RevID
;
347 BUSMASTER_CONTROLLER_INFORMATION_BASE
* DevTypeInfo
;
354 ULONG_PTR BaseMemAddress
;
355 ULONG_PTR BaseIoAddress1
;
356 ULONG_PTR BaseIoAddress2
;
357 ULONG_PTR BaseIoAddressBM
;
359 ULONG BaseMemAddress
;
360 ULONG BaseIoAddress1
;
361 ULONG BaseIoAddress2
;
362 ULONG BaseIoAddressBM
;
364 BOOLEAN MemIo
= FALSE
;
365 BOOLEAN IsPata
= FALSE
;
367 KdPrint2((PRINT_PREFIX
"UniataChipDetect:\n" ));
368 KdPrint2((PRINT_PREFIX
"HwFlags: %#x\n", deviceExtension
->HwFlags
));
370 i
= Ata_is_dev_listed((PBUSMASTER_CONTROLLER_INFORMATION_BASE
)&BusMasterAdapters
[0], VendorID
, 0xffff, 0, NUM_BUSMASTER_ADAPTERS
);
372 c
= AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"ForceSimplex", 0);
378 BaseIoAddressBM
= pciData
->u
.type0
.BaseAddresses
[4] & ~0x07;
379 deviceExtension
->MaxTransferMode
= BaseIoAddressBM
? ATA_DMA
: ATA_PIO4
;
380 ConfigInfo
->MaximumTransferLength
= DEV_BSIZE
*256;
381 deviceExtension
->MaximumDmaTransferLength
= ConfigInfo
->MaximumTransferLength
;
382 //deviceExtension->NumberOfPhysicalBreaks = min(deviceExtension->MaximumDmaTransferLength/PAGE_SIZE+1, ATA_DMA_ENTRIES);
383 deviceExtension
->DmaSegmentLength
= 0x10000;
384 deviceExtension
->DmaSegmentAlignmentMask
= 0xffff;
386 KdPrint2((PRINT_PREFIX
"i: %#x\n", i
));
387 if(i
!= BMLIST_TERMINATOR
) {
388 DevTypeInfo
= (PBUSMASTER_CONTROLLER_INFORMATION_BASE
)&BusMasterAdapters
[i
];
391 if(Ata_is_ahci_dev(pciData
)) {
392 KdPrint2((PRINT_PREFIX
" AHCI candidate"));
394 deviceExtension
->NumberChannels
= 0;
395 if(!UniataAhciDetect(HwDeviceExtension
, pciData
, ConfigInfo
)) {
396 KdPrint2((PRINT_PREFIX
" AHCI init failed - not detected\n"));
397 return STATUS_UNSUCCESSFUL
;
399 KdPrint2((PRINT_PREFIX
" unknown AHCI dev, addr %#x ", deviceExtension
->BaseIoAHCI_0
.Addr
));
401 KdPrint2((PRINT_PREFIX
" unknown dev, BM addr %#x ", BaseIoAddressBM
));
403 KdPrint2((PRINT_PREFIX
" MaxTransferMode %#x\n", deviceExtension
->MaxTransferMode
));
405 if(!UniataChipDetectChannels(HwDeviceExtension
, pciData
, DeviceNumber
, ConfigInfo
)) {
406 return STATUS_UNSUCCESSFUL
;
408 if(!UniataAllocateLunExt(deviceExtension
, UNIATA_ALLOCATE_NEW_LUNS
)) {
409 return STATUS_UNSUCCESSFUL
;
411 return STATUS_SUCCESS
;
414 static BUSMASTER_CONTROLLER_INFORMATION_BASE
const SiSAdapters
[] = {
415 PCI_DEV_HW_SPEC_BM( 1183, 1039, 0x00, ATA_SA150
, "SiS 1183 IDE" , SIS133NEW
),
416 PCI_DEV_HW_SPEC_BM( 1182, 1039, 0x00, ATA_SA150
, "SiS 1182" , SISSATA
| UNIATA_SATA
),
417 PCI_DEV_HW_SPEC_BM( 0183, 1039, 0x00, ATA_SA150
, "SiS 183 RAID" , SISSATA
| UNIATA_SATA
),
418 PCI_DEV_HW_SPEC_BM( 0182, 1039, 0x00, ATA_SA150
, "SiS 182" , SISSATA
| UNIATA_SATA
),
419 PCI_DEV_HW_SPEC_BM( 0181, 1039, 0x00, ATA_SA150
, "SiS 181" , SISSATA
| UNIATA_SATA
),
420 PCI_DEV_HW_SPEC_BM( 0180, 1039, 0x00, ATA_SA150
, "SiS 180" , SISSATA
| UNIATA_SATA
),
421 PCI_DEV_HW_SPEC_BM( 0965, 1039, 0x00, ATA_UDMA6
, "SiS 965" , SIS133NEW
),
422 PCI_DEV_HW_SPEC_BM( 0964, 1039, 0x00, ATA_UDMA6
, "SiS 964" , SIS133NEW
),
423 PCI_DEV_HW_SPEC_BM( 0963, 1039, 0x00, ATA_UDMA6
, "SiS 963" , SIS133NEW
),
424 PCI_DEV_HW_SPEC_BM( 0962, 1039, 0x00, ATA_UDMA6
, "SiS 962" , SIS133NEW
),
426 PCI_DEV_HW_SPEC_BM( 0745, 1039, 0x00, ATA_UDMA5
, "SiS 745" , SIS100NEW
),
427 PCI_DEV_HW_SPEC_BM( 0735, 1039, 0x00, ATA_UDMA5
, "SiS 735" , SIS100NEW
),
428 PCI_DEV_HW_SPEC_BM( 0733, 1039, 0x00, ATA_UDMA5
, "SiS 733" , SIS100NEW
),
429 PCI_DEV_HW_SPEC_BM( 0730, 1039, 0x00, ATA_UDMA5
, "SiS 730" , SIS100OLD
),
431 PCI_DEV_HW_SPEC_BM( 0646, 1039, 0x00, ATA_UDMA6
, "SiS 645DX", SIS133NEW
),
432 /* PCI_DEV_HW_SPEC_BM( 0645, 1039, 0x00, ATA_UDMA6, "SiS 645" , SIS133NEW ),*/
433 /* PCI_DEV_HW_SPEC_BM( 0640, 1039, 0x00, ATA_UDMA4, "SiS 640" , SIS_SOUTH ),*/
434 PCI_DEV_HW_SPEC_BM( 0635, 1039, 0x00, ATA_UDMA5
, "SiS 635" , SIS100NEW
),
435 PCI_DEV_HW_SPEC_BM( 0633, 1039, 0x00, ATA_UDMA5
, "SiS 633" , SIS100NEW
),
436 PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x30, ATA_UDMA5
, "SiS 630S" , SIS100OLD
),
437 PCI_DEV_HW_SPEC_BM( 0630, 1039, 0x00, ATA_UDMA4
, "SiS 630" , SIS66
),
438 PCI_DEV_HW_SPEC_BM( 0620, 1039, 0x00, ATA_UDMA4
, "SiS 620" , SIS66
),
440 PCI_DEV_HW_SPEC_BM( 0550, 1039, 0x00, ATA_UDMA5
, "SiS 550" , SIS66
),
441 PCI_DEV_HW_SPEC_BM( 0540, 1039, 0x00, ATA_UDMA4
, "SiS 540" , SIS66
),
442 PCI_DEV_HW_SPEC_BM( 0530, 1039, 0x00, ATA_UDMA4
, "SiS 530" , SIS66
),
444 // PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x04, ATA_UDMA6, "SiS 962L" , SIS133OLD ), // ???
445 // PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x00, ATA_UDMA6, "SiS 961" , SIS133OLD ),
447 PCI_DEV_HW_SPEC_BM( 5517, 1039, 0x00, ATA_UDMA5
, "SiS 961" , SIS100NEW
| SIS_BASE
),
448 PCI_DEV_HW_SPEC_BM( 5518, 1039, 0x00, ATA_UDMA6
, "SiS 962/3", SIS133NEW
| SIS_BASE
),
449 PCI_DEV_HW_SPEC_BM( 5513, 1039, 0xc2, ATA_UDMA2
, "SiS 5513" , SIS33
| SIS_BASE
),
450 PCI_DEV_HW_SPEC_BM( 5513, 1039, 0x00, ATA_WDMA2
, "SiS 5513" , SIS33
| SIS_BASE
),
451 PCI_DEV_HW_SPEC_BM( 0601, 1039, 0x00, ATA_UDMA2
, "SiS 5513" , SIS33
| SIS_BASE
),
452 PCI_DEV_HW_SPEC_BM( ffff
, ffff
, 0xff, BMLIST_TERMINATOR
, NULL
, BMLIST_TERMINATOR
)
455 static BUSMASTER_CONTROLLER_INFORMATION_BASE
const ViaAdapters
[] = {
456 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x41, ATA_UDMA2
, "VIA 82C586B", VIA33
| 0x00 ),
457 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x40, ATA_UDMA2
, "VIA 82C586B", VIA33
| VIAPRQ
),
458 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x02, ATA_UDMA2
, "VIA 82C586B", VIA33
| 0x00 ),
459 PCI_DEV_HW_SPEC_BM( 0586, 1106, 0x00, ATA_WDMA2
, "VIA 82C586" , VIA33
| 0x00 ),
460 PCI_DEV_HW_SPEC_BM( 0596, 1106, 0x12, ATA_UDMA4
, "VIA 82C596B", VIA66
| VIACLK
),
461 PCI_DEV_HW_SPEC_BM( 0596, 1106, 0x00, ATA_UDMA2
, "VIA 82C596" , VIA33
| 0x00 ),
462 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x40, ATA_UDMA5
, "VIA 82C686B", VIA100
| VIABUG
),
463 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x10, ATA_UDMA4
, "VIA 82C686A", VIA66
| VIACLK
),
464 PCI_DEV_HW_SPEC_BM( 0686, 1106, 0x00, ATA_UDMA2
, "VIA 82C686" , VIA33
| 0x00 ),
465 PCI_DEV_HW_SPEC_BM( 8231, 1106, 0x00, ATA_UDMA5
, "VIA 8231" , VIA100
| VIABUG
),
466 PCI_DEV_HW_SPEC_BM( 3074, 1106, 0x00, ATA_UDMA5
, "VIA 8233" , VIA100
| 0x00 ),
467 PCI_DEV_HW_SPEC_BM( 3109, 1106, 0x00, ATA_UDMA5
, "VIA 8233C" , VIA100
| 0x00 ),
468 PCI_DEV_HW_SPEC_BM( 3147, 1106, 0x00, ATA_UDMA6
, "VIA 8233A" , VIA133
| 0x00 ),
469 PCI_DEV_HW_SPEC_BM( 3177, 1106, 0x00, ATA_UDMA6
, "VIA 8235" , VIA133
| 0x00 ),
470 PCI_DEV_HW_SPEC_BM( 3227, 1106, 0x00, ATA_UDMA6
, "VIA 8237" , VIA133
| 0x00 ),
471 PCI_DEV_HW_SPEC_BM( 0591, 1106, 0x00, ATA_UDMA6
, "VIA 8237A" , VIA133
| 0x00 ),
472 // presence of AHCI controller means something about isa-mapped part
473 PCI_DEV_HW_SPEC_BM( 5337, 1106, 0x00, ATA_UDMA6
, "VIA 8237S" , VIA133
| 0x00 ),
474 PCI_DEV_HW_SPEC_BM( 5372, 1106, 0x00, ATA_UDMA6
, "VIA 8237" , VIA133
| 0x00 ),
475 PCI_DEV_HW_SPEC_BM( 7372, 1106, 0x00, ATA_UDMA6
, "VIA 8237" , VIA133
| 0x00 ),
476 PCI_DEV_HW_SPEC_BM( 3349, 1106, 0x00, ATA_UDMA6
, "VIA 8251" , VIA133
| 0x00 ),
477 PCI_DEV_HW_SPEC_BM( 8324, 1106, 0x00, ATA_SA150
, "VIA CX700" , VIANEW
| VIASATA
),
478 PCI_DEV_HW_SPEC_BM( 8353, 1106, 0x00, ATA_SA150
, "VIA VX800" , VIANEW
| VIASATA
),
479 PCI_DEV_HW_SPEC_BM( 8409, 1106, 0x00, ATA_UDMA6
, "VIA VX855" , VIA133
| 0x00 ),
480 PCI_DEV_HW_SPEC_BM( 8410, 1106, 0x00, ATA_SA300
, "VIA VX900" , VIANEW
| VIASATA
),
481 PCI_DEV_HW_SPEC_BM( ffff
, ffff
, 0xff, BMLIST_TERMINATOR
, NULL
, BMLIST_TERMINATOR
)
484 static BUSMASTER_CONTROLLER_INFORMATION_BASE
const ViaSouthAdapters
[] = {
485 PCI_DEV_HW_SPEC_BM( 3112, 1106, 0x00, ATA_MODE_NOT_SPEC
, "VIA 8361", VIASOUTH
),
486 PCI_DEV_HW_SPEC_BM( 0305, 1106, 0x00, ATA_MODE_NOT_SPEC
, "VIA 8363", VIASOUTH
),
487 PCI_DEV_HW_SPEC_BM( 0391, 1106, 0x00, ATA_MODE_NOT_SPEC
, "VIA 8371", VIASOUTH
),
488 PCI_DEV_HW_SPEC_BM( 3102, 1106, 0x00, ATA_MODE_NOT_SPEC
, "VIA 8662", VIASOUTH
),
489 PCI_DEV_HW_SPEC_BM( ffff
, ffff
, 0xff, BMLIST_TERMINATOR
, NULL
, BMLIST_TERMINATOR
)
492 KdPrint2((PRINT_PREFIX
"VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID
, DeviceID
, RevID
));
498 We shall get here for all SIS controllers, even unlisted.
499 Then perform bus scan to find SIS bridge and decide what to do with controller
501 KdPrint2((PRINT_PREFIX
"ATA_SIS_ID\n"));
502 DevTypeInfo
= (BUSMASTER_CONTROLLER_INFORMATION_BASE
*)&SiSAdapters
[0];
503 i
= AtapiFindListedDev(DevTypeInfo
, -1, HwDeviceExtension
, SystemIoBusNumber
, PCISLOTNUM_NOT_SPECIFIED
, NULL
);
504 if(i
!= BMLIST_TERMINATOR
) {
505 deviceExtension
->FullDevName
= SiSAdapters
[i
].FullDevName
;
510 KdPrint2((PRINT_PREFIX
"ATA_VIA_ID\n"));
511 // New chips have own DeviceId
512 if(deviceExtension
->DevID
!= ATA_VIA82C571
&&
513 deviceExtension
->DevID
!= ATA_VIACX700IDE
&&
514 deviceExtension
->DevID
!= ATA_VIASATAIDE
&&
515 deviceExtension
->DevID
!= ATA_VIASATAIDE2
&&
516 deviceExtension
->DevID
!= ATA_VIASATAIDE3
) {
517 KdPrint2((PRINT_PREFIX
"Via new\n"));
520 KdPrint2((PRINT_PREFIX
"Via-old-style %x\n", deviceExtension
->DevID
));
521 // Traditionally, chips have same DeviceId, we can distinguish between them
522 // only by ISA Bridge DeviceId
523 DevTypeInfo
= (BUSMASTER_CONTROLLER_INFORMATION_BASE
*)&ViaSouthAdapters
[0];
524 i
= AtapiFindListedDev(DevTypeInfo
, -1, HwDeviceExtension
, SystemIoBusNumber
,
525 PCISLOTNUM_NOT_SPECIFIED
/*slotNumber*/, NULL
);
526 /* if(i == BMLIST_TERMINATOR) {
527 i = AtapiFindListedDev(DevTypeInfo, -1, HwDeviceExtension, SystemIoBusNumber, PCISLOTNUM_NOT_SPECIFIED, NULL);
529 if(i
!= BMLIST_TERMINATOR
) {
530 KdPrint2((PRINT_PREFIX
"VIASOUTH\n"));
531 deviceExtension
->HwFlags
|= VIASOUTH
;
533 DevTypeInfo
= (BUSMASTER_CONTROLLER_INFORMATION_BASE
*)&ViaAdapters
[0];
534 i
= AtapiFindListedDev(DevTypeInfo
, -1, HwDeviceExtension
, SystemIoBusNumber
,
535 PCISLOTNUM_NOT_SPECIFIED
/*slotNumber*/, NULL
);
536 if(i
!= BMLIST_TERMINATOR
) {
537 deviceExtension
->FullDevName
= ViaAdapters
[i
].FullDevName
;
547 KdPrint2((PRINT_PREFIX
"Default\n"));
549 deviceExtension
->MaxTransferMode
= deviceExtension
->BaseIoAddressBM_0
? ATA_DMA
: ATA_PIO4
;
550 /* do extra chipset specific setups */
551 switch(deviceExtension
->DevID
) {
553 //case ATA_CYPRESS_ID:
554 case 0xc6931080: /* 82c693 ATA controller */
555 deviceExtension
->MaxTransferMode
= ATA_WDMA2
;
558 case 0x000116ca: /* Cenatek Rocket Drive controller */
559 deviceExtension
->MaxTransferMode
= ATA_WDMA2
;
562 /* case ATA_CYRIX_ID:
563 DevTypeInfo = &CyrixAdapters[0];
565 case 0x01021078: /* Cyrix 5530 ATA33 controller */
566 deviceExtension
->MaxTransferMode
= ATA_UDMA2
;
569 case 0x06401039: /* CMD 640 known bad, no DMA */
575 case 0x10001042: /* RZ 100x known bad, no DMA */
578 if(deviceExtension
->BaseIoAddressBM_0
)
579 ScsiPortFreeDeviceBase(HwDeviceExtension
,
580 deviceExtension
->BaseIoAddressBM_0
);
582 UniataInitIoResEx(&deviceExtension
->BaseIoAddressBM_0
, 0, FALSE
, FALSE
);
583 deviceExtension
->BusMaster
= DMA_MODE_NONE
;
584 deviceExtension
->MaxTransferMode
= ATA_PIO4
;
587 case 0x81721283: /* IT8172 IDE controller */
588 deviceExtension
->MaxTransferMode
= ATA_UDMA2
;
593 return STATUS_NOT_FOUND
;
595 return STATUS_SUCCESS
;
599 i
= Ata_is_dev_listed(DevTypeInfo
, VendorID
, DeviceID
, RevID
, -1);
601 KdPrint2((PRINT_PREFIX
"i: %#x\n", i
));
602 if(i
== BMLIST_TERMINATOR
) {
604 //return STATUS_NOT_FOUND;
606 deviceExtension
->MaxTransferMode
= DevTypeInfo
[i
].MaxTransferMode
;
607 deviceExtension
->HwFlags
|= DevTypeInfo
[i
].RaidFlags
;
609 KdPrint2((PRINT_PREFIX
"HwFlags: %#x\n", deviceExtension
->HwFlags
));
611 tmp32
= AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"HwFlagsOverride", deviceExtension
->HwFlags
);
612 KdPrint2((PRINT_PREFIX
"HwFlagsOverride: %#x\n", tmp32
));
613 deviceExtension
->HwFlags
= tmp32
;
615 tmp32
= AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"HwFlagsAdd", 0);
616 KdPrint2((PRINT_PREFIX
"HwFlagsAdd: %#x\n", tmp32
));
617 deviceExtension
->HwFlags
|= tmp32
;
619 KdPrint2((PRINT_PREFIX
"HwFlags (final): %#x\n", deviceExtension
->HwFlags
));
620 if(deviceExtension
->HwFlags
& UNIATA_SIMPLEX_ONLY
) {
621 KdPrint2((PRINT_PREFIX
"UNIATA_SIMPLEX_ONLY\n" ));
625 KdPrint2((PRINT_PREFIX
"MaxTransferMode: %#x\n", deviceExtension
->MaxTransferMode
));
626 tmp32
= AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"MaxTransferMode", deviceExtension
->MaxTransferMode
);
627 if(tmp32
!= 0xffffffff) {
628 KdPrint2((PRINT_PREFIX
"MaxTransferMode (overriden): %#x\n", deviceExtension
->MaxTransferMode
));
629 deviceExtension
->MaxTransferMode
= tmp32
;
632 if(deviceExtension
->MaxTransferMode
>= ATA_SA150
) {
633 KdPrint2((PRINT_PREFIX
"setting UNIATA_SATA flag\n"));
634 deviceExtension
->HwFlags
|= UNIATA_SATA
;
638 ConfigInfo->MaximumTransferLength = DEV_BSIZE*256;
639 deviceExtension->MaximumDmaTransferLength = ConfigInfo->MaximumTransferLength;
641 ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
642 ChipFlags
= deviceExtension
->HwFlags
& CHIPFLAG_MASK
;
644 /* for even more ugly AHCI-capable chips */
645 if(ChipFlags
& UNIATA_AHCI
) {
647 Seems, some chips may have inoperable/alternative BAR5 in SATA mode
648 This can be detected via PCI SubClass
653 KdPrint2((PRINT_PREFIX
"ATA_xxx_ID check AHCI subclass\n"));
654 if((pciData
)->SubClass
== PCI_DEV_SUBCLASS_IDE
) {
655 KdPrint2((PRINT_PREFIX
"Non-AHCI mode\n"));
656 ChipFlags
&= ~UNIATA_AHCI
;
657 deviceExtension
->HwFlags
&= ~UNIATA_AHCI
;
661 if(!ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo
->AccessRanges
)[5].RangeStart
)) {
662 KdPrint2((PRINT_PREFIX
"No BAR5, try BM\n"));
663 ChipFlags
&= ~UNIATA_AHCI
;
664 deviceExtension
->HwFlags
&= ~UNIATA_AHCI
;
670 if(ChipFlags
& UNIATA_AHCI
) {
672 deviceExtension
->NumberChannels
= 0;
673 if(!UniataAhciDetect(HwDeviceExtension
, pciData
, ConfigInfo
)) {
674 KdPrint2((PRINT_PREFIX
" AHCI detect failed\n"));
675 return STATUS_UNSUCCESSFUL
;
679 if(!UniataChipDetectChannels(HwDeviceExtension
, pciData
, DeviceNumber
, ConfigInfo
)) {
680 return STATUS_UNSUCCESSFUL
;
682 // UniataAhciDetect() sets proper number of channels
683 if(!UniataAllocateLunExt(deviceExtension
, UNIATA_ALLOCATE_NEW_LUNS
)) {
684 return STATUS_UNSUCCESSFUL
;
688 case ATA_ACER_LABS_ID
:
689 if(ChipFlags
& UNIATA_SATA
) {
690 deviceExtension
->AltRegMap
= TRUE
; // inform generic resource allocator
691 BaseIoAddress1
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
693 BaseIoAddress2
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
695 BaseIoAddressBM
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
696 4, 0, deviceExtension
->NumberChannels
*sizeof(IDE_BUSMASTER_REGISTERS
));
697 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
698 //ULONG unit01 = (c & 1);
699 ULONG unit10
= (c
& 2);
700 chan
= &deviceExtension
->chan
[c
];
702 for (i
=0; i
<=IDX_IO1_SZ
; i
++) {
703 UniataInitIoRes(chan
, IDX_IO1
+i
, BaseIoAddress1
+ i
+ (unit10
? 8 : 0), FALSE
, FALSE
);
705 UniataInitIoRes(chan
, IDX_IO2_AltStatus
, BaseIoAddress2
+ 2 + (unit10
? 4 : 0), FALSE
, FALSE
);
706 UniataInitSyncBaseIO(chan
);
708 for (i
=0; i
<=IDX_BM_IO_SZ
; i
++) {
709 UniataInitIoRes(chan
, IDX_BM_IO
+i
, BaseIoAddressBM
+ i
+ (c
* sizeof(IDE_BUSMASTER_REGISTERS
)), FALSE
, FALSE
);
712 // SATA not supported yet
714 //chan->RegTranslation[IDX_BM_Command] = BaseMemAddress + 0x260 + offs7;
715 //chan->RegTranslation[IDX_BM_PRD_Table] = BaseMemAddress + 0x244 + offs7;
716 //chan->RegTranslation[IDX_BM_DeviceSpecific0] = BaseMemAddress + (c << 2);
718 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
723 if(ChipFlags
& UNIATA_SATA
) {
724 KdPrint2((PRINT_PREFIX
"NVIDIA SATA\n"));
725 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
726 5, 0, ((ChipFlags
& NV4OFF
) ? 0x400 : 0) + 0x40*2);
727 KdPrint2((PRINT_PREFIX
"BaseMemAddress %x\n", BaseMemAddress
));
728 if(!BaseMemAddress
) {
729 return STATUS_UNSUCCESSFUL
;
731 if((*ConfigInfo
->AccessRanges
)[5].RangeInMemory
) {
732 KdPrint2((PRINT_PREFIX
"MemIo\n"));
735 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
736 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
737 chan
= &deviceExtension
->chan
[c
];
739 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ (c
<< 6), MemIo
, FALSE
);
740 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ 4 + (c
<< 6), MemIo
, FALSE
);
741 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ 8 + (c
<< 6), MemIo
, FALSE
);
743 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
749 if(ChipType
!= PRMIO
) {
755 deviceExtension
->AltRegMap
= TRUE
; // inform generic resource allocator
758 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
760 KdPrint2((PRINT_PREFIX
"BaseMemAddress[4] %x\n", BaseMemAddress
));
761 if(!BaseMemAddress
) {
762 return STATUS_UNSUCCESSFUL
;
764 if((*ConfigInfo
->AccessRanges
)[4].RangeInMemory
) {
765 KdPrint2((PRINT_PREFIX
"MemIo\n"));
768 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
771 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
773 KdPrint2((PRINT_PREFIX
"BaseMemAddress[3] %x\n", BaseMemAddress
));
774 if(!BaseMemAddress
) {
775 return STATUS_UNSUCCESSFUL
;
777 if((*ConfigInfo
->AccessRanges
)[3].RangeInMemory
) {
778 KdPrint2((PRINT_PREFIX
"MemIo\n"));
781 UniataInitIoResEx(&deviceExtension
->BaseIoAddressBM_0
, BaseMemAddress
, MemIo
, FALSE
);
783 if(!(ChipFlags
& UNIATA_SATA
)) {
786 reg48
= AtapiReadPortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x48);
787 deviceExtension
->NumberChannels
= ((reg48
& 0x01) ? 1 : 0) +
788 ((reg48
& 0x02) ? 1 : 0) +
790 KdPrint2((PRINT_PREFIX
"Channels -> %d\n", deviceExtension
->NumberChannels
));
793 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
798 chan
= &deviceExtension
->chan
[c
];
803 for (i
=0; i
<=IDX_IO1_SZ
; i
++) {
804 UniataInitIoRes(chan
, IDX_IO1
+i
, BaseMemAddress
+ 0x200 + (i
<< 2) + offs8
, MemIo
, FALSE
);
806 UniataInitIoRes(chan
, IDX_IO2_AltStatus
, BaseMemAddress
+ 0x238 + offs7
, MemIo
, FALSE
);
808 UniataInitSyncBaseIO(chan
);
810 UniataInitIoRes(chan
, IDX_BM_Command
, BaseMemAddress
+ 0x260 + offs7
, MemIo
, FALSE
);
811 UniataInitIoRes(chan
, IDX_BM_PRD_Table
, BaseMemAddress
+ 0x244 + offs7
, MemIo
, FALSE
);
812 UniataInitIoRes(chan
, IDX_BM_DeviceSpecific0
, BaseMemAddress
+ (c
<< 2), MemIo
, FALSE
);
814 if((ChipFlags
& PRSATA
) ||
815 ((ChipFlags
& PRCMBO
) && c
<2)) {
816 KdPrint2((PRINT_PREFIX
"Promise SATA\n"));
818 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ 0x400 + offs7
, MemIo
, FALSE
);
819 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ 0x404 + offs7
, MemIo
, FALSE
);
820 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ 0x408 + offs7
, MemIo
, FALSE
);
822 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
824 KdPrint2((PRINT_PREFIX
"Promise PATA\n"));
825 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA6
);
831 KdPrint2((PRINT_PREFIX
"ATI\n"));
832 if(ChipType
== ATI700
) {
833 KdPrint2((PRINT_PREFIX
"ATI700\n"));
834 if(!(ChipFlags
& UNIATA_AHCI
)) {
835 KdPrint2((PRINT_PREFIX
"IXP700 PATA\n"));
836 chan
= &deviceExtension
->chan
[0];
837 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA5
);
842 case ATA_SILICON_IMAGE_ID
: {
844 if(ChipFlags
& SIIBUG
) {
846 if(ChipType
!= SIIMIO
) {
853 if(VendorID
== ATA_SILICON_IMAGE_ID
) {
854 KdPrint2((PRINT_PREFIX
"New SII\n"));
856 KdPrint2((PRINT_PREFIX
"ATI SATA\n"));
858 //if(deviceExtension->HwFlags & SII4CH) {
859 deviceExtension
->AltRegMap
= TRUE
; // inform generic resource allocator
861 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
863 KdPrint2((PRINT_PREFIX
"BaseMemAddress %x\n", BaseMemAddress
));
864 if(!BaseMemAddress
) {
865 return STATUS_UNSUCCESSFUL
;
867 if((*ConfigInfo
->AccessRanges
)[5].RangeInMemory
) {
868 KdPrint2((PRINT_PREFIX
"MemIo\n"));
871 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
873 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
874 ULONG unit01
= (c
& 1);
875 ULONG unit10
= (c
& 2);
877 chan
= &deviceExtension
->chan
[c
];
879 if(deviceExtension
->AltRegMap
) {
880 for (i
=0; i
<=IDX_IO1_SZ
; i
++) {
881 UniataInitIoRes(chan
, IDX_IO1
+i
, BaseMemAddress
+ 0x80 + i
+ (unit01
<< 6) + (unit10
<< 8), MemIo
, FALSE
);
883 UniataInitIoRes(chan
, IDX_IO2_AltStatus
, BaseMemAddress
+ 0x8a + (unit01
<< 6) + (unit10
<< 8), MemIo
, FALSE
);
884 UniataInitSyncBaseIO(chan
);
886 UniataInitIoRes(chan
, IDX_BM_Command
, BaseMemAddress
+ 0x00 + (unit01
<< 3) + (unit10
<< 8), MemIo
, FALSE
);
887 UniataInitIoRes(chan
, IDX_BM_Status
, BaseMemAddress
+ 0x02 + (unit01
<< 3) + (unit10
<< 8), MemIo
, FALSE
);
888 UniataInitIoRes(chan
, IDX_BM_PRD_Table
, BaseMemAddress
+ 0x04 + (unit01
<< 3) + (unit10
<< 8), MemIo
, FALSE
);
889 UniataInitIoRes(chan
, IDX_BM_DeviceSpecific0
, BaseMemAddress
+ 0x10 + (unit01
<< 3) + (unit10
<< 8), MemIo
, FALSE
);
890 UniataInitIoRes(chan
, IDX_BM_DeviceSpecific1
, BaseMemAddress
+ 0x40 + (unit01
<< 2) + (unit10
<< 8), MemIo
, FALSE
);
893 if(chan
->MaxTransferMode
< ATA_SA150
) {
894 // do nothing for PATA part
895 KdPrint2((PRINT_PREFIX
"No SATA regs for PATA part\n"));
897 if(ChipFlags
& UNIATA_SATA
) {
898 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ 0x104 + (unit01
<< 7) + (unit10
<< 8), MemIo
, FALSE
);
899 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ 0x108 + (unit01
<< 2) + (unit10
<< 8), MemIo
, FALSE
);
900 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ 0x100 + (unit01
<< 2) + (unit10
<< 8), MemIo
, FALSE
);
902 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
907 case ATA_SERVERWORKS_ID
: {
909 if(ChipType
!= SWKSMIO
) {
916 KdPrint2((PRINT_PREFIX
"ServerWorks\n"));
918 deviceExtension
->AltRegMap
= TRUE
; // inform generic resource allocator
919 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
921 KdPrint2((PRINT_PREFIX
"BaseMemAddress %x\n", BaseMemAddress
));
922 if(!BaseMemAddress
) {
923 return STATUS_UNSUCCESSFUL
;
925 if((*ConfigInfo
->AccessRanges
)[5].RangeInMemory
) {
926 KdPrint2((PRINT_PREFIX
"MemIo\n"));
929 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
931 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
932 ULONG offs
= c
*0x100;
934 chan
= &deviceExtension
->chan
[c
];
935 for (i
=0; i
<=IDX_IO1_SZ
; i
++) {
936 UniataInitIoRes(chan
, IDX_IO1
+i
, BaseMemAddress
+ offs
+ i
*4, MemIo
, FALSE
);
938 UniataInitIoRes(chan
, IDX_IO2_AltStatus
, BaseMemAddress
+ offs
+ 0x20, MemIo
, FALSE
);
939 UniataInitSyncBaseIO(chan
);
941 UniataInitIoRes(chan
, IDX_BM_Command
, BaseMemAddress
+ offs
+ 0x30, MemIo
, FALSE
);
942 UniataInitIoRes(chan
, IDX_BM_Status
, BaseMemAddress
+ offs
+ 0x32, MemIo
, FALSE
);
943 UniataInitIoRes(chan
, IDX_BM_PRD_Table
, BaseMemAddress
+ offs
+ 0x34, MemIo
, FALSE
);
945 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ offs
+ 0x40, MemIo
, FALSE
);
946 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ offs
+ 0x44, MemIo
, FALSE
);
947 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ offs
+ 0x48, MemIo
, FALSE
);
949 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
954 //if(ChipType != SIS_SOUTH) {}
955 BOOLEAN SIS_182
=FALSE
;
957 if(!(ChipFlags
& SIS_BASE
)) {
958 KdPrint2((PRINT_PREFIX
"Found SIS_SOUTH\n"));
959 //PrintNtConsole("Found SIS_SOUTH\n");
962 // Make some additional checks
963 KdPrint2((PRINT_PREFIX
"ChipType == SIS_BASE\n"));
964 ChangePciConfig1(0x57, (a
& 0x7f));
965 GetPciConfig4(0x00, tmp32
);
966 if(tmp32
== ATA_SIS5518
) {
967 ChipType
= SIS133NEW
;
968 deviceExtension
->HwFlags
= (deviceExtension
->HwFlags
& ~CHIPTYPE_MASK
) | SIS133NEW
;
969 deviceExtension
->MaxTransferMode
= ATA_UDMA6
;
970 KdPrint2((PRINT_PREFIX
"UniataChipDetect: SiS 962/963 DMA %#x controller\n", deviceExtension
->MaxTransferMode
));
971 //PrintNtConsole("UniataChipDetect: SiS 962/963 DMA %#x controller\n", deviceExtension->MaxTransferMode);
973 ChangePciConfig1(0x57, (a
| 0x80));
975 static BUSMASTER_CONTROLLER_INFORMATION_BASE
const SiSSouthAdapters
[] = {
976 PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x10, ATA_MODE_NOT_SPEC
, "SiS 961", 0 ),
977 // PCI_DEV_HW_SPEC_BM( 0008, 1039, 0x00, ATA_MODE_NOT_SPEC, "SiS 961", 0 ),
978 PCI_DEV_HW_SPEC_BM( ffff
, ffff
, 0xff, ATA_MODE_NOT_SPEC
, NULL
, -1 )
981 GetPciConfig1(0x4a, tmp8
);
982 ChangePciConfig1(0x4a, (a
| 0x10));
983 if(tmp32
== ATA_SIS5513
||
984 tmp32
== ATA_SIS5517
) {
985 i
= AtapiFindListedDev((BUSMASTER_CONTROLLER_INFORMATION_BASE
*)&SiSSouthAdapters
[0],
986 -1, HwDeviceExtension
, SystemIoBusNumber
, PCISLOTNUM_NOT_SPECIFIED
, NULL
);
987 if(i
!= BMLIST_TERMINATOR
) {
988 KdPrint2((PRINT_PREFIX
"SIS South\n"));
989 deviceExtension
->HwFlags
= (deviceExtension
->HwFlags
& ~CHIPTYPE_MASK
) | SIS133OLD
;
990 deviceExtension
->MaxTransferMode
= ATA_UDMA6
;
991 //deviceExtension->MaxTransferMode = SiSSouthAdapters[i].MaxTransferMode;
992 if(SiSSouthAdapters
[i
].RaidFlags
& UNIATA_SATA
) {
993 KdPrint2((PRINT_PREFIX
"SIS South SATA\n"));
994 deviceExtension
->HwFlags
|= UNIATA_SATA
;
995 if(SiSSouthAdapters
[i
].nDeviceId
== 0x1182 ||
996 SiSSouthAdapters
[i
].nDeviceId
== 0x1183) {
997 KdPrint2((PRINT_PREFIX
"SIS_182\n"));
1002 // SiS-South not found
1003 if(tmp32
== ATA_SIS5517
) {
1004 deviceExtension
->HwFlags
= (deviceExtension
->HwFlags
& ~CHIPTYPE_MASK
) | SIS100NEW
;
1005 deviceExtension
->MaxTransferMode
= ATA_UDMA5
;
1008 KdPrint2((PRINT_PREFIX
"Generic SiS DMA\n"));
1013 SetPciConfig1(0x4a, tmp8
);
1014 KdPrint2((PRINT_PREFIX
"UniataChipDetect: SiS 961 DMA %#x controller\n", deviceExtension
->MaxTransferMode
));
1015 //PrintNtConsole("UniataChipDetect: SiS 961 DMA %#x controller\n", deviceExtension->MaxTransferMode);
1016 if(deviceExtension
->HwFlags
& UNIATA_SATA
) {
1017 KdPrint2((PRINT_PREFIX
"SiS SATA\n"));
1019 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
1021 KdPrint2((PRINT_PREFIX
"BaseMemAddress %x\n", BaseMemAddress
));
1022 if(BaseMemAddress
) {
1023 if((*ConfigInfo
->AccessRanges
)[5].RangeInMemory
) {
1024 KdPrint2((PRINT_PREFIX
"MemIo\n"));
1027 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
1029 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1030 ULONG offs
= c
<< (SIS_182
? 5 : 6);
1032 chan
= &deviceExtension
->chan
[c
];
1033 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ 0 + offs
, MemIo
, FALSE
);
1034 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ 4 + offs
, MemIo
, FALSE
);
1035 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ 8 + offs
, MemIo
, FALSE
);
1037 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
1042 //ChangePciConfig1(0x57, (a | 0x80));
1047 if(ChipFlags
& VIASATA
) {
1048 /* 2 SATA without SATA registers on first channel + 1 PATA on second */
1049 // do nothing, generic PATA INIT
1050 KdPrint2((PRINT_PREFIX
"VIA SATA without SATA regs\n"));
1053 if(ChipFlags
& UNIATA_SATA
) {
1059 case 0x3149: // VIA 6420
1060 KdPrint2((PRINT_PREFIX
"VIA 6420\n"));
1063 case 0x3249: // VIA 6421
1064 KdPrint2((PRINT_PREFIX
"VIA 6421\n"));
1069 KdPrint2((PRINT_PREFIX
"IoSize %x\n", IoSize
));
1070 /*deviceExtension->*/BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
1071 5, 0, IoSize
* deviceExtension
->NumberChannels
);
1072 if(BaseMemAddress
&& (*ConfigInfo
->AccessRanges
)[5].RangeInMemory
) {
1073 KdPrint2((PRINT_PREFIX
"MemIo\n"));
1076 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
1078 if(/*deviceExtension->*/BaseMemAddress
) {
1079 KdPrint2((PRINT_PREFIX
"UniataChipDetect: BAR5 %x\n", /*deviceExtension->*/BaseMemAddress
));
1080 if(ChipFlags
& VIABAR
) {
1082 ULONG BaseIoAddressBM_0
;
1085 KdPrint2((PRINT_PREFIX
"UniataChipDetect: VIABAR\n"));
1086 /*deviceExtension->*/BaseIoAddressBM_0
= /*(PIDE_BUSMASTER_REGISTERS)*/
1087 AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
, 4, 0,
1088 sizeof(IDE_BUSMASTER_REGISTERS
)*deviceExtension
->NumberChannels
);
1089 deviceExtension
->AltRegMap
= TRUE
; // inform generic resource allocator
1090 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1092 chan
= &deviceExtension
->chan
[c
];
1094 BaseIo
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
, c
, 0, /*0x80*/ sizeof(IDE_REGISTERS_1
) + sizeof(IDE_REGISTERS_2
)*2);
1096 for (i
=0; i
<=IDX_IO1_SZ
; i
++) {
1097 UniataInitIoRes(chan
, IDX_IO1
+i
, BaseIo
+ i
, FALSE
, FALSE
);
1099 UniataInitIoRes(chan
, IDX_IO2_AltStatus
, BaseIo
+ sizeof(IDE_REGISTERS_1
) + 2, FALSE
, FALSE
);
1100 UniataInitSyncBaseIO(chan
);
1102 for (i
=0; i
<=IDX_BM_IO_SZ
; i
++) {
1103 UniataInitIoRes(chan
, IDX_BM_IO
+i
, BaseIoAddressBM_0
+ sizeof(IDE_BUSMASTER_REGISTERS
)*c
+ i
, FALSE
, FALSE
);
1108 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1109 chan
= &deviceExtension
->chan
[c
];
1110 if((ChipFlags
& VIABAR
) && (c
==2)) {
1111 // Do not setup SATA registers for PATA part
1112 for (i
=0; i
<=IDX_SATA_IO_SZ
; i
++) {
1113 UniataInitIoRes(chan
, IDX_SATA_IO
+i
, 0, FALSE
, FALSE
);
1117 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ (c
* IoSize
), MemIo
, FALSE
);
1118 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ 4 + (c
* IoSize
), MemIo
, FALSE
);
1119 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ 8 + (c
* IoSize
), MemIo
, FALSE
);
1121 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
1127 case ATA_INTEL_ID
: {
1129 if(!(ChipFlags
& UNIATA_SATA
)) {
1133 /* the intel 31244 needs special care if in DPA mode */
1134 if(DeviceID
== 3200 && // Intel 31244
1135 pciData
->SubClass
!= PCI_DEV_SUBCLASS_IDE
) {
1137 KdPrint2((PRINT_PREFIX
"UniataChipDetect: Intel 31244, DPA mode\n"));
1138 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
1140 if(!BaseMemAddress
) {
1141 return STATUS_UNSUCCESSFUL
;
1143 if((*ConfigInfo
->AccessRanges
)[0].RangeInMemory
) {
1144 KdPrint2((PRINT_PREFIX
"MemIo\n"));
1147 deviceExtension
->AltRegMap
= TRUE
; // inform generic resource allocator
1148 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
1150 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1151 ULONG offs
= 0x200 + c
*0x200;
1153 chan
= &deviceExtension
->chan
[c
];
1154 for (i
=0; i
<=IDX_IO1_SZ
; i
++) {
1155 UniataInitIoRes(chan
, IDX_BM_IO
+i
, BaseMemAddress
+ i
*4 + offs
, MemIo
, FALSE
);
1158 UniataInitSyncBaseIO(chan
);
1160 UniataInitIoRes(chan
, IDX_IO1_o_Command
, BaseMemAddress
+ 0x1d + offs
, MemIo
, FALSE
);
1161 UniataInitIoRes(chan
, IDX_IO1_o_Feature
, BaseMemAddress
+ 0x06 + offs
, MemIo
, FALSE
);
1162 UniataInitIoRes(chan
, IDX_IO2_o_Control
, BaseMemAddress
+ 0x29 + offs
, MemIo
, FALSE
);
1164 UniataInitIoRes(chan
, IDX_IO2_AltStatus
, BaseMemAddress
+ 0x28 + offs
, MemIo
, FALSE
);
1166 UniataInitIoRes(chan
, IDX_BM_Command
, BaseMemAddress
+ 0x70 + offs
, MemIo
, FALSE
);
1167 UniataInitIoRes(chan
, IDX_BM_Status
, BaseMemAddress
+ 0x72 + offs
, MemIo
, FALSE
);
1168 UniataInitIoRes(chan
, IDX_BM_PRD_Table
, BaseMemAddress
+ 0x74 + offs
, MemIo
, FALSE
);
1170 UniataInitIoRes(chan
, IDX_SATA_SStatus
, BaseMemAddress
+ 0x100 + offs
, MemIo
, FALSE
);
1171 UniataInitIoRes(chan
, IDX_SATA_SError
, BaseMemAddress
+ 0x104 + offs
, MemIo
, FALSE
);
1172 UniataInitIoRes(chan
, IDX_SATA_SControl
, BaseMemAddress
+ 0x108 + offs
, MemIo
, FALSE
);
1174 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
1179 if(deviceExtension
->MaxTransferMode
>= ATA_SA150
) {
1181 BOOLEAN OrigAHCI
= FALSE
;
1183 GetPciConfig1(0x90, tmp8
);
1184 KdPrint2((PRINT_PREFIX
"Intel chip config: %x\n", tmp8
));
1185 /* SATA parts can be either compat or AHCI */
1187 if(ChipFlags
& UNIATA_AHCI
) {
1190 //KdPrint2((PRINT_PREFIX "AHCI not supported yet\n"));
1192 KdPrint2((PRINT_PREFIX
"try run AHCI\n"));
1193 if(ScsiPortConvertPhysicalAddressToUlong((*ConfigInfo
->AccessRanges
)[5].RangeStart
)) {
1196 KdPrint2((PRINT_PREFIX
"No BAR5, try BM\n"));
1197 deviceExtension
->HwFlags
&= ~UNIATA_AHCI
;
1199 BaseIoAddressBM
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
1200 4, 0, sizeof(IDE_BUSMASTER_REGISTERS
));
1201 if(BaseIoAddressBM
) {
1202 KdPrint2((PRINT_PREFIX
"Intel BM check at %x\n", BaseIoAddressBM
));
1203 /* check if we really have valid BM registers */
1204 if((*ConfigInfo
->AccessRanges
)[4].RangeInMemory
) {
1205 KdPrint2((PRINT_PREFIX
"MemIo[4]\n"));
1208 UniataInitIoResEx(&deviceExtension
->BaseIoAddressBM_0
, BaseIoAddressBM
, MemIo
, FALSE
);
1210 tmp8
= AtapiReadPortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),IDX_BM_Status
);
1211 KdPrint2((PRINT_PREFIX
"BM status: %x\n", tmp8
));
1214 ScsiPortFreeDeviceBase(HwDeviceExtension
, (PCHAR
)(ULONG_PTR
)BaseIoAddressBM
);
1216 ScsiPortFreeDeviceBase(HwDeviceExtension
, (PCHAR
)BaseIoAddressBM
);
1218 UniataInitIoResEx(&deviceExtension
->BaseIoAddressBM_0
, 0, 0, FALSE
);
1221 KdPrint2((PRINT_PREFIX
"invalid BM status, keep AHCI mode\n"));
1225 KdPrint2((PRINT_PREFIX
"Compatible mode, reallocate LUNs\n"));
1226 deviceExtension
->NumberLuns
= 2; // we may be in Legacy mode
1227 if(!UniataAllocateLunExt(deviceExtension
, 2)) {
1228 KdPrint2((PRINT_PREFIX
"can't re-allocate Luns\n"));
1229 return STATUS_UNSUCCESSFUL
;
1232 deviceExtension
->HwFlags
&= ~UNIATA_AHCI
;
1235 /* if BAR(5) is IO it should point to SATA interface registers */
1237 /* Skip BAR(5) in compatible mode */
1238 KdPrint2((PRINT_PREFIX
"Ignore BAR5 on compatible\n"));
1241 if(deviceExtension
->DevID
== 0x28288086 &&
1242 pciData
->u
.type0
.SubVendorID
== 0x106b) {
1243 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */
1244 KdPrint2((PRINT_PREFIX
"Ignore BAR5 on ICH8M Apples\n"));
1247 BaseMemAddress
= AtapiGetIoRange(HwDeviceExtension
, ConfigInfo
, pciData
, SystemIoBusNumber
,
1249 if(BaseMemAddress
&& (*ConfigInfo
->AccessRanges
)[5].RangeInMemory
) {
1250 KdPrint2((PRINT_PREFIX
"MemIo[5]\n"));
1254 UniataInitIoResEx(&deviceExtension
->BaseIoAddressSATA_0
, BaseMemAddress
, MemIo
, FALSE
);
1256 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1257 chan
= &deviceExtension
->chan
[c
];
1259 if(ChipFlags
& ICH5
) {
1260 KdPrint2((PRINT_PREFIX
"ICH5\n"));
1261 if ((tmp8
& 0x04) == 0) {
1262 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
1263 } else if ((tmp8
& 0x02) == 0) {
1266 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
1268 } else if ((tmp8
& 0x02) != 0) {
1271 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
1275 if(ChipFlags
& I6CH2
) {
1276 KdPrint2((PRINT_PREFIX
"I6CH2\n"));
1277 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
1279 KdPrint2((PRINT_PREFIX
"other Intel\n"));
1280 switch(tmp8
& 0x03) {
1297 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA5
);
1298 KdPrint2((PRINT_PREFIX
"PATA part\n"));
1301 if(!(ChipFlags
& ICH7
) && BaseMemAddress
) {
1302 KdPrint2((PRINT_PREFIX
"BaseMemAddress[5] -> indexed\n"));
1303 UniataInitIoRes(chan
, IDX_INDEXED_ADDR
, BaseMemAddress
+ 0, MemIo
, FALSE
);
1304 UniataInitIoRes(chan
, IDX_INDEXED_DATA
, BaseMemAddress
+ 4, MemIo
, FALSE
);
1306 if((ChipFlags
& ICH5
) || BaseMemAddress
) {
1308 KdPrint2((PRINT_PREFIX
"io proc()\n"));
1309 // Rather interesting way of register access...
1310 ChipType
= INTEL_IDX
;
1311 deviceExtension
->HwFlags
&= ~CHIPTYPE_MASK
;
1312 deviceExtension
->HwFlags
|= ChipType
;
1314 if(ChipFlags
& ICH7
) {
1315 KdPrint2((PRINT_PREFIX
"ICH7 way\n"));
1317 UniataInitIoRes(chan
, IDX_SATA_SStatus
, 0x200*c
+ 0, FALSE
, TRUE
); // this is fake non-zero value
1318 UniataInitIoRes(chan
, IDX_SATA_SError
, 0x200*c
+ 2, FALSE
, TRUE
);
1319 UniataInitIoRes(chan
, IDX_SATA_SControl
, 0x200*c
+ 1, FALSE
, TRUE
);
1325 // rest of INIT staff is in AtapiChipInit()
1330 /* Cyrix 5530 ATA33 controller */
1331 if(deviceExtension
->DevID
== 0x01021078) {
1332 ConfigInfo
->AlignmentMask
= 0x0f;
1333 deviceExtension
->MaximumDmaTransferLength
= 63*1024;
1336 case ATA_JMICRON_ID
:
1337 /* New JMicron PATA controllers */
1338 GetPciConfig1(0xdf, tmp8
);
1340 KdPrint((" Check JMicron AHCI\n"));
1341 if(Ata_is_ahci_dev(pciData
)) {
1342 ChipFlags
|= UNIATA_AHCI
;
1343 deviceExtension
->HwFlags
|= UNIATA_AHCI
;
1345 KdPrint((" JMicron PATA\n"));
1348 /* set controller configuration to a combined setup we support */
1349 SetPciConfig4(0x40, 0x80c0a131);
1350 SetPciConfig4(0x80, 0x01200000);
1351 //KdPrint((" JMicron Combined (not supported yet)\n"));
1352 //return STATUS_NOT_FOUND;
1357 return STATUS_SUCCESS
;
1359 } // end UniataChipDetect()
1363 Do some 'magic staff' for VIA SouthBridge
1364 This will prevent data losses
1368 AtapiViaSouthBridgeFixup(
1369 IN PVOID HwDeviceExtension
,
1370 IN BUS_DATA_TYPE BusDataType
,
1371 IN ULONG SystemIoBusNumber
,
1375 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
1376 PCI_COMMON_CONFIG pciData
;
1382 PCI_SLOT_NUMBER slotData
;
1384 BOOLEAN found
= FALSE
;
1386 slotData
.u
.AsULONG
= slotNumber
;
1387 for(funcNumber
= 0; funcNumber
< PCI_MAX_FUNCTION
; funcNumber
++) {
1389 slotData
.u
.bits
.FunctionNumber
= funcNumber
;
1391 busDataRead
= ScsiPortGetBusData(HwDeviceExtension
,
1396 PCI_COMMON_HDR_LENGTH
);
1398 if (busDataRead
< (ULONG
)PCI_COMMON_HDR_LENGTH
) {
1402 VendorID
= pciData
.VendorID
;
1403 DeviceID
= pciData
.DeviceID
;
1404 dev_id
= (VendorID
| (DeviceID
<< 16));
1406 if (dev_id
== 0x03051106 || /* VIA VT8363 */
1407 dev_id
== 0x03911106 || /* VIA VT8371 */
1408 dev_id
== 0x31021106 || /* VIA VT8662 */
1409 dev_id
== 0x31121106) { /* VIA VT8361 */
1412 GetPciConfig1(0x76, reg76
);
1414 if ((reg76
& 0xf0) != 0xd0) {
1415 SetPciConfig1(0x75, 0x80);
1416 SetPciConfig1(0x76, (reg76
& 0x0f) | 0xd0);
1423 deviceExtension
->HwFlags
&= ~VIABUG
;
1425 } // end AtapiViaSouthBridgeFixup()
1428 Do some 'magic staff' for ROSB SouthBridge
1429 This will prevent data losses
1433 AtapiRosbSouthBridgeFixup(
1434 IN PVOID HwDeviceExtension
,
1435 IN BUS_DATA_TYPE BusDataType
,
1436 IN ULONG SystemIoBusNumber
,
1440 //PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1441 PCI_COMMON_CONFIG pciData
;
1447 PCI_SLOT_NUMBER slotData
;
1449 // BOOLEAN found = FALSE;
1451 /* locate the ISA part in the southbridge and enable UDMA33 */
1452 slotData
.u
.AsULONG
= slotNumber
;
1453 for(funcNumber
= 0; funcNumber
< PCI_MAX_FUNCTION
; funcNumber
++) {
1455 slotData
.u
.bits
.FunctionNumber
= funcNumber
;
1457 busDataRead
= ScsiPortGetBusData(HwDeviceExtension
,
1462 PCI_COMMON_HDR_LENGTH
);
1464 if (busDataRead
< (ULONG
)PCI_COMMON_HDR_LENGTH
) {
1468 VendorID
= pciData
.VendorID
;
1469 DeviceID
= pciData
.DeviceID
;
1470 dev_id
= (VendorID
| (DeviceID
<< 16));
1472 if (dev_id
== ATA_ROSB4_ISA
) { /* */
1473 ChangePciConfig4(0x64, ((a
& ~0x00002000) | 0x00004000));
1477 } // end AtapiRosbSouthBridgeFixup()
1480 Do some 'magic staff' for ROSB SouthBridge
1481 This will prevent data losses
1485 AtapiAliSouthBridgeFixup(
1486 IN PVOID HwDeviceExtension
,
1487 IN BUS_DATA_TYPE BusDataType
,
1488 IN ULONG SystemIoBusNumber
,
1489 IN ULONG slotNumber
,
1493 //PHW_DEVICE_EXTENSION deviceExtension = (PHW_DEVICE_EXTENSION)HwDeviceExtension;
1494 PCI_COMMON_CONFIG pciData
;
1500 PCI_SLOT_NUMBER slotData
;
1502 // BOOLEAN found = FALSE;
1504 /* workaround for datacorruption bug found on at least SUN Blade-100
1505 * find the ISA function on the southbridge and disable then enable
1506 * the ATA channel tristate buffer */
1507 slotData
.u
.AsULONG
= slotNumber
;
1508 for(funcNumber
= 0; funcNumber
< PCI_MAX_FUNCTION
; funcNumber
++) {
1510 slotData
.u
.bits
.FunctionNumber
= funcNumber
;
1512 busDataRead
= ScsiPortGetBusData(HwDeviceExtension
,
1517 PCI_COMMON_HDR_LENGTH
);
1519 if (busDataRead
< (ULONG
)PCI_COMMON_HDR_LENGTH
) {
1523 VendorID
= pciData
.VendorID
;
1524 DeviceID
= pciData
.DeviceID
;
1525 dev_id
= (VendorID
| (DeviceID
<< 16));
1527 if (dev_id
== ATA_ALI_1533
) { /* SOUTH */
1528 ChangePciConfig1(0x58, (a
& ~(0x04 << c
)));
1529 ChangePciConfig1(0x58, (a
| (0x04 << c
)));
1533 } // end AtapiRosbSouthBridgeFixup()
1538 IN PHW_DEVICE_EXTENSION deviceExtension
,
1539 IN ULONG channel
// physical channel number (0-1)
1542 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
1543 ULONG slotNumber
= deviceExtension
->slotNumber
;
1544 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
1546 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
1548 UCHAR reg
, val
, res
;
1549 PCI_SLOT_NUMBER slotData
;
1552 ULONG c
; // logical channel (for Compatible Mode controllers)
1554 c
= channel
- deviceExtension
->Channel
; // logical channel (for Compatible Mode controllers)
1555 chan
= &deviceExtension
->chan
[c
];
1557 slotData
.u
.AsULONG
= deviceExtension
->slotNumber
;
1559 if(deviceExtension
->HwFlags
& UNIATA_NO80CHK
) {
1560 KdPrint2((PRINT_PREFIX
"UNIATA_NO80CHK\n"));
1564 if(ChipType
== HPT374
&& slotData
.u
.bits
.FunctionNumber
== 1) {
1565 reg
= channel
? 0x57 : 0x53;
1566 GetPciConfig1(reg
, val
);
1567 SetPciConfig1(reg
, val
| 0x80);
1571 GetPciConfig1(reg
, val
);
1572 SetPciConfig1(reg
, val
& 0xfe);
1574 GetPciConfig1(0x5a, res
);
1575 res
= res
& (channel
? 0x01 : 0x02);
1576 SetPciConfig1(reg
, val
);
1577 if(chan
->Force80pin
) {
1578 KdPrint2((PRINT_PREFIX
"Force80pin\n"));
1581 KdPrint2((PRINT_PREFIX
"hpt_cable80(%d) = %d\n", channel
, !res
));
1583 } // end hpt_cable80()
1589 IN PHW_DEVICE_EXTENSION deviceExtension,
1590 IN ULONG channel // physical channel number (0-1)
1593 PVOID HwDeviceExtension = (PVOID)deviceExtension;
1594 ULONG slotNumber = deviceExtension->slotNumber;
1595 ULONG SystemIoBusNumber = deviceExtension->SystemIoBusNumber;
1597 ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1604 GetPciConfig1(0x50, reg50);
1621 for (j=0; j>=2; i -= 8) {
1622 i = (3-(channel*2+j))*8;
1623 if (((reg50 >> (i & 0x10)) & 8) &&
1624 ((reg50 >> i) & 0x20) &&
1625 (((reg50 >> i) & 7) < a)) {
1627 res |= TRUE; //(1 << (1 - (i >> 4)));
1630 KdPrint2((PRINT_PREFIX "via_cable80(%d) = %d\n", channel, res));
1633 } // end via_cable80()
1639 IN PHW_DEVICE_EXTENSION deviceExtension
,
1640 IN ULONG channel
, // physical channel number (0-1)
1645 PVOID HwDeviceExtension
= (PVOID
)deviceExtension
;
1646 ULONG slotNumber
= deviceExtension
->slotNumber
;
1647 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
1649 if(deviceExtension
->MaxTransferMode
<= ATA_UDMA2
) {
1650 KdPrint2((PRINT_PREFIX
"generic_cable80(%d, %#x, %d) <= UDMA2\n", channel
, pci_reg
, bit_offs
));
1654 //ULONG ChipType = deviceExtension->HwFlags & CHIPTYPE_MASK;
1656 ULONG c
; // logical channel (for Compatible Mode controllers)
1659 c
= channel
- deviceExtension
->Channel
; // logical channel (for Compatible Mode controllers)
1660 chan
= &deviceExtension
->chan
[c
];
1662 if(chan
->Force80pin
) {
1663 KdPrint2((PRINT_PREFIX
"Force80pin\n"));
1667 GetPciConfig1(pci_reg
, tmp8
);
1668 if(!(tmp8
& (1 << (channel
<< bit_offs
)))) {
1669 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
1670 KdPrint2((PRINT_PREFIX
"generic_cable80(%d, %#x, %d) = 0\n", channel
, pci_reg
, bit_offs
));
1674 KdPrint2((PRINT_PREFIX
"generic_cable80(%d, %#x, %d) = 1\n", channel
, pci_reg
, bit_offs
));
1676 } // end generic_cable80()
1680 UniAtaReadLunConfig(
1681 IN PHW_DEVICE_EXTENSION deviceExtension
,
1682 IN ULONG channel
, // physical channel
1683 IN ULONG DeviceNumber
1688 PHW_LU_EXTENSION LunExt
;
1691 c
= channel
- deviceExtension
->Channel
; // logical channel
1693 chan
= &deviceExtension
->chan
[c
];
1694 DeviceNumber
= (DeviceNumber
% deviceExtension
->NumberLuns
);
1695 LunExt
= chan
->lun
[DeviceNumber
];
1697 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"ReadCacheEnable", 1);
1698 LunExt
->opt_ReadCacheEnable
= tmp32
? TRUE
: FALSE
;
1700 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"WriteCacheEnable", 1);
1701 LunExt
->opt_WriteCacheEnable
= tmp32
? TRUE
: FALSE
;
1703 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"MaxTransferMode", chan
->MaxTransferMode
);
1704 LunExt
->opt_MaxTransferMode
= tmp32
;
1706 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"PreferedTransferMode", 0xffffffff);
1707 LunExt
->opt_PreferedTransferMode
= tmp32
;
1709 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"AdvancedPowerMode", ATA_C_F_APM_CNT_MIN_NO_STANDBY
);
1711 tmp32
= 0xfe; // max. performance
1713 LunExt
->opt_AdvPowerMode
= (UCHAR
)tmp32
;
1715 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"AcousticMgmt", ATA_C_F_AAM_CNT_MAX_POWER_SAVE
);
1717 tmp32
= 0xfe; // max. performance
1720 tmp32
= 0x0; // disable feature
1722 LunExt
->opt_AcousticMode
= (UCHAR
)tmp32
;
1724 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"StandbyTimer", 0);
1728 LunExt
->opt_StandbyTimer
= (UCHAR
)tmp32
;
1730 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"ReadOnly", 0);
1732 LunExt
->opt_ReadOnly
= (UCHAR
)tmp32
;
1735 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"GeomType", 0xffffffff);
1736 if(tmp32
> GEOM_MANUAL
) {
1739 LunExt
->opt_GeomType
= tmp32
;
1740 if(tmp32
== GEOM_MANUAL
) {
1741 LunExt
->DeviceFlags
|= DFLAGS_MANUAL_CHS
;
1742 LunExt
->opt_GeomType
= GEOM_ORIG
;
1743 // assume IdentifyData is already zero-filled
1744 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"C", 0);
1745 LunExt
->IdentifyData
.NumberOfCurrentCylinders
=
1746 LunExt
->IdentifyData
.NumberOfCylinders
= (USHORT
)tmp32
;
1747 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"H", 0);
1748 LunExt
->IdentifyData
.NumberOfCurrentHeads
=
1749 LunExt
->IdentifyData
.NumberOfHeads
= (USHORT
)tmp32
;
1750 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"S", 0);
1751 LunExt
->IdentifyData
.CurrentSectorsPerTrack
=
1752 LunExt
->IdentifyData
.SectorsPerTrack
= (USHORT
)tmp32
;
1753 memcpy(LunExt
->IdentifyData
.ModelNumber
, "SEIDH DD", 8); // ESDI HDD
1754 memcpy(LunExt
->IdentifyData
.SerialNumber
, ".10", 4);
1755 memcpy(LunExt
->IdentifyData
.FirmwareRevision
, ".10", 4);
1756 if(!LunExt
->IdentifyData
.SectorsPerTrack
||
1757 !LunExt
->IdentifyData
.NumberOfCylinders
||
1758 !LunExt
->IdentifyData
.NumberOfHeads
) {
1760 KdPrint2((PRINT_PREFIX
"Wrong CHS\n"));
1761 LunExt
->opt_GeomType
= GEOM_AUTO
;
1763 LunExt
->DeviceFlags
|= DFLAGS_MANUAL_CHS
;
1764 LunExt
->opt_GeomType
= GEOM_ORIG
;
1768 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"Hidden", 0);
1770 LunExt
->DeviceFlags
|= DFLAGS_HIDDEN
;
1772 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DeviceNumber
, L
"Exclude", 0);
1774 LunExt
->DeviceFlags
|= DFLAGS_HIDDEN
;
1778 } // end UniAtaReadLunConfig()
1782 AtapiReadChipConfig(
1783 IN PVOID HwDeviceExtension
,
1784 IN ULONG DeviceNumber
,
1785 IN ULONG channel
// physical channel
1788 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
1791 ULONG c
; // logical channel (for Compatible Mode controllers)
1794 KdPrint2((PRINT_PREFIX
"AtapiReadChipConfig: devExt %#x\n", deviceExtension
));
1795 ASSERT(deviceExtension
);
1797 if(channel
!= CHAN_NOT_SPECIFIED
) {
1798 c
= channel
- deviceExtension
->Channel
; // logical channel (for Compatible Mode controllers)
1800 c
= CHAN_NOT_SPECIFIED
;
1803 KdPrint2((PRINT_PREFIX
"AtapiReadChipConfig: dev %#x, ph chan %d\n", DeviceNumber
, channel
));
1805 if(channel
== CHAN_NOT_SPECIFIED
) {
1806 if(AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"ForceSimplex", FALSE
)) {
1807 deviceExtension
->simplexOnly
= TRUE
;
1809 deviceExtension
->opt_AtapiDmaZeroTransfer
= FALSE
;
1810 deviceExtension
->opt_AtapiDmaControlCmd
= FALSE
;
1811 deviceExtension
->opt_AtapiDmaRawRead
= g_opt_AtapiDmaRawRead
;
1812 deviceExtension
->opt_AtapiDmaReadWrite
= TRUE
;
1815 if(c
== CHAN_NOT_SPECIFIED
) {
1816 KdPrint2((PRINT_PREFIX
"MaxTransferMode (base): %#x\n", deviceExtension
->MaxTransferMode
));
1817 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1818 chan
= &deviceExtension
->chan
[c
];
1819 chan
->MaxTransferMode
= deviceExtension
->MaxTransferMode
;
1820 tmp32
= AtapiRegCheckDevValue(deviceExtension
, channel
, DEVNUM_NOT_SPECIFIED
, L
"MaxTransferMode", chan
->MaxTransferMode
);
1821 if(tmp32
!= 0xffffffff) {
1822 KdPrint2((PRINT_PREFIX
"MaxTransferMode (overriden): %#x\n", chan
->MaxTransferMode
));
1823 chan
->MaxTransferMode
= tmp32
;
1825 tmp32
= AtapiRegCheckDevValue(deviceExtension
, c
, DEVNUM_NOT_SPECIFIED
, L
"Force80pin", FALSE
);
1826 chan
->Force80pin
= tmp32
? TRUE
: FALSE
;
1827 if(chan
->Force80pin
) {
1828 KdPrint2((PRINT_PREFIX
"Force80pin on chip\n"));
1829 deviceExtension
->HwFlags
|= UNIATA_NO80CHK
;
1832 //UniAtaReadLunConfig(deviceExtension, c, 0);
1833 //UniAtaReadLunConfig(deviceExtension, c, 1);
1836 deviceExtension
->opt_AtapiDmaZeroTransfer
=
1837 AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"AtapiDmaZeroTransfer", deviceExtension
->opt_AtapiDmaZeroTransfer
) ?
1840 deviceExtension
->opt_AtapiDmaControlCmd
=
1841 AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"AtapiDmaControlCmd", deviceExtension
->opt_AtapiDmaControlCmd
) ?
1844 deviceExtension
->opt_AtapiDmaRawRead
=
1845 AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"AtapiDmaRawRead", deviceExtension
->opt_AtapiDmaRawRead
) ?
1848 deviceExtension
->opt_AtapiDmaReadWrite
=
1849 AtapiRegCheckDevValue(deviceExtension
, CHAN_NOT_SPECIFIED
, DEVNUM_NOT_SPECIFIED
, L
"AtapiDmaReadWrite", deviceExtension
->opt_AtapiDmaReadWrite
) ?
1853 chan
= &deviceExtension
->chan
[c
];
1854 chan
->MaxTransferMode
= deviceExtension
->MaxTransferMode
;
1855 tmp32
= AtapiRegCheckDevValue(deviceExtension
, c
, DEVNUM_NOT_SPECIFIED
, L
"MaxTransferMode", chan
->MaxTransferMode
);
1856 if(tmp32
!= 0xffffffff) {
1857 KdPrint2((PRINT_PREFIX
"MaxTransferMode (overriden): %#x\n", chan
->MaxTransferMode
));
1858 chan
->MaxTransferMode
= tmp32
;
1860 tmp32
= AtapiRegCheckDevValue(deviceExtension
, c
, DEVNUM_NOT_SPECIFIED
, L
"ReorderEnable", TRUE
);
1861 chan
->UseReorder
= tmp32
? TRUE
: FALSE
;
1863 tmp32
= AtapiRegCheckDevValue(deviceExtension
, c
, DEVNUM_NOT_SPECIFIED
, L
"Force80pin", FALSE
);
1864 chan
->Force80pin
= tmp32
? TRUE
: FALSE
;
1865 if(chan
->Force80pin
) {
1866 KdPrint2((PRINT_PREFIX
"Force80pin on channel\n"));
1869 for(i
=0; i
<deviceExtension
->NumberLuns
; i
++) {
1870 UniAtaReadLunConfig(deviceExtension
, channel
, i
);
1875 } // end AtapiReadChipConfig()
1880 IN PVOID HwDeviceExtension
,
1881 IN ULONG DeviceNumber
,
1882 IN ULONG channel
// logical channel
1885 PHW_DEVICE_EXTENSION deviceExtension
= (PHW_DEVICE_EXTENSION
)HwDeviceExtension
;
1886 ULONG slotNumber
= deviceExtension
->slotNumber
;
1887 ULONG SystemIoBusNumber
= deviceExtension
->SystemIoBusNumber
;
1888 ULONG VendorID
= deviceExtension
->DevID
& 0xffff;
1889 ULONG DeviceID
= (deviceExtension
->DevID
>> 16) & 0xffff;
1890 ULONG RevID
= deviceExtension
->RevID
;
1892 // BUSMASTER_CONTROLLER_INFORMATION_BASE* DevTypeInfo;
1893 ULONG ChipType
= deviceExtension
->HwFlags
& CHIPTYPE_MASK
;
1894 ULONG ChipFlags
= deviceExtension
->HwFlags
& CHIPFLAG_MASK
;
1899 ULONG c
; // logical channel (for Compatible Mode controllers)
1900 BOOLEAN CheckCable
= FALSE
;
1901 BOOLEAN GlobalInit
= FALSE
;
1902 //ULONG BaseIoAddress;
1905 case CHAN_NOT_SPECIFIED_CHECK_CABLE
:
1908 case CHAN_NOT_SPECIFIED
:
1909 c
= CHAN_NOT_SPECIFIED
;
1913 //c = channel - deviceExtension->Channel; // logical channel (for Compatible Mode controllers)
1915 channel
+= deviceExtension
->Channel
;
1918 KdPrint2((PRINT_PREFIX
"AtapiChipInit: dev %#x, ph chan %d, c %d\n", DeviceNumber
, channel
, c
));
1920 KdPrint2((PRINT_PREFIX
"HwFlags: %#x\n", deviceExtension
->HwFlags
));
1921 KdPrint2((PRINT_PREFIX
"VendorID/DeviceID/Rev %#x/%#x/%#x\n", VendorID
, DeviceID
, RevID
));
1923 if(deviceExtension
->UnknownDev
) {
1924 KdPrint2((PRINT_PREFIX
" Unknown chip\n" ));
1926 VendorID
= 0xffffffff;
1930 if(ChipFlags
& UNIATA_AHCI
) {
1931 /* if BAR(5) is IO it should point to SATA interface registers */
1932 if(!deviceExtension
->BaseIoAHCI_0
.Addr
) {
1933 KdPrint2((PRINT_PREFIX
" !BaseIoAHCI_0, exiting\n" ));
1936 if(c
== CHAN_NOT_SPECIFIED
) {
1937 return UniataAhciInit(HwDeviceExtension
);
1939 if(c
<deviceExtension
->NumberChannels
) {
1940 KdPrint2((PRINT_PREFIX
" AHCI single channel init\n" ));
1941 UniataAhciReset(HwDeviceExtension
, c
);
1944 KdPrint2((PRINT_PREFIX
" AHCI non-existent channel\n" ));
1949 if((WinVer_Id() > WinVer_NT
) &&
1951 deviceExtension
->MasterDev
) {
1952 PCI_COMMON_CONFIG pciData
;
1955 KdPrint2((PRINT_PREFIX
" re-enable IO resources of MasterDev\n" ));
1957 busDataRead
= HalGetBusData
1958 //ScsiPortGetBusData
1960 //HwDeviceExtension,
1961 PCIConfiguration
, SystemIoBusNumber
, slotNumber
,
1962 &pciData
, PCI_COMMON_HDR_LENGTH
);
1963 if(busDataRead
== PCI_COMMON_HDR_LENGTH
) {
1964 UniataEnableIoPCI(SystemIoBusNumber
, slotNumber
, &pciData
);
1966 KdPrint2((PRINT_PREFIX
" re-enable IO resources of MasterDev FAILED\n" ));
1971 // case ATA_ACARD_ID:
1973 case ATA_ACER_LABS_ID
:
1974 if(ChipFlags
& UNIATA_SATA
) {
1975 if(c
== CHAN_NOT_SPECIFIED
) {
1976 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
1977 chan
= &deviceExtension
->chan
[c
];
1978 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
1979 /* the southbridge might need the data corruption fix */
1980 if(RevID
== 0xc2 || RevID
== 0xc3) {
1981 AtapiAliSouthBridgeFixup(HwDeviceExtension
, PCIConfiguration
,
1982 SystemIoBusNumber
, slotNumber
, c
);
1985 /* enable PCI interrupt */
1986 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG
, Command
), (a
& ~0x0400));
1989 if(ChipFlags
& ALINEW
) {
1990 if(c
== CHAN_NOT_SPECIFIED
) {
1991 /* use device interrupt as byte count end */
1992 ChangePciConfig1(0x4a, (a
| 0x20));
1993 /* enable cable detection and UDMA support on newer chips, rev < 0xc7 */
1995 ChangePciConfig1(0x4b, (a
| 0x09));
1998 /* enable ATAPI UDMA mode */
1999 ChangePciConfig1(0x53, (a
| (RevID
>= 0xc7 ? 0x03 : 0x01)));
2002 // check 80-pin cable
2003 generic_cable80(deviceExtension
, channel
, 0x4a, 0);
2006 if(c
== CHAN_NOT_SPECIFIED
) {
2007 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
2008 ChangePciConfig1(0x53, (a
| 0x03));
2011 deviceExtension
->chan
[c
].ChannelCtrlFlags
|= CTRFLAGS_DMA_RO
;
2016 if(c
== CHAN_NOT_SPECIFIED
) {
2017 /* set prefetch, postwrite */
2018 if(ChipFlags
& AMDBUG
) {
2019 ChangePciConfig1(0x41, (a
& 0x0f));
2021 ChangePciConfig1(0x41, (a
| 0xf0));
2024 if(deviceExtension
->MaxTransferMode
< ATA_UDMA2
)
2026 // check 80-pin cable
2027 if(!(ChipFlags
& UNIATA_NO80CHK
)) {
2028 if(c
== CHAN_NOT_SPECIFIED
) {
2031 generic_cable80(deviceExtension
, channel
, 0x42, 0);
2035 case ATA_HIGHPOINT_ID
:
2037 if(c
== CHAN_NOT_SPECIFIED
) {
2039 if(ChipFlags
& HPTOLD
) {
2040 /* turn off interrupt prediction */
2041 ChangePciConfig1(0x51, (a
& ~0x80));
2043 /* turn off interrupt prediction */
2044 ChangePciConfig1(0x51, (a
& ~0x03));
2045 ChangePciConfig1(0x55, (a
& ~0x03));
2046 /* turn on interrupts */
2047 ChangePciConfig1(0x5a, (a
& ~0x10));
2048 /* set clocks etc */
2049 if(ChipType
< HPT372
) {
2050 SetPciConfig1(0x5b, 0x22);
2052 ChangePciConfig1(0x5b, ((a
& 0x01) | 0x20));
2057 // check 80-pin cable
2058 chan
= &deviceExtension
->chan
[c
];
2059 if(!hpt_cable80(deviceExtension
, channel
)) {
2060 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2064 case ATA_INTEL_ID
: {
2067 if(ChipFlags
& UNIATA_SATA
) {
2069 KdPrint2((PRINT_PREFIX
"Intel SATA\n"));
2070 if(ChipFlags
& UNIATA_AHCI
) {
2071 KdPrint2((PRINT_PREFIX
"Do nothing for AHCI\n"));
2072 /* enable PCI interrupt */
2073 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG
, Command
), (a
& ~0x0400));
2076 if(c
== CHAN_NOT_SPECIFIED
) {
2077 KdPrint2((PRINT_PREFIX
"Base init\n"));
2078 /* force all ports active "the legacy way" */
2079 ChangePciConfig2(0x92, (a
| 0x0f));
2081 if(deviceExtension
->BaseIoAddressSATA_0
.Addr
&& (ChipFlags
& ICH7
)) {
2082 /* Set SCRAE bit to enable registers access. */
2083 ChangePciConfig4(0x94, (a
| (1 << 9)));
2084 /* Set Ports Implemented register bits. */
2085 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
), 0x0c,
2086 AtapiReadPortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
), 0x0c) | 0x0f);
2088 /* enable PCI interrupt */
2089 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG
, Command
), (a
& ~0x0400));
2093 KdPrint2((PRINT_PREFIX
"channel init\n"));
2095 GetPciConfig1(0x90, tmp8
);
2096 KdPrint2((PRINT_PREFIX
"reg 90: %x, init lun map\n", tmp8
));
2098 KdPrint2((PRINT_PREFIX
"chan %d\n", c
));
2099 chan
= &deviceExtension
->chan
[c
];
2101 if(ChipFlags
& ICH5
) {
2102 KdPrint2((PRINT_PREFIX
"ICH5\n"));
2103 if ((tmp8
& 0x04) == 0) {
2104 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
2105 chan
->lun
[0]->SATA_lun_map
= (tmp8
& 0x01) ^ c
;
2106 chan
->lun
[1]->SATA_lun_map
= 0;
2107 } else if ((tmp8
& 0x02) == 0) {
2109 chan
->lun
[0]->SATA_lun_map
= (tmp8
& 0x01) ? 1 : 0;
2110 chan
->lun
[1]->SATA_lun_map
= (tmp8
& 0x01) ? 0 : 1;
2113 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2115 } else if ((tmp8
& 0x02) != 0) {
2117 chan
->lun
[0]->SATA_lun_map
= (tmp8
& 0x01) ? 1 : 0;
2118 chan
->lun
[1]->SATA_lun_map
= (tmp8
& 0x01) ? 0 : 1;
2121 //chan->ChannelCtrlFlags |= CTRFLAGS_PATA;
2125 if(ChipFlags
& I6CH2
) {
2126 KdPrint2((PRINT_PREFIX
"I6CH2\n"));
2127 chan
->ChannelCtrlFlags
|= CTRFLAGS_NO_SLAVE
;
2128 chan
->lun
[0]->SATA_lun_map
= c
? 0 : 1;
2129 chan
->lun
[1]->SATA_lun_map
= 0;
2131 KdPrint2((PRINT_PREFIX
"other Intel\n"));
2132 switch(tmp8
& 0x03) {
2134 KdPrint2((PRINT_PREFIX
"0 -> %d/%d\n", 0+c
, 2+c
));
2135 chan
->lun
[0]->SATA_lun_map
= 0+c
;
2136 chan
->lun
[1]->SATA_lun_map
= 2+c
;
2140 KdPrint2((PRINT_PREFIX
"2 -> %d/%d\n", 0, 2));
2141 chan
->lun
[0]->SATA_lun_map
= 0;
2142 chan
->lun
[1]->SATA_lun_map
= 2;
2145 KdPrint2((PRINT_PREFIX
"PATA\n"));
2151 KdPrint2((PRINT_PREFIX
"2 -> %d/%d\n", 1, 3));
2152 chan
->lun
[0]->SATA_lun_map
= 1;
2153 chan
->lun
[1]->SATA_lun_map
= 3;
2156 KdPrint2((PRINT_PREFIX
"PATA\n"));
2164 KdPrint2((PRINT_PREFIX
"PATA part\n"));
2165 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA5
);
2168 if(ChipType
== INTEL_IDX
) {
2169 KdPrint2((PRINT_PREFIX
"io indexed\n"));
2170 //for(c=0; c<deviceExtension->NumberChannels; c++) {
2171 chan
= &deviceExtension
->chan
[c
];
2172 UniataSataWritePort4(chan
, IDX_SATA_SError
, 0xffffffff, 0);
2173 if(!(chan
->ChannelCtrlFlags
& CTRFLAGS_NO_SLAVE
)) {
2174 UniataSataWritePort4(chan
, IDX_SATA_SError
, 0xffffffff, 1);
2182 if(deviceExtension
->MaxTransferMode
<= ATA_UDMA2
)
2184 // check 80-pin cable
2185 if(c
== CHAN_NOT_SPECIFIED
) {
2188 chan
= &deviceExtension
->chan
[c
];
2189 GetPciConfig2(0x54, reg54
);
2190 KdPrint2((PRINT_PREFIX
" intel 80-pin check (reg54=%x)\n", reg54
));
2191 if(deviceExtension
->HwFlags
& UNIATA_NO80CHK
) {
2192 KdPrint2((PRINT_PREFIX
" No check (administrative)\n"));
2193 if(chan
->Force80pin
) {
2194 KdPrint2((PRINT_PREFIX
"Force80pin\n"));
2197 if(reg54
== 0x0000 || reg54
== 0xffff) {
2198 KdPrint2((PRINT_PREFIX
" check failed (not supported)\n"));
2200 if( ((reg54
>> (channel
*2)) & 30) == 0) {
2201 KdPrint2((PRINT_PREFIX
" intel 40-pin\n"));
2202 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2206 case ATA_NVIDIA_ID
: {
2207 if(ChipFlags
& UNIATA_SATA
) {
2208 if(c
== CHAN_NOT_SPECIFIED
) {
2209 ULONG offs
= (ChipFlags
& NV4OFF
) ? 0x0440 : 0x0010;
2210 /* enable control access */
2211 ChangePciConfig1(0x50, (a
| 0x04));
2212 /* MCP55 seems to need some time to allow r_res2 read. */
2213 AtapiStallExecution(10);
2214 KdPrint2((PRINT_PREFIX
"BaseIoAddressSATA_0=%x\n", deviceExtension
->BaseIoAddressSATA_0
.Addr
));
2215 if(ChipFlags
& NVQ
) {
2216 KdPrint2((PRINT_PREFIX
"Disable NCQ\n"));
2217 tmp32
= AtapiReadPortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x0400);
2218 KdPrint2((PRINT_PREFIX
"MODE=%#x\n", tmp32
));
2219 if(tmp32
& ~0xfffffff9) {
2220 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x0400,
2221 tmp32
& 0xfffffff9);
2224 deviceExtension
->HwFlags
= ChipFlags
;
2226 if(ChipFlags
& NVQ
) {
2227 /* disable ECO 398 */
2228 ChangePciConfig1(0x7f, (a
& ~(1 << 7)));
2230 KdPrint2((PRINT_PREFIX
"Enable NCQ\n"));
2231 /* enable NCQ support */
2232 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x0400,
2233 tmp32
| ~0x00000006);
2235 /* clear interrupt status */
2236 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),offs
, 0x00ff00ff);
2237 /* enable device and PHY state change interrupts */
2238 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),offs
+4, 0x000d000d);
2240 /* clear interrupt status */
2241 AtapiWritePortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),offs
, 0xff);
2242 /* enable device and PHY state change interrupts */
2243 AtapiWritePortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),offs
+1, 0xdd);
2245 /* enable PCI interrupt */
2246 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG
, Command
), (a
& ~0x0400));
2248 //UniataSataPhyEnable(HwDeviceExtension, c);
2253 if(c
== CHAN_NOT_SPECIFIED
) {
2254 /* set prefetch, postwrite */
2255 ChangePciConfig1(0x51, (a
& 0x0f));
2257 // check 80-pin cable
2258 generic_cable80(deviceExtension
, channel
, 0x52, 1);
2259 /* chan = &deviceExtension->chan[c];
2260 GetPciConfig1(0x52, reg52);
2261 if( !((reg52 >> (channel*2)) & 0x01)) {
2262 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2267 case ATA_PROMISE_ID
: {
2272 if(c
== CHAN_NOT_SPECIFIED
) {
2273 // ATA_OUTB(ctlr->r_res1, 0x11, ATA_INB(ctlr->r_res1, 0x11) | 0x0a);
2274 AtapiWritePortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11,
2275 AtapiReadPortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x11) | 0x0a );
2279 /* enable burst mode */
2280 // ATA_OUTB(ctlr->r_res1, 0x1f, ATA_INB(ctlr->r_res1, 0x1f) | 0x01);
2281 if(c
== CHAN_NOT_SPECIFIED
) {
2282 AtapiWritePortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x1f,
2283 AtapiReadPortEx1(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),0x1f) | 0x01 );
2285 // check 80-pin cable
2286 chan
= &deviceExtension
->chan
[c
];
2287 GetPciConfig2(0x50, Reg50
);
2288 if(Reg50
& (1 << (channel
+10))) {
2289 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2294 if(c
== CHAN_NOT_SPECIFIED
) {
2297 // check 80-pin cable
2298 chan
= &deviceExtension
->chan
[c
];
2299 AtapiWritePort1(chan
, IDX_BM_DeviceSpecific0
, 0x0b);
2300 if(AtapiReadPort1(chan
, IDX_BM_DeviceSpecific1
) & 0x04) {
2301 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2306 if(c
== CHAN_NOT_SPECIFIED
) {
2307 /* clear SATA status and unmask interrupts */
2308 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
),
2309 (ChipFlags
& PRG2
) ? 0x60 : 0x6c, 0x000000ff);
2310 if(ChipFlags
& UNIATA_SATA
) {
2311 /* enable "long burst length" on gen2 chips */
2312 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), 0x44,
2313 AtapiReadPortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressBM_0
), 0x44) | 0x2000);
2316 chan
= &deviceExtension
->chan
[c
];
2317 AtapiWritePort4(chan
, IDX_BM_Command
,
2318 (AtapiReadPort4(chan
, IDX_BM_Command
) & ~0x00000f8f) | channel
);
2319 AtapiWritePort4(chan
, IDX_BM_DeviceSpecific0
, 0x00000001);
2320 // check 80-pin cable
2321 if(chan
->MaxTransferMode
< ATA_SA150
&&
2322 (AtapiReadPort4(chan
, IDX_BM_Command
) & 0x01000000)) {
2323 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2329 case ATA_SERVERWORKS_ID
:
2330 if(c
== CHAN_NOT_SPECIFIED
) {
2331 if(ChipType
== SWKS33
) {
2332 AtapiRosbSouthBridgeFixup(HwDeviceExtension
, PCIConfiguration
,
2333 SystemIoBusNumber
, slotNumber
);
2335 ChangePciConfig1(0x5a, ((a
& ~0x40) | ((ChipType
== SWKS100
) ? 0x03 : 0x02)));
2340 if(ChipType
== SIIMIO
) {
2341 KdPrint2((PRINT_PREFIX
"ATI New\n"));
2344 KdPrint2((PRINT_PREFIX
"ATI\n"));
2348 case ATA_SILICON_IMAGE_ID
:
2349 /* if(ChipFlags & SIIENINTR) {
2350 SetPciConfig1(0x71, 0x01);
2355 KdPrint2((PRINT_PREFIX
"SII\n"));
2358 if(c
== CHAN_NOT_SPECIFIED
) {
2359 if(ChipFlags
& SIISETCLK
) {
2360 KdPrint2((PRINT_PREFIX
"SIISETCLK\n"));
2361 GetPciConfig1(0x8a, tmp8
);
2362 if ((tmp8
& 0x30) != 0x10)
2363 ChangePciConfig1(0x8a, (a
& 0xcf) | 0x10);
2364 GetPciConfig1(0x8a, tmp8
);
2365 if ((tmp8
& 0x30) != 0x10) {
2366 KdPrint2((PRINT_PREFIX
"Sil 0680 could not set ATA133 clock\n"));
2367 deviceExtension
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA5
);
2371 if(deviceExtension
->MaxTransferMode
< ATA_SA150
) {
2372 // check 80-pin cable
2373 if(c
== CHAN_NOT_SPECIFIED
) {
2376 KdPrint2((PRINT_PREFIX
"Check UDMA66 cable\n"));
2377 chan
= &deviceExtension
->chan
[c
];
2378 GetPciConfig2(0x79, Reg79
);
2379 if(Reg79
& (channel
? 0x02 : 0x01)) {
2380 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2384 ULONG unit01
= (c
& 1);
2385 ULONG unit10
= (c
& 2);
2386 /* enable/disable PHY state change interrupt */
2387 if(c
== CHAN_NOT_SPECIFIED
) {
2388 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
2391 if(ChipFlags
& SIINOSATAIRQ
) {
2392 KdPrint2((PRINT_PREFIX
"Disable broken SATA intr on c=%x\n", c
));
2393 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
), 0x148 + (unit01
<< 7) + (unit10
<< 8),0);
2397 if(ChipFlags
& SIINOSATAIRQ
) {
2398 KdPrint2((PRINT_PREFIX
"Disable broken SATA intr on c=%x\n", c
));
2399 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
), 0x148 + (unit01
<< 7) + (unit10
<< 8),0);
2401 KdPrint2((PRINT_PREFIX
"Enable SATA intr on c=%x\n", c
));
2402 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
), 0x148 + (unit01
<< 7) + (unit10
<< 8),(1 << 16));
2406 if(c
== CHAN_NOT_SPECIFIED
) {
2407 /* enable interrupt as BIOS might not */
2408 ChangePciConfig1(0x8a, (a
& 0x3f));
2409 // Enable 3rd and 4th channels
2410 if (ChipFlags
& SII4CH
) {
2411 KdPrint2((PRINT_PREFIX
"SII4CH\n"));
2412 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x0200, 0x00000002);
2415 chan
= &deviceExtension
->chan
[c
];
2416 /* dont block interrupts */
2417 //ChangePciConfig4(0x48, (a & ~0x03c00000));
2418 /*tmp32 =*/ AtapiReadPortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x48);
2419 AtapiWritePortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x48, (1 << 22) << c
);
2421 /*tmp32 =*/ AtapiReadPortEx4(NULL
, (ULONGIO_PTR
)(&deviceExtension
->BaseIoAddressSATA_0
),0x48);
2423 /* Initialize FIFO PCI bus arbitration */
2424 GetPciConfig1(offsetof(PCI_COMMON_CONFIG
, CacheLineSize
), tmp8
);
2426 KdPrint2((PRINT_PREFIX
"SII: CacheLine=%d\n", tmp8
));
2428 AtapiWritePort2(chan
, IDX_BM_DeviceSpecific1
, ((USHORT
)tmp8
) << 8 | tmp8
);
2430 KdPrint2((PRINT_PREFIX
"SII: CacheLine=0 !!!\n"));
2437 KdPrint2((PRINT_PREFIX
"SII_CMD\n"));
2438 if(c
== CHAN_NOT_SPECIFIED
) {
2439 /* Setup interrupts. */
2440 SetPciConfig1(0x71, 0x01);
2442 /* GetPciConfig1(0x8a, tmp8);
2444 SetPciConfig1(0x71, tmp8);*/
2446 /* Use MEMORY READ LINE for reads.
2447 * NOTE: Although not mentioned in the PCI0646U specs,
2448 * these bits are write only and won't be read
2449 * back as set or not. The PCI0646U2 specs clarify
2453 SetPciConfig1(0x71, tmp8);
2455 /* Set reasonable active/recovery/address-setup values. */
2456 SetPciConfig1(0x53, 0x40);
2457 SetPciConfig1(0x54, 0x3f);
2458 SetPciConfig1(0x55, 0x40);
2459 SetPciConfig1(0x56, 0x3f);
2460 SetPciConfig1(0x57, 0x1c);
2461 SetPciConfig1(0x58, 0x3f);
2462 SetPciConfig1(0x5b, 0x3f);
2467 KdPrint2((PRINT_PREFIX
"ATI700\n"));
2468 if(c
== 0 && !(ChipFlags
& UNIATA_AHCI
)) {
2469 KdPrint2((PRINT_PREFIX
"IXP700 PATA\n"));
2470 chan
= &deviceExtension
->chan
[c
];
2471 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA5
);
2474 } /* switch(ChipType) */
2477 if(c
== CHAN_NOT_SPECIFIED
) {
2483 ChangePciConfig1(0x52, (a
& ~0x04));
2487 ChangePciConfig1(0x49, (a
& ~0x01));
2490 ChangePciConfig2(0x50, (a
| 0x0008));
2491 ChangePciConfig2(0x52, (a
| 0x0008));
2494 ChangePciConfig2(0x04, (a
& ~0x0400));
2498 if(deviceExtension
->HwFlags
& UNIATA_SATA
) {
2499 // do nothing for SATA
2501 if(ChipType
== SIS133NEW
) {
2502 // check 80-pin cable
2503 if(c
== CHAN_NOT_SPECIFIED
) {
2506 chan
= &deviceExtension
->chan
[c
];
2507 GetPciConfig2(channel
? 0x52 : 0x50, tmp16
);
2508 if(tmp16
& 0x8000) {
2509 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2513 // check 80-pin cable
2514 if(c
== CHAN_NOT_SPECIFIED
) {
2517 chan
= &deviceExtension
->chan
[c
];
2518 GetPciConfig1(48, tmp8
);
2519 if(tmp8
& (0x10 << channel
)) {
2520 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2527 /* if(ChipFlags & (UNIATA_SATA | UNIATA_AHCI | VIASATA) {
2530 if(c
== CHAN_NOT_SPECIFIED
) {
2531 /* prepare for ATA-66 on the 82C686a and 82C596b */
2532 if(ChipFlags
& VIACLK
) {
2533 ChangePciConfig4(0x50, (a
| 0x030b030b));
2536 if(ChipFlags
& (UNIATA_SATA
| VIASATA
)) {
2537 /* enable PCI interrupt */
2538 ChangePciConfig2(offsetof(PCI_COMMON_CONFIG
, Command
), (a
& ~0x0400));
2541 * vt6420/1 has problems talking to some drives. The following
2542 * is based on the fix from Joseph Chan <JosephChan@via.com.tw>.
2544 * When host issues HOLD, device may send up to 20DW of data
2545 * before acknowledging it with HOLDA and the host should be
2546 * able to buffer them in FIFO. Unfortunately, some WD drives
2547 * send upto 40DW before acknowledging HOLD and, in the
2548 * default configuration, this ends up overflowing vt6421's
2549 * FIFO, making the controller abort the transaction with
2552 * Rx52[2] is the internal 128DW FIFO Flow control watermark
2553 * adjusting mechanism enable bit and the default value 0
2554 * means host will issue HOLD to device when the left FIFO
2555 * size goes below 32DW. Setting it to 1 makes the watermark
2558 * http://www.reactos.org/bugzilla/show_bug.cgi?id=6500
2561 if(DeviceID
== 0x3149 || DeviceID
== 0x3249) { //vt6420 or vt6421
2562 KdPrint2((PRINT_PREFIX
"VIA 642x FIFO\n"));
2563 ChangePciConfig1(0x52, a
| (1 << 2));
2569 /* the southbridge might need the data corruption fix */
2570 if(ChipFlags
& VIABUG
) {
2571 AtapiViaSouthBridgeFixup(HwDeviceExtension
, PCIConfiguration
,
2572 SystemIoBusNumber
, slotNumber
);
2574 /* set prefetch, postwrite */
2575 if(ChipType
!= VIA133
) {
2576 ChangePciConfig1(0x41, (a
| 0xf0));
2579 /* set fifo configuration half'n'half */
2580 ChangePciConfig1(0x43, ((a
& ((ChipFlags
& VIAPRQ
) ? 0x80 : 0x90)) | 0x2a));
2582 /* set status register read retry */
2583 ChangePciConfig1(0x44, (a
| 0x08));
2585 /* set DMA read & end-of-sector fifo flush */
2586 ChangePciConfig1(0x46, ((a
& 0x0c) | 0xf0));
2588 /* set sector size */
2589 SetPciConfig2(0x60, DEV_BSIZE
);
2590 SetPciConfig2(0x68, DEV_BSIZE
);
2593 chan
= &deviceExtension
->chan
[c
];
2595 if(ChipFlags
& (UNIATA_SATA
| VIASATA
)) {
2596 if((ChipFlags
& VIABAR
) && (c
>= 2)) {
2597 // this is PATA channel
2598 chan
->MaxTransferMode
= ATA_UDMA5
;
2601 UniataSataWritePort4(chan
, IDX_SATA_SError
, 0xffffffff, 0);
2605 // check 80-pin cable
2606 if(!via_cable80(deviceExtension, channel)) {
2607 chan->MaxTransferMode = min(deviceExtension->MaxTransferMode, ATA_UDMA2);
2615 if(ChipType
== ITE_33
|| ChipType
== ITE_133_NEW
) {
2618 if(ChipType
== ITE_133
) {
2619 if(c
== CHAN_NOT_SPECIFIED
) {
2620 /* set PCI mode and 66Mhz reference clock */
2621 ChangePciConfig1(0x50, a
& ~0x83);
2623 /* set default active & recover timings */
2624 SetPciConfig1(0x54, 0x31);
2625 SetPciConfig1(0x56, 0x31);
2627 // check 80-pin cable
2628 GetPciConfig2(0x40, tmp16
);
2629 chan
= &deviceExtension
->chan
[c
];
2630 if(!(tmp16
& (channel
? 0x08 : 0x04))) {
2631 chan
->MaxTransferMode
= min(deviceExtension
->MaxTransferMode
, ATA_UDMA2
);
2635 if(ChipType
== ITE_133_NEW
) {
2639 KdPrint2((PRINT_PREFIX
"Cyrix\n"));
2640 if(ChipType
== CYRIX_OLD
) {
2641 if(c
== CHAN_NOT_SPECIFIED
) {
2642 GetPciConfig1(0x60, tmp8
);
2643 if(!(tmp8
& 0x40)) {
2644 KdPrint2((PRINT_PREFIX
"Enable DMA\n"));
2646 SetPciConfig1(0x60, tmp8
);
2652 if(c
!= CHAN_NOT_SPECIFIED
) {
2653 // We don't know how to check for 80-pin cable on unknown controllers.
2654 // Later we shall check bit in IDENTIFY structure, but it is not reliable way.
2655 // So, leave this flag to use as hint in error recovery procedures
2656 KdPrint2((PRINT_PREFIX
"UNIATA_NO80CHK\n"));
2657 deviceExtension
->HwFlags
|= UNIATA_NO80CHK
;
2662 // In all places separate channels are inited after common controller init
2663 // The only exception is probe. But there we may need info about 40/80 pin and MaxTransferRate
2664 if(CheckCable
&& !(ChipFlags
& (UNIATA_NO80CHK
| UNIATA_SATA
))) {
2665 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
2666 AtapiChipInit(HwDeviceExtension
, DeviceNumber
, c
);
2671 } // end AtapiChipInit()
2676 IN PHW_DEVICE_EXTENSION deviceExtension
,
2677 IN PIDE_BUSMASTER_REGISTERS BaseIoAddressBM_0
,
2685 if(!BaseIoAddressBM_0
) {
2688 for(c
=0; c
<deviceExtension
->NumberChannels
; c
++) {
2689 chan
= &deviceExtension
->chan
[c
];
2690 for (i
=0; i
<IDX_BM_IO_SZ
; i
++) {
2691 UniataInitIoRes(chan
, IDX_BM_IO
+i
, BaseIoAddressBM_0
? ((ULONGIO_PTR
)BaseIoAddressBM_0
+ i
) : 0, MemIo
, FALSE
);
2693 if(BaseIoAddressBM_0
) {
2694 BaseIoAddressBM_0
++;
2698 } // end UniataInitMapBM()
2703 IN PHW_CHANNEL chan
,
2704 IN PIDE_REGISTERS_1 BaseIoAddress1
,
2705 IN PIDE_REGISTERS_2 BaseIoAddress2
2710 for (i
=0; i
<IDX_IO1_SZ
; i
++) {
2711 UniataInitIoRes(chan
, IDX_IO1
+i
, BaseIoAddress1
? ((ULONGIO_PTR
)BaseIoAddress1
+ i
) : 0, FALSE
, FALSE
);
2713 for (i
=0; i
<IDX_IO2_SZ
; i
++) {
2714 UniataInitIoRes(chan
, IDX_IO2
+i
, BaseIoAddress2
? ((ULONGIO_PTR
)BaseIoAddress2
+ i
) : 0, FALSE
, FALSE
);
2716 UniataInitSyncBaseIO(chan
);
2718 } // end UniataInitMapBase()
2722 UniataInitSyncBaseIO(
2726 RtlCopyMemory(&chan
->RegTranslation
[IDX_IO1_o
], &chan
->RegTranslation
[IDX_IO1
], IDX_IO1_SZ
*sizeof(chan
->RegTranslation
[0]));
2727 RtlCopyMemory(&chan
->RegTranslation
[IDX_IO2_o
], &chan
->RegTranslation
[IDX_IO2
], IDX_IO2_SZ
*sizeof(chan
->RegTranslation
[0]));
2729 } // end UniataInitSyncBaseIO()
2733 IN PHW_CHANNEL chan
,
2741 MemIo
= Proc
= FALSE
;
2743 chan
->RegTranslation
[idx
].Addr
= addr
;
2744 chan
->RegTranslation
[idx
].MemIo
= MemIo
;
2745 chan
->RegTranslation
[idx
].Proc
= Proc
;
2746 } // end UniataInitIoRes()
2757 MemIo
= Proc
= FALSE
;
2760 IoRes
->MemIo
= MemIo
;
2762 } // end UniataInitIoResEx()
2767 IN PHW_CHANNEL chan
,
2768 IN PHW_DEVICE_EXTENSION deviceExtension
,
2774 KdPrint2((PRINT_PREFIX
"AtapiSetupLunPtrs for channel %d of %d, %d luns \n", c
, deviceExtension
->NumberChannels
, deviceExtension
->NumberLuns
));
2776 if(!deviceExtension
->NumberLuns
) {
2777 KdPrint2((PRINT_PREFIX
"Achtung !deviceExtension->NumberLuns \n"));
2778 deviceExtension
->NumberLuns
= IDE_MAX_LUN_PER_CHAN
;
2780 KdPrint2((PRINT_PREFIX
" Chan %#x\n", chan
));
2781 chan
->DeviceExtension
= deviceExtension
;
2783 chan
->NumberLuns
= deviceExtension
->NumberLuns
;
2784 for(i
=0; i
<deviceExtension
->NumberLuns
; i
++) {
2785 chan
->lun
[i
] = &(deviceExtension
->lun
[c
*deviceExtension
->NumberLuns
+i
]);
2786 KdPrint2((PRINT_PREFIX
" Lun %#x\n", i
));
2787 KdPrint2((PRINT_PREFIX
" Lun ptr %#x\n", chan
->lun
[i
]));
2789 chan
->AltRegMap
= deviceExtension
->AltRegMap
;
2790 chan
->NextDpcChan
= -1;
2791 chan
->last_devsel
= -1;
2792 for(i
=0; i
<deviceExtension
->NumberLuns
; i
++) {
2793 chan
->lun
[i
]->DeviceExtension
= deviceExtension
;
2794 chan
->lun
[i
]->chan
= chan
;
2795 chan
->lun
[i
]->Lun
= i
;
2797 if((deviceExtension
->HwFlags
& UNIATA_AHCI
) &&
2798 deviceExtension
->AhciInternalAtaReq0
&&
2799 deviceExtension
->AhciInternalSrb0
) {
2800 chan
->AhciInternalAtaReq
= &(deviceExtension
->AhciInternalAtaReq0
[c
]);
2801 chan
->AhciInternalSrb
= &(deviceExtension
->AhciInternalSrb0
[c
]);
2802 UniataAhciSetupCmdPtr(chan
->AhciInternalAtaReq
);
2803 chan
->AhciInternalSrb
->SrbExtension
= chan
->AhciInternalAtaReq
;
2804 chan
->AhciInternalAtaReq
->Srb
= chan
->AhciInternalSrb
;
2807 } // end AtapiSetupLunPtrs()
2811 UniataAllocateLunExt(
2812 PHW_DEVICE_EXTENSION deviceExtension
,
2813 ULONG NewNumberChannels
2816 PHW_LU_EXTENSION old_luns
= NULL
;
2817 PHW_CHANNEL old_chans
= NULL
;
2819 KdPrint2((PRINT_PREFIX
"allocate %d Luns for %d channels\n", deviceExtension
->NumberLuns
, deviceExtension
->NumberChannels
));
2821 old_luns
= deviceExtension
->lun
;
2822 old_chans
= deviceExtension
->chan
;
2824 if(old_luns
|| old_chans
) {
2825 if(NewNumberChannels
== UNIATA_ALLOCATE_NEW_LUNS
) {
2826 KdPrint2((PRINT_PREFIX
"already allocated!\n"));
2831 if(!deviceExtension
->NumberLuns
) {
2832 KdPrint2((PRINT_PREFIX
"default NumberLuns=2\n"));
2833 deviceExtension
->NumberLuns
= 2;
2836 if(deviceExtension
->HwFlags
& UNIATA_AHCI
) {
2837 if(!deviceExtension
->AhciInternalAtaReq0
) {
2838 deviceExtension
->AhciInternalAtaReq0
= (PATA_REQ
)ExAllocatePool(NonPagedPool
, sizeof(ATA_REQ
)*deviceExtension
->NumberChannels
);
2839 if (!deviceExtension
->AhciInternalAtaReq0
) {
2840 KdPrint2((PRINT_PREFIX
"!deviceExtension->AhciInternalAtaReq0 => SP_RETURN_ERROR\n"));
2843 RtlZeroMemory(deviceExtension
->AhciInternalAtaReq0
, sizeof(ATA_REQ
)*deviceExtension
->NumberChannels
);
2845 if(!deviceExtension
->AhciInternalSrb0
) {
2846 deviceExtension
->AhciInternalSrb0
= (PSCSI_REQUEST_BLOCK
)ExAllocatePool(NonPagedPool
, sizeof(SCSI_REQUEST_BLOCK
)*deviceExtension
->NumberChannels
);
2847 if (!deviceExtension
->AhciInternalSrb0
) {
2848 KdPrint2((PRINT_PREFIX
"!deviceExtension->AhciInternalSrb0 => SP_RETURN_ERROR\n"));
2849 UniataFreeLunExt(deviceExtension
);
2852 RtlZeroMemory(deviceExtension
->AhciInternalSrb0
, sizeof(SCSI_REQUEST_BLOCK
)*deviceExtension
->NumberChannels
);
2856 deviceExtension
->lun
= (PHW_LU_EXTENSION
)ExAllocatePool(NonPagedPool
, sizeof(HW_LU_EXTENSION
) * (deviceExtension
->NumberChannels
+1) * deviceExtension
->NumberLuns
);
2857 if (!deviceExtension
->lun
) {
2858 KdPrint2((PRINT_PREFIX
"!deviceExtension->lun => SP_RETURN_ERROR\n"));
2859 UniataFreeLunExt(deviceExtension
);
2862 RtlZeroMemory(deviceExtension
->lun
, sizeof(HW_LU_EXTENSION
) * (deviceExtension
->NumberChannels
+1) * deviceExtension
->NumberLuns
);
2864 deviceExtension
->chan
= (PHW_CHANNEL
)ExAllocatePool(NonPagedPool
, sizeof(HW_CHANNEL
) * (deviceExtension
->NumberChannels
+1));
2865 if (!deviceExtension
->chan
) {
2866 UniataFreeLunExt(deviceExtension
);
2867 KdPrint2((PRINT_PREFIX
"!deviceExtension->chan => SP_RETURN_ERROR\n"));
2870 RtlZeroMemory(deviceExtension
->chan
, sizeof(HW_CHANNEL
) * (deviceExtension
->NumberChannels
+1));
2872 } // end UniataAllocateLunExt()
2877 PHW_DEVICE_EXTENSION deviceExtension
2880 if (deviceExtension
->lun
) {
2881 ExFreePool(deviceExtension
->lun
);
2882 deviceExtension
->lun
= NULL
;
2884 if (deviceExtension
->chan
) {
2885 ExFreePool(deviceExtension
->chan
);
2886 deviceExtension
->chan
= NULL
;
2888 if(deviceExtension
->AhciInternalAtaReq0
) {
2889 ExFreePool(deviceExtension
->AhciInternalAtaReq0
);
2890 deviceExtension
->AhciInternalAtaReq0
= NULL
;
2892 if(deviceExtension
->AhciInternalSrb0
) {
2893 ExFreePool(deviceExtension
->AhciInternalSrb0
);
2894 deviceExtension
->AhciInternalSrb0
= NULL
;
2898 } // end UniataFreeLunExt()