drivers/storage/inc/ide.h

   1 /*++
   2
   3 Copyright (C) Microsoft Corporation, 1999 - 1999
   4
   5 Module Name:
   6
   7     ide.h
   8
   9 Abstract:
  10
  11     These are the structures and defines that are used in the
  12     PCI IDE mini drivers.
  13
  14 Revision History:
  15
  16 --*/
  17
  18
  19 #if !defined (___ide_h___)
  20 #define ___ide_h___
  21
  22 #include "ideuser.h"
  23
  24 #define MAX_IDE_DEVICE      2
  25 #define MAX_IDE_LINE        2
  26 #define MAX_IDE_CHANNEL     2
  27
  28 //
  29 // Some miniports need this structure.
  30 // IdentifyData is passed to the miniport in
  31 // the XfermodeSelect structure
  32 //
  33
  34 //
  35 // IDENTIFY data
  36 //
  37
  38 #pragma pack (1)
  39 typedef struct _IDENTIFY_DATA {
  40     USHORT GeneralConfiguration;            // 00 00
  41     USHORT NumCylinders;                    // 02  1
  42     USHORT Reserved1;                       // 04  2
  43     USHORT NumHeads;                        // 06  3
  44     USHORT UnformattedBytesPerTrack;        // 08  4
  45     USHORT UnformattedBytesPerSector;       // 0A  5
  46     USHORT NumSectorsPerTrack;              // 0C  6
  47     USHORT VendorUnique1[3];                // 0E  7-9
  48     UCHAR  SerialNumber[20];                // 14  10-19
  49     USHORT BufferType;                      // 28  20
  50     USHORT BufferSectorSize;                // 2A  21
  51     USHORT NumberOfEccBytes;                // 2C  22
  52     UCHAR  FirmwareRevision[8];             // 2E  23-26
  53     UCHAR  ModelNumber[40];                 // 36  27-46
  54     UCHAR  MaximumBlockTransfer;            // 5E  47
  55     UCHAR  VendorUnique2;                   // 5F
  56     USHORT DoubleWordIo;                    // 60  48
  57     USHORT Capabilities;                    // 62  49
  58     USHORT Reserved2;                       // 64  50
  59     UCHAR  VendorUnique3;                   // 66  51
  60     UCHAR  PioCycleTimingMode;              // 67
  61     UCHAR  VendorUnique4;                   // 68  52
  62     UCHAR  DmaCycleTimingMode;              // 69
  63     USHORT TranslationFieldsValid:3;        // 6A  53
  64     USHORT Reserved3:13;
  65     USHORT NumberOfCurrentCylinders;        // 6C  54
  66     USHORT NumberOfCurrentHeads;            // 6E  55
  67     USHORT CurrentSectorsPerTrack;          // 70  56
  68     ULONG  CurrentSectorCapacity;           // 72  57-58
  69     USHORT CurrentMultiSectorSetting;       //     59
  70     ULONG  UserAddressableSectors;          //     60-61
  71     USHORT SingleWordDMASupport : 8;        //     62
  72     USHORT SingleWordDMAActive : 8;
  73     USHORT MultiWordDMASupport : 8;         //     63
  74     USHORT MultiWordDMAActive : 8;
  75     USHORT AdvancedPIOModes : 8;            //     64
  76     USHORT Reserved4 : 8;
  77     USHORT MinimumMWXferCycleTime;          //     65
  78     USHORT RecommendedMWXferCycleTime;      //     66
  79     USHORT MinimumPIOCycleTime;             //     67
  80     USHORT MinimumPIOCycleTimeIORDY;        //     68
  81     USHORT Reserved5[11];                   //     69-79
  82     USHORT MajorRevision;                   //     80
  83     USHORT MinorRevision;                   //     81
  84     USHORT Reserved6;                       //     82
  85     USHORT CommandSetSupport;               //     83
  86     USHORT Reserved6a[2];                   //     84-85
  87     USHORT CommandSetActive;                //     86
  88     USHORT Reserved6b;                      //     87
  89     USHORT UltraDMASupport : 8;             //     88
  90     USHORT UltraDMAActive  : 8;             //
  91     USHORT Reserved7[11];                   //     89-99
  92     ULONG  Max48BitLBA[2];                  //     100-103
  93     USHORT Reserved7a[22];                  //     104-125
  94     USHORT LastLun:3;                       //     126
  95     USHORT Reserved8:13;
  96     USHORT MediaStatusNotification:2;       //     127
  97     USHORT Reserved9:6;
  98     USHORT DeviceWriteProtect:1;
  99     USHORT Reserved10:7;
 100     USHORT Reserved11[128];                  //     128-255
 101 } IDENTIFY_DATA, *PIDENTIFY_DATA;
 102
 103 //
 104 // Identify data without the Reserved4.
 105 //
 106
 107 //typedef struct _IDENTIFY_DATA2 {
 108 //    USHORT GeneralConfiguration;            // 00 00
 109 //    USHORT NumCylinders;                    // 02  1
 110 //    USHORT Reserved1;                       // 04  2
 111 //    USHORT NumHeads;                        // 06  3
 112 //    USHORT UnformattedBytesPerTrack;        // 08  4
 113 //    USHORT UnformattedBytesPerSector;       // 0A  5
 114 //    USHORT NumSectorsPerTrack;              // 0C  6
 115 //    USHORT VendorUnique1[3];                // 0E  7-9
 116 //    UCHAR  SerialNumber[20];                // 14  10-19
 117 //    USHORT BufferType;                      // 28  20
 118 //    USHORT BufferSectorSize;                // 2A  21
 119 //    USHORT NumberOfEccBytes;                // 2C  22
 120 //    UCHAR  FirmwareRevision[8];             // 2E  23-26
 121 //    UCHAR  ModelNumber[40];                 // 36  27-46
 122 //    UCHAR  MaximumBlockTransfer;            // 5E  47
 123 //    UCHAR  VendorUnique2;                   // 5F
 124 //    USHORT DoubleWordIo;                    // 60  48
 125 //    USHORT Capabilities;                    // 62  49
 126 //    USHORT Reserved2;                       // 64  50
 127 //    UCHAR  VendorUnique3;                   // 66  51
 128 //    UCHAR  PioCycleTimingMode;              // 67
 129 //    UCHAR  VendorUnique4;                   // 68  52
 130 //    UCHAR  DmaCycleTimingMode;              // 69
 131 //    USHORT TranslationFieldsValid:3;        // 6A  53
 132 //    USHORT Reserved3:13;
 133 //    USHORT NumberOfCurrentCylinders;        // 6C  54
 134 //    USHORT NumberOfCurrentHeads;            // 6E  55
 135 //    USHORT CurrentSectorsPerTrack;          // 70  56
 136 //    ULONG  CurrentSectorCapacity;           // 72  57-58
 137 //    USHORT CurrentMultiSectorSetting;       //     59
 138 //    ULONG  UserAddressableSectors;          //     60-61
 139 //    USHORT SingleWordDMASupport : 8;        //     62
 140 //    USHORT SingleWordDMAActive : 8;
 141 //    USHORT MultiWordDMASupport : 8;         //     63
 142 //    USHORT MultiWordDMAActive : 8;
 143 //    USHORT AdvancedPIOModes : 8;            //     64
 144 //    USHORT Reserved4 : 8;
 145 //    USHORT MinimumMWXferCycleTime;          //     65
 146 //    USHORT RecommendedMWXferCycleTime;      //     66
 147 //    USHORT MinimumPIOCycleTime;             //     67
 148 //    USHORT MinimumPIOCycleTimeIORDY;        //     68
 149 //    USHORT Reserved5[11];                   //     69-79
 150 //    USHORT MajorRevision;                   //     80
 151 //    USHORT MinorRevision;                   //     81
 152 //    USHORT Reserved6[6];                    //     82-87
 153 //    USHORT UltraDMASupport : 8;             //     88
 154 //    USHORT UltraDMAActive  : 8;             //
 155 //    USHORT Reserved7[37];                   //     89-125
 156 //    USHORT LastLun:3;                       //     126
 157 //    USHORT Reserved8:13;
 158 //    USHORT MediaStatusNotification:2;       //     127
 159 //    USHORT Reserved9:6;
 160 //    USHORT DeviceWriteProtect:1;
 161 //    USHORT Reserved10:7;
 162 //} IDENTIFY_DATA2, *PIDENTIFY_DATA2;
 163 #pragma pack ()
 164
 165 #define IDENTIFY_DATA_SIZE sizeof(IDENTIFY_DATA)
 166
 167
 168 //
 169 // The structure is passed to pci ide mini driver
 170 // TransferModeSelect callback for selecting
 171 // proper transfer mode the the devices connected
 172 // to the given IDE channel
 173 //
 174 typedef struct _PCIIDE_TRANSFER_MODE_SELECT {
 175
 176     //
 177     // Input Parameters
 178     //
 179
 180     //
 181     // IDE Channel Number.  0 or 1
 182     //
 183     ULONG   Channel;
 184
 185     //
 186     // Indicate whether devices are present
 187     //
 188     BOOLEAN DevicePresent[MAX_IDE_DEVICE * MAX_IDE_LINE];
 189
 190     //
 191     // Indicate whether devices are ATA harddisk
 192     //
 193     BOOLEAN FixedDisk[MAX_IDE_DEVICE * MAX_IDE_LINE];
 194
 195     //
 196     // Indicate whether devices support IO Ready Line
 197     //
 198     BOOLEAN IoReadySupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
 199
 200     //
 201     // Indicate the data transfer modes devices support
 202     //
 203     ULONG DeviceTransferModeSupported[MAX_IDE_DEVICE * MAX_IDE_LINE];
 204
 205     //
 206     // Indicate devices' best timings for PIO, single word DMA,
 207     // multiword DMA, and Ultra DMA modes
 208     //
 209     ULONG BestPioCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
 210     ULONG BestSwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
 211     ULONG BestMwDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
 212     ULONG BestUDmaCycleTime[MAX_IDE_DEVICE * MAX_IDE_LINE];
 213
 214     //
 215     // Indicate devices' current data transfer modes
 216     //
 217     ULONG DeviceTransferModeCurrent[MAX_IDE_DEVICE * MAX_IDE_LINE];
 218
 219     //
 220     // The user's choice. This will allow pciidex to
 221     // default to a transfer mode indicated by the mini driver
 222     //
 223     ULONG UserChoiceTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE];
 224
 225     //
 226     // This enables UDMA66 on the intel chipsets
 227     //
 228     ULONG EnableUDMA66;
 229
 230     //
 231     //Some miniports need this
 232     // The miniport will save this data in their deviceExtension
 233     //
 234     IDENTIFY_DATA IdentifyData[MAX_IDE_DEVICE];
 235
 236
 237     //
 238     // Output Parameters
 239     //
 240
 241     //
 242     // Indicate devices' data transfer modes chosen by
 243     // the pcii ide mini drive
 244     //
 245     ULONG DeviceTransferModeSelected[MAX_IDE_DEVICE * MAX_IDE_LINE];
 246
 247     //
 248     // Transfermode timings
 249     //
 250     PULONG TransferModeTimingTable;
 251     ULONG   TransferModeTableLength;
 252
 253 } PCIIDE_TRANSFER_MODE_SELECT, *PPCIIDE_TRANSFER_MODE_SELECT;
 254
 255 //
 256 // possible ide channel state
 257 //
 258
 259 typedef enum {
 260     ChannelDisabled = 0,
 261     ChannelEnabled,
 262     ChannelStateUnknown
 263 } IDE_CHANNEL_STATE;
 264
 265
 266 //
 267 // Prototype for different PCI IDE mini driver
 268 // callbacks
 269 //
 270 typedef IDE_CHANNEL_STATE
 271     (*PCIIDE_CHANNEL_ENABLED) (
 272         IN PVOID DeviceExtension,
 273         IN ULONG Channel
 274         );
 275
 276 typedef BOOLEAN
 277     (*PCIIDE_SYNC_ACCESS_REQUIRED) (
 278         IN PVOID DeviceExtension
 279         );
 280
 281 typedef NTSTATUS
 282     (*PCIIDE_TRANSFER_MODE_SELECT_FUNC) (
 283         IN     PVOID                     DeviceExtension,
 284         IN OUT PPCIIDE_TRANSFER_MODE_SELECT TransferModeSelect
 285         );
 286
 287 typedef    ULONG
 288     (*PCIIDE_USEDMA_FUNC)(
 289         IN PVOID deviceExtension,
 290         IN PVOID cdbCmd,
 291         IN UCHAR targetID
 292         );
 293
 294 typedef    NTSTATUS
 295     (*PCIIDE_UDMA_MODES_SUPPORTED) (
 296         IDENTIFY_DATA   IdentifyData,
 297         PULONG          BestXferMode,
 298         PULONG          CurrentMode
 299         );
 300 //
 301 // This structure is for the PCI IDE mini driver to
 302 // return its properties
 303 //
 304 typedef struct _IDE_CONTROLLER_PROPERTIES {
 305
 306     //
 307     // sizeof (IDE_CONTROLLER_PROPERTIES)
 308     //
 309     ULONG Size;
 310
 311     //
 312     // Indicate the amount of memory PCI IDE mini driver
 313     // needs for its private data
 314     //
 315     ULONG ExtensionSize;
 316
 317     //
 318     // Indicate all the data transfer modes the PCI IDE
 319     // controller supports
 320     //
 321     ULONG SupportedTransferMode[MAX_IDE_CHANNEL][MAX_IDE_DEVICE];
 322
 323     //
 324     // callback to query whether a IDE channel is enabled
 325     //
 326     PCIIDE_CHANNEL_ENABLED      PciIdeChannelEnabled;
 327
 328     //
 329     // callback to query whether both IDE channels requires
 330     // synchronized access.  (one channel at a time)
 331     //
 332     PCIIDE_SYNC_ACCESS_REQUIRED PciIdeSyncAccessRequired;
 333
 334     //
 335     // callback to select proper transfer modes for the
 336     // given devices
 337     //
 338     PCIIDE_TRANSFER_MODE_SELECT_FUNC PciIdeTransferModeSelect;
 339
 340     //
 341     // at the end of a ATA data transfer, ignores busmaster
 342     // status active bit.  Normally, it should be FALSE
 343     //
 344     BOOLEAN IgnoreActiveBitForAtaDevice;
 345
 346     //
 347     // always clear the busmaster interrupt on every interrupt
 348     // generated by the device.  Normally, it should be FALSE
 349     //
 350     BOOLEAN AlwaysClearBusMasterInterrupt;
 351
 352     //
 353     // callback to determine whether DMA should be used or not
 354     // called for every IO
 355     //
 356     PCIIDE_USEDMA_FUNC PciIdeUseDma;
 357
 358
 359     //
 360     // if the miniport needs a different alignment
 361     //
 362     ULONG AlignmentRequirement;
 363
 364     ULONG DefaultPIO;
 365
 366     //
 367     // retrieves the supported udma modes from the Identify data
 368     //
 369     PCIIDE_UDMA_MODES_SUPPORTED PciIdeUdmaModesSupported;
 370
 371 } IDE_CONTROLLER_PROPERTIES, *PIDE_CONTROLLER_PROPERTIES;
 372
 373 //
 374 // callback to query PCI IDE controller properties
 375 //
 376 typedef
 377 NTSTATUS (*PCONTROLLER_PROPERTIES) (
 378     IN PVOID                      DeviceExtension,
 379     IN PIDE_CONTROLLER_PROPERTIES ControllerProperties
 380     );
 381
 382
 383 //
 384 // To initialize PCI IDE mini driver
 385 //
 386 NTSTATUS
 387 PciIdeXInitialize(
 388     IN PDRIVER_OBJECT           DriverObject,
 389     IN PUNICODE_STRING          RegistryPath,
 390     IN PCONTROLLER_PROPERTIES   PciIdeGetControllerProperties,
 391     IN ULONG                    ExtensionSize
 392     );
 393
 394 //
 395 // To query PCI IDE config space data
 396 //
 397 NTSTATUS
 398 PciIdeXGetBusData(
 399     IN PVOID DeviceExtension,
 400     IN PVOID Buffer,
 401     IN ULONG ConfigDataOffset,
 402     IN ULONG BufferLength
 403     );
 404
 405 //
 406 // To save PCI IDE config space data
 407 //
 408 NTSTATUS
 409 PciIdeXSetBusData(
 410     IN PVOID DeviceExtension,
 411     IN PVOID Buffer,
 412     IN PVOID DataMask,
 413     IN ULONG ConfigDataOffset,
 414     IN ULONG BufferLength
 415     );
 416
 417
 418 #pragma pack(1)
 419 typedef struct _PCIIDE_CONFIG_HEADER {
 420
 421     USHORT  VendorID;                   // (ro)
 422     USHORT  DeviceID;                   // (ro)
 423
 424     //
 425     //  Command
 426     //
 427     union {
 428
 429         struct {
 430
 431             USHORT  IoAccessEnable:1;           // Device control
 432             USHORT  MemAccessEnable:1;
 433             USHORT  MasterEnable:1;
 434             USHORT  SpecialCycle:1;
 435             USHORT  MemWriteInvalidateEnable:1;
 436             USHORT  VgaPaletteSnoopEnable:1;
 437             USHORT  ParityErrorResponse:1;
 438             USHORT  WaitCycleEnable:1;
 439             USHORT  SystemErrorEnable:1;
 440             USHORT  FastBackToBackEnable:1;
 441             USHORT  CommandReserved:6;
 442         } b;
 443
 444         USHORT w;
 445
 446     } Command;
 447
 448
 449     USHORT  Status;
 450     UCHAR   RevisionID;                 // (ro)
 451
 452     //
 453     //  Program Interface
 454     //
 455     UCHAR   Chan0OpMode:1;
 456     UCHAR   Chan0Programmable:1;
 457     UCHAR   Chan1OpMode:1;
 458     UCHAR   Chan1Programmable:1;
 459     UCHAR   ProgIfReserved:3;
 460     UCHAR   MasterIde:1;
 461
 462     UCHAR   SubClass;                   // (ro)
 463     UCHAR   BaseClass;                  // (ro)
 464     UCHAR   CacheLineSize;              // (ro+)
 465     UCHAR   LatencyTimer;               // (ro+)
 466     UCHAR   HeaderType;                 // (ro)
 467     UCHAR   BIST;                       // Built in self test
 468
 469     struct _PCI_HEADER_TYPE_0 type0;
 470
 471 } PCIIDE_CONFIG_HEADER, *PPCIIDE_CONFIG_HEADER;
 472 #pragma pack()
 473
 474 //
 475 // Debug Print
 476 //
 477 #if DBG
 478
 479 VOID
 480 PciIdeXDebugPrint(
 481     ULONG DebugPrintLevel,
 482     PCCHAR DebugMessage,
 483     ...
 484     );
 485
 486 #define PciIdeXDebugPrint(x)    PciIdeXDebugPrint x
 487
 488 #else
 489
 490 #define PciIdeXDebugPrint(x)
 491
 492 #endif // DBG
 493
 494 #endif // ___ide_h___
 495