22a47e7d527693d4ca29a202b12bf814e2546e3b
[reactos.git] / drivers / storage / storahci / storahci.h
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GNU GPLv2 only as published by the Free Software Foundation
4 * PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
5 * PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
6 */
7
8 #include "miniport.h"
9 #include "storport.h"
10
11 #define AHCI_POOL_TAG 'ahci'
12 #define MAXIMUM_AHCI_PORT_COUNT 12
13
14 // section 3.1.2
15 #define AHCI_Global_HBA_CONTROL_HR (0x1<<0)
16 #define AHCI_Global_HBA_CONTROL_IE (0x1<<1)
17 #define AHCI_Global_HBA_CONTROL_MRSM (0x1<<2)
18 #define AHCI_Global_HBA_CONTROL_AE (0x1<<31)
19
20 //////////////////////////////////////////////////////////////
21 // ---- Support Structures --- //
22 //////////////////////////////////////////////////////////////
23
24 typedef struct _AHCI_FIS_DMA_SETUP
25 {
26 ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
27 // Port multiplier
28 // Reserved
29 // Data transfer direction, 1 - device to host
30 // Interrupt bit
31 // Auto-activate. Specifies if DMA Activate FIS is needed
32 UCHAR Reserved[2]; // Reserved
33 ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
34 ULONG DmaBufferHigh;
35 ULONG Reserved2; //More reserved
36 ULONG DmaBufferOffset; //Byte offset into buffer. First 2 bits must be 0
37 ULONG TranferCount; //Number of bytes to transfer. Bit 0 must be 0
38 ULONG Reserved3; //Reserved
39 } AHCI_FIS_DMA_SETUP;
40
41 typedef struct _AHCI_PIO_SETUP_FIS
42 {
43 UCHAR FisType; //0x5F
44 UCHAR Reserved1 :5;
45 UCHAR D :1; // 1 is write (device to host)
46 UCHAR I :1;
47 UCHAR Reserved2 :1;
48 UCHAR Status;
49 UCHAR Error;
50
51 UCHAR SectorNumber;
52 UCHAR CylLow;
53 UCHAR CylHigh;
54 UCHAR Dev_Head;
55
56 UCHAR SectorNumb_Exp;
57 UCHAR CylLow_Exp;
58 UCHAR CylHigh_Exp;
59 UCHAR Reserved3;
60
61 UCHAR SectorCount;
62 UCHAR SectorCount_Exp;
63 UCHAR Reserved4;
64 UCHAR E_Status;
65
66 USHORT TransferCount;
67 UCHAR Reserved5[2];
68 } AHCI_PIO_SETUP_FIS;
69
70 typedef struct _AHCI_D2H_REGISTER_FIS
71 {
72 UCHAR FisType;
73 UCHAR Reserved1 :6;
74 UCHAR I:1;
75 UCHAR Reserved2 :1;
76 UCHAR Status;
77 UCHAR Error;
78
79 UCHAR SectorNumber;
80 UCHAR CylLow;
81 UCHAR CylHigh;
82 UCHAR Dev_Head;
83
84 UCHAR SectorNum_Exp;
85 UCHAR CylLow_Exp;
86 UCHAR CylHigh_Exp;
87 UCHAR Reserved;
88
89 UCHAR SectorCount;
90 UCHAR SectorCount_Exp;
91 UCHAR Reserved3[2];
92
93 UCHAR Reserved4[4];
94 } AHCI_D2H_REGISTER_FIS;
95
96 typedef struct _AHCI_SET_DEVICE_BITS_FIS
97 {
98 UCHAR FisType;
99
100 UCHAR PMPort: 4;
101 UCHAR Reserved1 :2;
102 UCHAR I :1;
103 UCHAR N :1;
104
105 UCHAR Status_Lo :3;
106 UCHAR Reserved2 :1;
107 UCHAR Status_Hi :3;
108 UCHAR Reserved3 :1;
109
110 UCHAR Error;
111
112 UCHAR Reserved5[4];
113 } AHCI_SET_DEVICE_BITS_FIS;
114
115 //////////////////////////////////////////////////////////////
116 // --------------------------- //
117 //////////////////////////////////////////////////////////////
118
119 // 4.2.2 Command Header
120 typedef struct _AHCI_COMMAND_HEADER
121 {
122 ULONG HEADER_DESCRIPTION; // DW 0
123 ULONG PRDBC; // DW 1
124 ULONG CTBA0; // DW 2
125 ULONG CTBA_U0; // DW 3
126 ULONG Reserved[4]; // DW 4-7
127 } AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
128
129 // Received FIS
130 typedef struct _AHCI_RECEIVED_FIS
131 {
132 struct _AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
133 ULONG pad0; // 4 BYTE padding
134 struct _AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
135 ULONG pad1[3]; // 12 BYTE padding
136 struct _AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
137 ULONG pad2; // 4 BYTE padding
138 struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
139 ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
140 ULONG Reserved[24]; // 0xA0 -- Reserved
141 } AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
142
143 // Holds Port Information
144 typedef struct _AHCI_PORT
145 {
146 ULONG CLB; // 0x00, command list base address, 1K-byte aligned
147 ULONG CLBU; // 0x04, command list base address upper 32 bits
148 ULONG FB; // 0x08, FIS base address, 256-byte aligned
149 ULONG FBU; // 0x0C, FIS base address upper 32 bits
150 ULONG IS; // 0x10, interrupt status
151 ULONG IE; // 0x14, interrupt enable
152 ULONG CMD; // 0x18, command and status
153 ULONG RSV0; // 0x1C, Reserved
154 ULONG TFD; // 0x20, task file data
155 ULONG SIG; // 0x24, signature
156 ULONG SSTS; // 0x28, SATA status (SCR0:SStatus)
157 ULONG SCTL; // 0x2C, SATA control (SCR2:SControl)
158 ULONG SERR; // 0x30, SATA error (SCR1:SError)
159 ULONG SACT; // 0x34, SATA active (SCR3:SActive)
160 ULONG CI; // 0x38, command issue
161 ULONG SNTF; // 0x3C, SATA notification (SCR4:SNotification)
162 ULONG FBS; // 0x40, FIS-based switch control
163 ULONG RSV1[11]; // 0x44 ~ 0x6F, Reserved
164 ULONG Vendor[4]; // 0x70 ~ 0x7F, vendor specific
165 } AHCI_PORT, *PAHCI_PORT;
166
167 typedef struct _AHCI_MEMORY_REGISTERS
168 {
169 // 0x00 - 0x2B, Generic Host Control
170 ULONG CAP; // 0x00, Host capability
171 ULONG GHC; // 0x04, Global host control
172 ULONG IS; // 0x08, Interrupt status
173 ULONG PI; // 0x0C, Port implemented
174 ULONG VS; // 0x10, Version
175 ULONG CCC_CTL; // 0x14, Command completion coalescing control
176 ULONG CCC_PTS; // 0x18, Command completion coalescing ports
177 ULONG EM_LOC; // 0x1C, Enclosure management location
178 ULONG EM_CTL; // 0x20, Enclosure management control
179 ULONG CAP2; // 0x24, Host capabilities extended
180 ULONG BOHC; // 0x28, BIOS/OS handoff control and status
181 ULONG Reserved[0xA0-0x2C]; // 0x2C - 0x9F, Reserved
182 ULONG VendorSpecific[0x100-0xA0]; // 0xA0 - 0xFF, Vendor specific registers
183 AHCI_PORT PortList[MAXIMUM_AHCI_PORT_COUNT];
184
185 } AHCI_MEMORY_REGISTERS, *PAHCI_MEMORY_REGISTERS;
186
187 // Holds information for each attached attached port to a given adapter.
188 typedef struct _AHCI_PORT_EXTENSION
189 {
190 ULONG PortNumber;
191 BOOLEAN IsActive;
192 PAHCI_PORT Port; // AHCI Port Infomation
193 PAHCI_RECEIVED_FIS ReceivedFIS;
194 PAHCI_COMMAND_HEADER CommandList;
195 STOR_DEVICE_POWER_STATE DevicePowerState; // Device Power State
196 struct _AHCI_ADAPTER_EXTENSION* AdapterExtension; // Port's Adapter Information
197 } AHCI_PORT_EXTENSION, *PAHCI_PORT_EXTENSION;
198
199 // Holds Adapter Information
200 typedef struct _AHCI_ADAPTER_EXTENSION
201 {
202 ULONG SystemIoBusNumber;
203 ULONG SlotNumber;
204 ULONG AhciBaseAddress;
205 PULONG IS;// Interrupt Status, In case of MSIM == `1`
206 ULONG PortImplemented;// bit-mapping of ports which are implemented
207
208 USHORT VendorID;
209 USHORT DeviceID;
210 USHORT RevisionID;
211
212 ULONG Version;
213 ULONG CAP;
214 ULONG CAP2;
215
216 PVOID NonCachedExtension;// holds virtual address to noncached buffer allocated for Port Extension
217
218 struct
219 {
220 // Message per port or shared port?
221 ULONG MessagePerPort : 1;
222 ULONG Removed : 1;
223 ULONG Reserved : 30; // not in use -- maintain 4 byte alignment
224 } StateFlags;
225
226 PAHCI_MEMORY_REGISTERS ABAR_Address;
227 AHCI_PORT_EXTENSION PortExtension[MAXIMUM_AHCI_PORT_COUNT];
228 } AHCI_ADAPTER_EXTENSION, *PAHCI_ADAPTER_EXTENSION;
229
230 typedef struct _AHCI_SRB_EXTENSION
231 {
232 ULONG Reserved[4];
233 } AHCI_SRB_EXTENSION;