2 * PROJECT: ReactOS Kernel
3 * LICENSE: GNU GPLv2 only as published by the Free Software Foundation
4 * PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
5 * PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
13 #pragma warning(disable:4214) // bit field types other than int
14 #pragma warning(disable:4201) // nameless struct/union
16 #define MAXIMUM_AHCI_PORT_COUNT 32
17 #define MAXIMUM_AHCI_PRDT_ENTRIES 32
18 #define MAXIMUM_AHCI_PORT_NCS 30
19 #define MAXIMUM_QUEUE_BUFFER_SIZE 255
20 #define MAXIMUM_TRANSFER_LENGTH (128*1024) // 128 KB
22 #define DEVICE_ATA_BLOCK_SIZE 512
24 // device type (DeviceParams)
25 #define AHCI_DEVICE_TYPE_ATA 1
26 #define AHCI_DEVICE_TYPE_ATAPI 2
27 #define AHCI_DEVICE_TYPE_NODEVICE 3
30 #define AHCI_Global_HBA_CAP_S64A (1 << 31)
32 // FIS Types : http://wiki.osdev.org/AHCI
33 #define FIS_TYPE_REG_H2D 0x27 // Register FIS - host to device
34 #define FIS_TYPE_REG_D2H 0x34 // Register FIS - device to host
35 #define FIS_TYPE_DMA_ACT 0x39 // DMA activate FIS - device to host
36 #define FIS_TYPE_DMA_SETUP 0x41 // DMA setup FIS - bidirectional
37 #define FIS_TYPE_BIST 0x58 // BIST activate FIS - bidirectional
38 #define FIS_TYPE_PIO_SETUP 0x5F // PIO setup FIS - device to host
39 #define FIS_TYPE_DEV_BITS 0xA1 // Set device bits FIS - device to host
41 #define AHCI_ATA_CFIS_FisType 0
42 #define AHCI_ATA_CFIS_PMPort_C 1
43 #define AHCI_ATA_CFIS_CommandReg 2
44 #define AHCI_ATA_CFIS_FeaturesLow 3
45 #define AHCI_ATA_CFIS_LBA0 4
46 #define AHCI_ATA_CFIS_LBA1 5
47 #define AHCI_ATA_CFIS_LBA2 6
48 #define AHCI_ATA_CFIS_Device 7
49 #define AHCI_ATA_CFIS_LBA3 8
50 #define AHCI_ATA_CFIS_LBA4 9
51 #define AHCI_ATA_CFIS_LBA5 10
52 #define AHCI_ATA_CFIS_FeaturesHigh 11
53 #define AHCI_ATA_CFIS_SectorCountLow 12
54 #define AHCI_ATA_CFIS_SectorCountHigh 13
57 #define ATA_FUNCTION_ATA_COMMAND 0x100
58 #define ATA_FUNCTION_ATA_IDENTIFY 0x101
59 #define ATA_FUNCTION_ATA_READ 0x102
62 #define ATA_FUNCTION_ATAPI_COMMAND 0x200
65 #define ATA_FLAGS_DATA_IN (1 << 1)
66 #define ATA_FLAGS_DATA_OUT (1 << 2)
67 #define ATA_FLAGS_48BIT_COMMAND (1 << 3)
68 #define ATA_FLAGS_USE_DMA (1 << 4)
70 #define IsAtaCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATA_COMMAND)
71 #define IsAtapiCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATAPI_COMMAND)
72 #define IsDataTransferNeeded(SrbExtension) (SrbExtension->Flags & (ATA_FLAGS_DATA_IN | ATA_FLAGS_DATA_OUT))
73 #define IsAdapterCAPS64(CAP) (CAP & AHCI_Global_HBA_CAP_S64A)
75 // 3.1.1 NCS = CAP[12:08] -> Align
76 #define AHCI_Global_Port_CAP_NCS(x) (((x) & 0xF00) >> 8)
78 #define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
79 #define AhciDebugPrint(format, ...) StorPortDebugPrint(0, format, __VA_ARGS__)
83 (*PAHCI_COMPLETION_ROUTINE
) (
84 __in PVOID PortExtension
,
88 //////////////////////////////////////////////////////////////
89 // ---- Support Structures --- //
90 //////////////////////////////////////////////////////////////
93 typedef union _AHCI_INTERRUPT_STATUS
97 ULONG DHRS
:1; //Device to Host Register FIS Interrupt
98 ULONG PSS
:1; //PIO Setup FIS Interrupt
99 ULONG DSS
:1; //DMA Setup FIS Interrupt
100 ULONG SDBS
:1; //Set Device Bits Interrupt
101 ULONG UFS
:1; //Unknown FIS Interrupt
102 ULONG DPS
:1; //Descriptor Processed
103 ULONG PCS
:1; //Port Connect Change Status
104 ULONG DMPS
:1; //Device Mechanical Presence Status (DMPS)
106 ULONG PRCS
:1; //PhyRdy Change Status
107 ULONG IPMS
:1; //Incorrect Port Multiplier Status
108 ULONG OFS
:1; //Overflow Status
110 ULONG INFS
:1; //Interface Non-fatal Error Status
111 ULONG IFS
:1; //Interface Fatal Error Status
112 ULONG HBDS
:1; //Host Bus Data Error Status
113 ULONG HBFS
:1; //Host Bus Fatal Error Status
114 ULONG TFES
:1; //Task File Error Status
115 ULONG CPDS
:1; //Cold Port Detect Status
119 } AHCI_INTERRUPT_STATUS
;
121 typedef struct _AHCI_FIS_DMA_SETUP
123 ULONG ULONG0_1
; // FIS_TYPE_DMA_SETUP
126 // Data transfer direction, 1 - device to host
128 // Auto-activate. Specifies if DMA Activate FIS is needed
129 UCHAR Reserved
[2]; // Reserved
130 ULONG DmaBufferLow
; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
132 ULONG Reserved2
; // More reserved
133 ULONG DmaBufferOffset
; // Byte offset into buffer. First 2 bits must be 0
134 ULONG TranferCount
; // Number of bytes to transfer. Bit 0 must be 0
135 ULONG Reserved3
; // Reserved
136 } AHCI_FIS_DMA_SETUP
;
138 typedef struct _AHCI_PIO_SETUP_FIS
153 UCHAR SectorNumb_Exp
;
159 UCHAR SectorCount_Exp
;
163 USHORT TransferCount
;
165 } AHCI_PIO_SETUP_FIS
;
167 typedef struct _AHCI_D2H_REGISTER_FIS
187 UCHAR SectorCount_Exp
;
191 } AHCI_D2H_REGISTER_FIS
;
193 typedef struct _AHCI_SET_DEVICE_BITS_FIS
210 } AHCI_SET_DEVICE_BITS_FIS
;
212 typedef struct _AHCI_QUEUE
214 PVOID Buffer
[MAXIMUM_QUEUE_BUFFER_SIZE
]; // because Storahci hold Srb queue of 255 size
217 } AHCI_QUEUE
, *PAHCI_QUEUE
;
219 //////////////////////////////////////////////////////////////
220 // --------------------------- //
221 //////////////////////////////////////////////////////////////
223 typedef union _AHCI_COMMAND_HEADER_DESCRIPTION
227 ULONG CFL
: 5; // Command FIS Length
228 ULONG A
: 1; // IsATAPI
229 ULONG W
: 1; // Write
230 ULONG P
: 1; // Prefetchable
232 ULONG R
: 1; // Reset
234 ULONG C
: 1; //Clear Busy upon R_OK
236 ULONG PMP
: 4; //Port Multiplier Port
238 ULONG PRDTL
: 16; //Physical Region Descriptor Table Length
242 } AHCI_COMMAND_HEADER_DESCRIPTION
;
244 typedef union _AHCI_GHC
259 typedef union _AHCI_PORT_CMD
291 typedef union _AHCI_SERIAL_ATA_CONTROL
300 ULONG DW11_Reserved
:12;
304 } AHCI_SERIAL_ATA_CONTROL
;
306 typedef union _AHCI_SERIAL_ATA_STATUS
317 } AHCI_SERIAL_ATA_STATUS
;
319 typedef union _AHCI_TASK_FILE_DATA
336 } AHCI_TASK_FILE_DATA
;
338 typedef struct _AHCI_PRDT
347 } AHCI_PRDT
, *PAHCI_PRDT
;
349 // 4.2.3 Command Table
350 typedef struct _AHCI_COMMAND_TABLE
352 // (16 * 32) + 64 + 16 + 48 = 648
353 // 128 byte aligned :D
357 AHCI_PRDT PRDT
[MAXIMUM_AHCI_PRDT_ENTRIES
];
358 } AHCI_COMMAND_TABLE
, *PAHCI_COMMAND_TABLE
;
360 // 4.2.2 Command Header
361 typedef struct _AHCI_COMMAND_HEADER
363 AHCI_COMMAND_HEADER_DESCRIPTION DI
; // DW 0
366 ULONG CTBA_U
; // DW 3
367 ULONG Reserved
[4]; // DW 4-7
368 } AHCI_COMMAND_HEADER
, *PAHCI_COMMAND_HEADER
;
371 typedef struct _AHCI_RECEIVED_FIS
373 struct _AHCI_FIS_DMA_SETUP DmaSetupFIS
; // 0x00 -- DMA Setup FIS
374 ULONG pad0
; // 4 BYTE padding
375 struct _AHCI_PIO_SETUP_FIS PioSetupFIS
; // 0x20 -- PIO Setup FIS
376 ULONG pad1
[3]; // 12 BYTE padding
377 struct _AHCI_D2H_REGISTER_FIS RegisterFIS
; // 0x40 -- Register – Device to Host FIS
378 ULONG pad2
; // 4 BYTE padding
379 struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS
; // 0x58 -- Set Device Bit FIS
380 ULONG UnknowFIS
[16]; // 0x60 -- Unknown FIS
381 ULONG Reserved
[24]; // 0xA0 -- Reserved
382 } AHCI_RECEIVED_FIS
, *PAHCI_RECEIVED_FIS
;
384 // Holds Port Information
385 typedef struct _AHCI_PORT
387 ULONG CLB
; // 0x00, command list base address, 1K-byte aligned
388 ULONG CLBU
; // 0x04, command list base address upper 32 bits
389 ULONG FB
; // 0x08, FIS base address, 256-byte aligned
390 ULONG FBU
; // 0x0C, FIS base address upper 32 bits
391 ULONG IS
; // 0x10, interrupt status
392 ULONG IE
; // 0x14, interrupt enable
393 ULONG CMD
; // 0x18, command and status
394 ULONG RSV0
; // 0x1C, Reserved
395 ULONG TFD
; // 0x20, task file data
396 ULONG SIG
; // 0x24, signature
397 ULONG SSTS
; // 0x28, SATA status (SCR0:SStatus)
398 ULONG SCTL
; // 0x2C, SATA control (SCR2:SControl)
399 ULONG SERR
; // 0x30, SATA error (SCR1:SError)
400 ULONG SACT
; // 0x34, SATA active (SCR3:SActive)
401 ULONG CI
; // 0x38, command issue
402 ULONG SNTF
; // 0x3C, SATA notification (SCR4:SNotification)
403 ULONG FBS
; // 0x40, FIS-based switch control
404 ULONG RSV1
[11]; // 0x44 ~ 0x6F, Reserved
405 ULONG Vendor
[4]; // 0x70 ~ 0x7F, vendor specific
406 } AHCI_PORT
, *PAHCI_PORT
;
408 typedef union _AHCI_INTERRUPT_ENABLE
420 ULONG DW5_Reserved
:14;
424 ULONG DW5_Reserved2
:1;
434 } AHCI_INTERRUPT_ENABLE
;
436 typedef struct _AHCI_MEMORY_REGISTERS
438 // 0x00 - 0x2B, Generic Host Control
439 ULONG CAP
; // 0x00, Host capability
440 ULONG GHC
; // 0x04, Global host control
441 ULONG IS
; // 0x08, Interrupt status
442 ULONG PI
; // 0x0C, Port implemented
443 ULONG VS
; // 0x10, Version
444 ULONG CCC_CTL
; // 0x14, Command completion coalescing control
445 ULONG CCC_PTS
; // 0x18, Command completion coalescing ports
446 ULONG EM_LOC
; // 0x1C, Enclosure management location
447 ULONG EM_CTL
; // 0x20, Enclosure management control
448 ULONG CAP2
; // 0x24, Host capabilities extended
449 ULONG BOHC
; // 0x28, BIOS/OS handoff control and status
450 ULONG Reserved
[0x1d]; // 0x2C - 0x9F, Reserved
451 ULONG VendorSpecific
[0x18]; // 0xA0 - 0xFF, Vendor specific registers
452 AHCI_PORT PortList
[MAXIMUM_AHCI_PORT_COUNT
];
453 } AHCI_MEMORY_REGISTERS
, *PAHCI_MEMORY_REGISTERS
;
455 // Holds information for each attached attached port to a given adapter.
456 typedef struct _AHCI_PORT_EXTENSION
459 ULONG QueueSlots
; // slots which we have already assigned task (Slot)
460 ULONG CommandIssuedSlots
; // slots which has been programmed
461 ULONG MaxPortQueueDepth
;
465 UCHAR RemovableDevice
;
470 LARGE_INTEGER MaxLba
;
471 ULONG BytesPerLogicalSector
;
472 ULONG BytesPerPhysicalSector
;
475 UCHAR SerialNumber
[21];
478 STOR_DPC CommandCompletion
;
479 PAHCI_PORT Port
; // AHCI Port Infomation
480 AHCI_QUEUE SrbQueue
; // pending Srbs
481 AHCI_QUEUE CompletionQueue
;
482 PSCSI_REQUEST_BLOCK Slot
[MAXIMUM_AHCI_PORT_NCS
]; // Srbs which has been alloted a port
483 PAHCI_RECEIVED_FIS ReceivedFIS
;
484 PAHCI_COMMAND_HEADER CommandList
;
485 STOR_DEVICE_POWER_STATE DevicePowerState
; // Device Power State
486 PIDENTIFY_DEVICE_DATA IdentifyDeviceData
;
487 STOR_PHYSICAL_ADDRESS IdentifyDeviceDataPhysicalAddress
;
488 struct _AHCI_ADAPTER_EXTENSION
* AdapterExtension
; // Port's Adapter Information
489 } AHCI_PORT_EXTENSION
, *PAHCI_PORT_EXTENSION
;
491 // Holds Adapter Information
492 typedef struct _AHCI_ADAPTER_EXTENSION
494 ULONG SystemIoBusNumber
;
496 ULONG AhciBaseAddress
;
497 PULONG IS
;// Interrupt Status, In case of MSIM == `1`
498 ULONG PortImplemented
;// bit-mapping of ports which are implemented
508 ULONG LastInterruptPort
;
509 ULONG CurrentCommandSlot
;
511 PVOID NonCachedExtension
; // holds virtual address to noncached buffer allocated for Port Extension
515 // Message per port or shared port?
516 ULONG MessagePerPort
: 1;
518 ULONG Reserved
: 30; // not in use -- maintain 4 byte alignment
521 PAHCI_MEMORY_REGISTERS ABAR_Address
;
522 AHCI_PORT_EXTENSION PortExtension
[MAXIMUM_AHCI_PORT_COUNT
];
523 } AHCI_ADAPTER_EXTENSION
, *PAHCI_ADAPTER_EXTENSION
;
525 typedef struct _LOCAL_SCATTER_GATHER_LIST
527 ULONG NumberOfElements
;
529 STOR_SCATTER_GATHER_ELEMENT List
[MAXIMUM_AHCI_PRDT_ENTRIES
];
530 } LOCAL_SCATTER_GATHER_LIST
, *PLOCAL_SCATTER_GATHER_LIST
;
532 typedef struct _AHCI_SRB_EXTENSION
534 AHCI_COMMAND_TABLE CommandTable
;
549 UCHAR SectorCountLow
;
550 UCHAR SectorCountHigh
;
553 LOCAL_SCATTER_GATHER_LIST Sgl
;
554 PLOCAL_SCATTER_GATHER_LIST pSgl
;
555 PAHCI_COMPLETION_ROUTINE CompletionRoutine
;
557 // for alignment purpose -- 128 byte alignment
558 // do not try to access (R/W) this field
560 } AHCI_SRB_EXTENSION
, *PAHCI_SRB_EXTENSION
;
562 //////////////////////////////////////////////////////////////
564 //////////////////////////////////////////////////////////////
568 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
570 __in PSCSI_REQUEST_BLOCK Srb
575 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
582 __in ULONG BufferSize
588 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
592 UCHAR
DeviceRequestSense (
593 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
594 __in PSCSI_REQUEST_BLOCK Srb
,
598 UCHAR
DeviceRequestReadWrite (
599 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
600 __in PSCSI_REQUEST_BLOCK Srb
,
604 UCHAR
DeviceRequestCapacity (
605 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
606 __in PSCSI_REQUEST_BLOCK Srb
,
611 DeviceInquiryRequest (
612 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
613 __in PSCSI_REQUEST_BLOCK Srb
,
617 UCHAR
DeviceRequestComplete (
618 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
619 __in PSCSI_REQUEST_BLOCK Srb
,
623 UCHAR
DeviceReportLuns (
624 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
625 __in PSCSI_REQUEST_BLOCK Srb
,
632 __inout PAHCI_QUEUE Queue
,
639 __inout PAHCI_QUEUE Queue
645 __in PSCSI_REQUEST_BLOCK Srb
655 //////////////////////////////////////////////////////////////
657 //////////////////////////////////////////////////////////////
659 // I assert every silly mistake I can do while coding
660 // because god never help me debugging the code
661 // but these asserts do :')
663 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, CAP
) == 0x00);
664 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, GHC
) == 0x04);
665 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, IS
) == 0x08);
666 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, PI
) == 0x0C);
667 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, VS
) == 0x10);
668 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, CCC_CTL
) == 0x14);
669 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, CCC_PTS
) == 0x18);
670 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, EM_LOC
) == 0x1C);
671 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, EM_CTL
) == 0x20);
672 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, CAP2
) == 0x24);
673 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, BOHC
) == 0x28);
674 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, Reserved
) == 0x2C);
675 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, VendorSpecific
) == 0xA0);
676 C_ASSERT(FIELD_OFFSET(AHCI_MEMORY_REGISTERS
, PortList
) == 0x100);
678 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, CLB
) == 0x00);
679 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, CLBU
) == 0x04);
680 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, FB
) == 0x08);
681 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, FBU
) == 0x0C);
682 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, IS
) == 0x10);
683 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, IE
) == 0x14);
684 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, CMD
) == 0x18);
685 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, RSV0
) == 0x1C);
686 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, TFD
) == 0x20);
687 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, SIG
) == 0x24);
688 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, SSTS
) == 0x28);
689 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, SCTL
) == 0x2C);
690 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, SERR
) == 0x30);
691 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, SACT
) == 0x34);
692 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, CI
) == 0x38);
693 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, SNTF
) == 0x3C);
694 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, FBS
) == 0x40);
695 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, RSV1
) == 0x44);
696 C_ASSERT(FIELD_OFFSET(AHCI_PORT
, Vendor
) == 0x70);
698 C_ASSERT((sizeof(AHCI_COMMAND_TABLE
) % 128) == 0);
700 C_ASSERT(sizeof(AHCI_GHC
) == sizeof(ULONG
));
701 C_ASSERT(sizeof(AHCI_PORT_CMD
) == sizeof(ULONG
));
702 C_ASSERT(sizeof(AHCI_TASK_FILE_DATA
) == sizeof(ULONG
));
703 C_ASSERT(sizeof(AHCI_INTERRUPT_ENABLE
) == sizeof(ULONG
));
704 C_ASSERT(sizeof(AHCI_SERIAL_ATA_STATUS
) == sizeof(ULONG
));
705 C_ASSERT(sizeof(AHCI_SERIAL_ATA_CONTROL
) == sizeof(ULONG
));
706 C_ASSERT(sizeof(AHCI_COMMAND_HEADER_DESCRIPTION
) == sizeof(ULONG
));
708 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE
, CFIS
) == 0x00);
709 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE
, ACMD
) == 0x40);
710 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE
, RSV0
) == 0x50);
711 C_ASSERT(FIELD_OFFSET(AHCI_COMMAND_TABLE
, PRDT
) == 0x80);