2 * PROJECT: ReactOS Kernel
3 * LICENSE: GNU GPLv2 only as published by the Free Software Foundation
4 * PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
5 * PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
14 #define MAXIMUM_AHCI_PORT_COUNT 25
15 #define MAXIMUM_AHCI_PRDT_ENTRIES 32
16 #define MAXIMUM_QUEUE_BUFFER_SIZE 255
17 #define MAXIMUM_TRANSFER_LENGTH (128*1024) // 128 KB
20 #define AHCI_Global_HBA_CONTROL_HR (1 << 0)
21 #define AHCI_Global_HBA_CONTROL_IE (1 << 1)
22 #define AHCI_Global_HBA_CONTROL_MRSM (1 << 2)
23 #define AHCI_Global_HBA_CONTROL_AE (1 << 31)
24 #define AHCI_Global_HBA_CAP_S64A (1 << 31)
26 #define AHCI_ATA_CFIS_FisType 0
27 #define AHCI_ATA_CFIS_PMPort_C 1
28 #define AHCI_ATA_CFIS_CommandReg 2
29 #define AHCI_ATA_CFIS_FeaturesLow 3
30 #define AHCI_ATA_CFIS_LBA0 4
31 #define AHCI_ATA_CFIS_LBA1 5
32 #define AHCI_ATA_CFIS_LBA2 6
33 #define AHCI_ATA_CFIS_Device 7
34 #define AHCI_ATA_CFIS_LBA3 8
35 #define AHCI_ATA_CFIS_LBA4 9
36 #define AHCI_ATA_CFIS_LBA5 10
37 #define AHCI_ATA_CFIS_FeaturesHigh 11
38 #define AHCI_ATA_CFIS_SectorCountLow 12
39 #define AHCI_ATA_CFIS_SectorCountHigh 13
42 #define ATA_FUNCTION_ATA_COMMAND 0x100
43 #define ATA_FUNCTION_ATA_IDENTIFY 0x101
46 #define ATA_FUNCTION_ATAPI_COMMAND 0x200
49 #define ATA_FLAGS_DATA_IN (1 << 1)
50 #define ATA_FLAGS_DATA_OUT (1 << 2)
52 #define IsAtaCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATA_COMMAND)
53 #define IsAtapiCommand(AtaFunction) (AtaFunction & ATA_FUNCTION_ATAPI_COMMAND)
54 #define IsDataTransferNeeded(SrbExtension) (SrbExtension->Flags & (ATA_FLAGS_DATA_IN | ATA_FLAGS_DATA_OUT))
55 #define IsAdapterCAPS64(CAP) (CAP & AHCI_Global_HBA_CAP_S64A)
57 // 3.1.1 NCS = CAP[12:08] -> Align
58 #define AHCI_Global_Port_CAP_NCS(x) (((x) & 0xF00) >> 8)
60 #define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
62 #define DebugPrint(format, ...) StorPortDebugPrint(0, format, __VA_ARGS__)
65 //////////////////////////////////////////////////////////////
66 // ---- Support Structures --- //
67 //////////////////////////////////////////////////////////////
70 typedef union _AHCI_INTERRUPT_STATUS
74 ULONG DHRS
:1; //Device to Host Register FIS Interrupt
75 ULONG PSS
:1; //PIO Setup FIS Interrupt
76 ULONG DSS
:1; //DMA Setup FIS Interrupt
77 ULONG SDBS
:1; //Set Device Bits Interrupt
78 ULONG UFS
:1; //Unknown FIS Interrupt
79 ULONG DPS
:1; //Descriptor Processed
80 ULONG PCS
:1; //Port Connect Change Status
81 ULONG DMPS
:1; //Device Mechanical Presence Status (DMPS)
83 ULONG PRCS
:1; //PhyRdy Change Status
84 ULONG IPMS
:1; //Incorrect Port Multiplier Status
85 ULONG OFS
:1; //Overflow Status
87 ULONG INFS
:1; //Interface Non-fatal Error Status
88 ULONG IFS
:1; //Interface Fatal Error Status
89 ULONG HBDS
:1; //Host Bus Data Error Status
90 ULONG HBFS
:1; //Host Bus Fatal Error Status
91 ULONG TFES
:1; //Task File Error Status
92 ULONG CPDS
:1; //Cold Port Detect Status
96 } AHCI_INTERRUPT_STATUS
;
98 typedef struct _AHCI_FIS_DMA_SETUP
100 ULONG ULONG0_1
; // FIS_TYPE_DMA_SETUP
103 // Data transfer direction, 1 - device to host
105 // Auto-activate. Specifies if DMA Activate FIS is needed
106 UCHAR Reserved
[2]; // Reserved
107 ULONG DmaBufferLow
; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
109 ULONG Reserved2
; // More reserved
110 ULONG DmaBufferOffset
; // Byte offset into buffer. First 2 bits must be 0
111 ULONG TranferCount
; // Number of bytes to transfer. Bit 0 must be 0
112 ULONG Reserved3
; // Reserved
113 } AHCI_FIS_DMA_SETUP
;
115 typedef struct _AHCI_PIO_SETUP_FIS
130 UCHAR SectorNumb_Exp
;
136 UCHAR SectorCount_Exp
;
140 USHORT TransferCount
;
142 } AHCI_PIO_SETUP_FIS
;
144 typedef struct _AHCI_D2H_REGISTER_FIS
164 UCHAR SectorCount_Exp
;
168 } AHCI_D2H_REGISTER_FIS
;
170 typedef struct _AHCI_SET_DEVICE_BITS_FIS
187 } AHCI_SET_DEVICE_BITS_FIS
;
189 typedef struct _AHCI_QUEUE
191 PVOID Buffer
[MAXIMUM_QUEUE_BUFFER_SIZE
]; // because Storahci hold Srb queue of 255 size
194 } AHCI_QUEUE
, *PAHCI_QUEUE
;
196 //////////////////////////////////////////////////////////////
197 // --------------------------- //
198 //////////////////////////////////////////////////////////////
200 typedef union _AHCI_COMMAND_HEADER_DESCRIPTION
204 ULONG CFL
:5; // Command FIS Length
205 ULONG A
:1; // IsATAPI
207 ULONG P
:1; // Prefetchable
211 ULONG C
:1; //Clear Busy upon R_OK
212 ULONG DW0_Reserved
:1;
213 ULONG PMP
:4; //Port Multiplier Port
215 ULONG PRDTL
:16; //Physical Region Descriptor Table Length
219 } AHCI_COMMAND_HEADER_DESCRIPTION
;
221 typedef struct _AHCI_PRDT
230 } AHCI_PRDT
, *PAHCI_PRDT
;
232 // 4.2.3 Command Table
233 typedef struct _AHCI_COMMAND_TABLE
235 // (16 * 32) + 64 + 16 + 48 = 648
236 // 128 byte aligned :D
240 AHCI_PRDT PRDT
[MAXIMUM_AHCI_PRDT_ENTRIES
];
241 } AHCI_COMMAND_TABLE
, *PAHCI_COMMAND_TABLE
;
243 // 4.2.2 Command Header
244 typedef struct _AHCI_COMMAND_HEADER
246 AHCI_COMMAND_HEADER_DESCRIPTION DI
; // DW 0
249 ULONG CTBA_U0
; // DW 3
250 ULONG Reserved
[4]; // DW 4-7
251 } AHCI_COMMAND_HEADER
, *PAHCI_COMMAND_HEADER
;
254 typedef struct _AHCI_RECEIVED_FIS
256 struct _AHCI_FIS_DMA_SETUP DmaSetupFIS
; // 0x00 -- DMA Setup FIS
257 ULONG pad0
; // 4 BYTE padding
258 struct _AHCI_PIO_SETUP_FIS PioSetupFIS
; // 0x20 -- PIO Setup FIS
259 ULONG pad1
[3]; // 12 BYTE padding
260 struct _AHCI_D2H_REGISTER_FIS RegisterFIS
; // 0x40 -- Register – Device to Host FIS
261 ULONG pad2
; // 4 BYTE padding
262 struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS
; // 0x58 -- Set Device Bit FIS
263 ULONG UnknowFIS
[16]; // 0x60 -- Unknown FIS
264 ULONG Reserved
[24]; // 0xA0 -- Reserved
265 } AHCI_RECEIVED_FIS
, *PAHCI_RECEIVED_FIS
;
267 // Holds Port Information
268 typedef struct _AHCI_PORT
270 ULONG CLB
; // 0x00, command list base address, 1K-byte aligned
271 ULONG CLBU
; // 0x04, command list base address upper 32 bits
272 ULONG FB
; // 0x08, FIS base address, 256-byte aligned
273 ULONG FBU
; // 0x0C, FIS base address upper 32 bits
274 ULONG IS
; // 0x10, interrupt status
275 ULONG IE
; // 0x14, interrupt enable
276 ULONG CMD
; // 0x18, command and status
277 ULONG RSV0
; // 0x1C, Reserved
278 ULONG TFD
; // 0x20, task file data
279 ULONG SIG
; // 0x24, signature
280 ULONG SSTS
; // 0x28, SATA status (SCR0:SStatus)
281 ULONG SCTL
; // 0x2C, SATA control (SCR2:SControl)
282 ULONG SERR
; // 0x30, SATA error (SCR1:SError)
283 ULONG SACT
; // 0x34, SATA active (SCR3:SActive)
284 ULONG CI
; // 0x38, command issue
285 ULONG SNTF
; // 0x3C, SATA notification (SCR4:SNotification)
286 ULONG FBS
; // 0x40, FIS-based switch control
287 ULONG RSV1
[11]; // 0x44 ~ 0x6F, Reserved
288 ULONG Vendor
[4]; // 0x70 ~ 0x7F, vendor specific
289 } AHCI_PORT
, *PAHCI_PORT
;
291 typedef struct _AHCI_MEMORY_REGISTERS
293 // 0x00 - 0x2B, Generic Host Control
294 ULONG CAP
; // 0x00, Host capability
295 ULONG GHC
; // 0x04, Global host control
296 ULONG IS
; // 0x08, Interrupt status
297 ULONG PI
; // 0x0C, Port implemented
298 ULONG VS
; // 0x10, Version
299 ULONG CCC_CTL
; // 0x14, Command completion coalescing control
300 ULONG CCC_PTS
; // 0x18, Command completion coalescing ports
301 ULONG EM_LOC
; // 0x1C, Enclosure management location
302 ULONG EM_CTL
; // 0x20, Enclosure management control
303 ULONG CAP2
; // 0x24, Host capabilities extended
304 ULONG BOHC
; // 0x28, BIOS/OS handoff control and status
305 ULONG Reserved
[0xA0-0x2C]; // 0x2C - 0x9F, Reserved
306 ULONG VendorSpecific
[0x100-0xA0]; // 0xA0 - 0xFF, Vendor specific registers
307 AHCI_PORT PortList
[MAXIMUM_AHCI_PORT_COUNT
];
309 } AHCI_MEMORY_REGISTERS
, *PAHCI_MEMORY_REGISTERS
;
311 // Holds information for each attached attached port to a given adapter.
312 typedef struct _AHCI_PORT_EXTENSION
315 ULONG QueueSlots
; // slots to which we have already assigned task
316 ULONG CommandIssuedSlots
;
318 PAHCI_PORT Port
; // AHCI Port Infomation
320 PAHCI_RECEIVED_FIS ReceivedFIS
;
321 PAHCI_COMMAND_HEADER CommandList
;
322 STOR_DEVICE_POWER_STATE DevicePowerState
; // Device Power State
323 PIDENTIFY_DEVICE_DATA IdentifyDeviceData
;
324 STOR_PHYSICAL_ADDRESS IdentifyDeviceDataPhysicalAddress
;
325 struct _AHCI_ADAPTER_EXTENSION
* AdapterExtension
; // Port's Adapter Information
326 } AHCI_PORT_EXTENSION
, *PAHCI_PORT_EXTENSION
;
328 // Holds Adapter Information
329 typedef struct _AHCI_ADAPTER_EXTENSION
331 ULONG SystemIoBusNumber
;
333 ULONG AhciBaseAddress
;
334 PULONG IS
;// Interrupt Status, In case of MSIM == `1`
335 ULONG PortImplemented
;// bit-mapping of ports which are implemented
345 ULONG LastInterruptPort
;
346 ULONG CurrentCommandSlot
;
348 PVOID NonCachedExtension
;// holds virtual address to noncached buffer allocated for Port Extension
352 // Message per port or shared port?
353 ULONG MessagePerPort
: 1;
355 ULONG Reserved
: 30; // not in use -- maintain 4 byte alignment
358 PAHCI_MEMORY_REGISTERS ABAR_Address
;
359 AHCI_PORT_EXTENSION PortExtension
[MAXIMUM_AHCI_PORT_COUNT
];
360 } AHCI_ADAPTER_EXTENSION
, *PAHCI_ADAPTER_EXTENSION
;
362 typedef struct _LOCAL_SCATTER_GATHER_LIST
364 ULONG NumberOfElements
;
366 STOR_SCATTER_GATHER_ELEMENT List
[MAXIMUM_AHCI_PRDT_ENTRIES
];
367 } LOCAL_SCATTER_GATHER_LIST
, *PLOCAL_SCATTER_GATHER_LIST
;
369 typedef struct _AHCI_SRB_EXTENSION
371 AHCI_COMMAND_TABLE CommandTable
;
386 UCHAR SectorCountLow
;
387 UCHAR SectorCountHigh
;
390 LOCAL_SCATTER_GATHER_LIST Sgl
;
391 } AHCI_SRB_EXTENSION
, *PAHCI_SRB_EXTENSION
;
393 //////////////////////////////////////////////////////////////
395 //////////////////////////////////////////////////////////////
399 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
406 __in ULONG BufferSize
412 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
417 DeviceInquiryRequest (
418 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
,
419 __in PSCSI_REQUEST_BLOCK Srb
,
426 __inout PAHCI_QUEUE Queue
,
433 __inout PAHCI_QUEUE Queue
439 __in PSCSI_REQUEST_BLOCK Srb