- Fixed CMakeLists issues reported by hbelusca
[reactos.git] / drivers / storage / storahci / storahci.h
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GNU GPLv2 only as published by the Free Software Foundation
4 * PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
5 * PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
6 */
7
8 #include <ntddk.h>
9 #include <storport.h>
10
11 #define DEBUG 1
12
13 #define MAXIMUM_AHCI_PORT_COUNT 12
14 #define MAXIMUM_QUEUE_BUFFER_SIZE 255
15 #define MAXIMUM_TRANSFER_LENGTH (128*1024) // 128 KB
16
17 // section 3.1.2
18 #define AHCI_Global_HBA_CONTROL_HR (1 << 0)
19 #define AHCI_Global_HBA_CONTROL_IE (1 << 1)
20 #define AHCI_Global_HBA_CONTROL_MRSM (1 << 2)
21 #define AHCI_Global_HBA_CONTROL_AE (1 << 31)
22 #define AHCI_Global_HBA_CAP_S64A (1 << 31)
23
24 // 3.1.1 NCS = CAP[12:08] -> Align
25 #define AHCI_Global_Port_CAP_NCS(x) (((x) & 0xF00) >> 8)
26
27 #define ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
28 #if DEBUG
29 #define DebugPrint(format, ...) StorPortDebugPrint(0, format, __VA_ARGS__)
30 #endif
31
32 //////////////////////////////////////////////////////////////
33 // ---- Support Structures --- //
34 //////////////////////////////////////////////////////////////
35
36 // section 3.3.5
37 typedef union _AHCI_INTERRUPT_STATUS
38 {
39 struct
40 {
41 ULONG DHRS:1; //Device to Host Register FIS Interrupt
42 ULONG PSS :1; //PIO Setup FIS Interrupt
43 ULONG DSS :1; //DMA Setup FIS Interrupt
44 ULONG SDBS :1; //Set Device Bits Interrupt
45 ULONG UFS :1; //Unknown FIS Interrupt
46 ULONG DPS :1; //Descriptor Processed
47 ULONG PCS :1; //Port Connect Change Status
48 ULONG DMPS :1; //Device Mechanical Presence Status (DMPS)
49 ULONG Reserved :14;
50 ULONG PRCS :1; //PhyRdy Change Status
51 ULONG IPMS :1; //Incorrect Port Multiplier Status
52 ULONG OFS :1; //Overflow Status
53 ULONG Reserved2 :1;
54 ULONG INFS :1; //Interface Non-fatal Error Status
55 ULONG IFS :1; //Interface Fatal Error Status
56 ULONG HBDS :1; //Host Bus Data Error Status
57 ULONG HBFS :1; //Host Bus Fatal Error Status
58 ULONG TFES :1; //Task File Error Status
59 ULONG CPDS :1; //Cold Port Detect Status
60 };
61
62 ULONG Status;
63 } AHCI_INTERRUPT_STATUS;
64
65 typedef struct _AHCI_FIS_DMA_SETUP
66 {
67 ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
68 // Port multiplier
69 // Reserved
70 // Data transfer direction, 1 - device to host
71 // Interrupt bit
72 // Auto-activate. Specifies if DMA Activate FIS is needed
73 UCHAR Reserved[2]; // Reserved
74 ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
75 ULONG DmaBufferHigh;
76 ULONG Reserved2; // More reserved
77 ULONG DmaBufferOffset; // Byte offset into buffer. First 2 bits must be 0
78 ULONG TranferCount; // Number of bytes to transfer. Bit 0 must be 0
79 ULONG Reserved3; // Reserved
80 } AHCI_FIS_DMA_SETUP;
81
82 typedef struct _AHCI_PIO_SETUP_FIS
83 {
84 UCHAR FisType;
85 UCHAR Reserved1 :5;
86 UCHAR D :1;
87 UCHAR I :1;
88 UCHAR Reserved2 :1;
89 UCHAR Status;
90 UCHAR Error;
91
92 UCHAR SectorNumber;
93 UCHAR CylLow;
94 UCHAR CylHigh;
95 UCHAR Dev_Head;
96
97 UCHAR SectorNumb_Exp;
98 UCHAR CylLow_Exp;
99 UCHAR CylHigh_Exp;
100 UCHAR Reserved3;
101
102 UCHAR SectorCount;
103 UCHAR SectorCount_Exp;
104 UCHAR Reserved4;
105 UCHAR E_Status;
106
107 USHORT TransferCount;
108 UCHAR Reserved5[2];
109 } AHCI_PIO_SETUP_FIS;
110
111 typedef struct _AHCI_D2H_REGISTER_FIS
112 {
113 UCHAR FisType;
114 UCHAR Reserved1 :6;
115 UCHAR I:1;
116 UCHAR Reserved2 :1;
117 UCHAR Status;
118 UCHAR Error;
119
120 UCHAR SectorNumber;
121 UCHAR CylLow;
122 UCHAR CylHigh;
123 UCHAR Dev_Head;
124
125 UCHAR SectorNum_Exp;
126 UCHAR CylLow_Exp;
127 UCHAR CylHigh_Exp;
128 UCHAR Reserved;
129
130 UCHAR SectorCount;
131 UCHAR SectorCount_Exp;
132 UCHAR Reserved3[2];
133
134 UCHAR Reserved4[4];
135 } AHCI_D2H_REGISTER_FIS;
136
137 typedef struct _AHCI_SET_DEVICE_BITS_FIS
138 {
139 UCHAR FisType;
140
141 UCHAR PMPort: 4;
142 UCHAR Reserved1 :2;
143 UCHAR I :1;
144 UCHAR N :1;
145
146 UCHAR Status_Lo :3;
147 UCHAR Reserved2 :1;
148 UCHAR Status_Hi :3;
149 UCHAR Reserved3 :1;
150
151 UCHAR Error;
152
153 UCHAR Reserved5[4];
154 } AHCI_SET_DEVICE_BITS_FIS;
155
156 typedef struct _AHCI_QUEUE
157 {
158 PVOID Buffer[MAXIMUM_QUEUE_BUFFER_SIZE]; // because Storahci hold Srb queue of 255 size
159 ULONG Head;
160 ULONG Tail;
161 } AHCI_QUEUE, *PAHCI_QUEUE;
162
163 //////////////////////////////////////////////////////////////
164 // --------------------------- //
165 //////////////////////////////////////////////////////////////
166
167 // 4.2.2 Command Header
168 typedef struct _AHCI_COMMAND_HEADER
169 {
170 ULONG HEADER_DESCRIPTION; // DW 0
171 ULONG PRDBC; // DW 1
172 ULONG CTBA0; // DW 2
173 ULONG CTBA_U0; // DW 3
174 ULONG Reserved[4]; // DW 4-7
175 } AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
176
177 // Received FIS
178 typedef struct _AHCI_RECEIVED_FIS
179 {
180 struct _AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
181 ULONG pad0; // 4 BYTE padding
182 struct _AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
183 ULONG pad1[3]; // 12 BYTE padding
184 struct _AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
185 ULONG pad2; // 4 BYTE padding
186 struct _AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
187 ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
188 ULONG Reserved[24]; // 0xA0 -- Reserved
189 } AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
190
191 // Holds Port Information
192 typedef struct _AHCI_PORT
193 {
194 ULONG CLB; // 0x00, command list base address, 1K-byte aligned
195 ULONG CLBU; // 0x04, command list base address upper 32 bits
196 ULONG FB; // 0x08, FIS base address, 256-byte aligned
197 ULONG FBU; // 0x0C, FIS base address upper 32 bits
198 ULONG IS; // 0x10, interrupt status
199 ULONG IE; // 0x14, interrupt enable
200 ULONG CMD; // 0x18, command and status
201 ULONG RSV0; // 0x1C, Reserved
202 ULONG TFD; // 0x20, task file data
203 ULONG SIG; // 0x24, signature
204 ULONG SSTS; // 0x28, SATA status (SCR0:SStatus)
205 ULONG SCTL; // 0x2C, SATA control (SCR2:SControl)
206 ULONG SERR; // 0x30, SATA error (SCR1:SError)
207 ULONG SACT; // 0x34, SATA active (SCR3:SActive)
208 ULONG CI; // 0x38, command issue
209 ULONG SNTF; // 0x3C, SATA notification (SCR4:SNotification)
210 ULONG FBS; // 0x40, FIS-based switch control
211 ULONG RSV1[11]; // 0x44 ~ 0x6F, Reserved
212 ULONG Vendor[4]; // 0x70 ~ 0x7F, vendor specific
213 } AHCI_PORT, *PAHCI_PORT;
214
215 typedef struct _AHCI_MEMORY_REGISTERS
216 {
217 // 0x00 - 0x2B, Generic Host Control
218 ULONG CAP; // 0x00, Host capability
219 ULONG GHC; // 0x04, Global host control
220 ULONG IS; // 0x08, Interrupt status
221 ULONG PI; // 0x0C, Port implemented
222 ULONG VS; // 0x10, Version
223 ULONG CCC_CTL; // 0x14, Command completion coalescing control
224 ULONG CCC_PTS; // 0x18, Command completion coalescing ports
225 ULONG EM_LOC; // 0x1C, Enclosure management location
226 ULONG EM_CTL; // 0x20, Enclosure management control
227 ULONG CAP2; // 0x24, Host capabilities extended
228 ULONG BOHC; // 0x28, BIOS/OS handoff control and status
229 ULONG Reserved[0xA0-0x2C]; // 0x2C - 0x9F, Reserved
230 ULONG VendorSpecific[0x100-0xA0]; // 0xA0 - 0xFF, Vendor specific registers
231 AHCI_PORT PortList[MAXIMUM_AHCI_PORT_COUNT];
232
233 } AHCI_MEMORY_REGISTERS, *PAHCI_MEMORY_REGISTERS;
234
235 // Holds information for each attached attached port to a given adapter.
236 typedef struct _AHCI_PORT_EXTENSION
237 {
238 ULONG PortNumber;
239 ULONG OccupiedSlots; // slots to which we have already assigned task
240 BOOLEAN IsActive;
241 PAHCI_PORT Port; // AHCI Port Infomation
242 AHCI_QUEUE SrbQueue;
243 PAHCI_RECEIVED_FIS ReceivedFIS;
244 PAHCI_COMMAND_HEADER CommandList;
245 STOR_DEVICE_POWER_STATE DevicePowerState; // Device Power State
246 struct _AHCI_ADAPTER_EXTENSION* AdapterExtension; // Port's Adapter Information
247 } AHCI_PORT_EXTENSION, *PAHCI_PORT_EXTENSION;
248
249 // Holds Adapter Information
250 typedef struct _AHCI_ADAPTER_EXTENSION
251 {
252 ULONG SystemIoBusNumber;
253 ULONG SlotNumber;
254 ULONG AhciBaseAddress;
255 PULONG IS;// Interrupt Status, In case of MSIM == `1`
256 ULONG PortImplemented;// bit-mapping of ports which are implemented
257
258 USHORT VendorID;
259 USHORT DeviceID;
260 USHORT RevisionID;
261
262 ULONG Version;
263 ULONG CAP;
264 ULONG CAP2;
265 ULONG LastInterruptPort;
266
267 PVOID NonCachedExtension;// holds virtual address to noncached buffer allocated for Port Extension
268
269 struct
270 {
271 // Message per port or shared port?
272 ULONG MessagePerPort : 1;
273 ULONG Removed : 1;
274 ULONG Reserved : 30; // not in use -- maintain 4 byte alignment
275 } StateFlags;
276
277 PAHCI_MEMORY_REGISTERS ABAR_Address;
278 AHCI_PORT_EXTENSION PortExtension[MAXIMUM_AHCI_PORT_COUNT];
279 } AHCI_ADAPTER_EXTENSION, *PAHCI_ADAPTER_EXTENSION;
280
281 typedef struct _AHCI_SRB_EXTENSION
282 {
283 ULONG Reserved[4];
284 } AHCI_SRB_EXTENSION;
285
286 //////////////////////////////////////////////////////////////
287 // Declarations //
288 //////////////////////////////////////////////////////////////
289
290 BOOLEAN
291 AhciAdapterReset (
292 __in PAHCI_ADAPTER_EXTENSION AdapterExtension
293 );
294
295 __inline
296 VOID
297 AhciZeroMemory (
298 __out PCHAR Buffer,
299 __in ULONG BufferSize
300 );
301
302 __inline
303 BOOLEAN
304 IsPortValid (
305 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
306 __in UCHAR pathId
307 );
308
309 ULONG
310 DeviceInquiryRequest (
311 __in PAHCI_ADAPTER_EXTENSION AdapterExtension,
312 __in PSCSI_REQUEST_BLOCK Srb,
313 __in PCDB Cdb
314 );
315
316 __inline
317 BOOLEAN
318 AddQueue (
319 __inout PAHCI_QUEUE Queue,
320 __in PVOID Srb
321 );
322
323 __inline
324 PVOID
325 RemoveQueue (
326 __inout PAHCI_QUEUE Queue
327 );