AhciFindAdapter Completed
[reactos.git] / drivers / storage / storahci / storahci.h
1 /*
2 * PROJECT: ReactOS Kernel
3 * LICENSE: GNU GPLv2 only as published by the Free Software Foundation
4 * PURPOSE: To Implement AHCI Miniport driver targeting storport NT 5.2
5 * PROGRAMMERS: Aman Priyadarshi (aman.eureka@gmail.com)
6 */
7
8 #include "miniport.h"
9 #include "storport.h"
10
11 #define AHCI_POOL_TAG 'ahci'
12
13 typedef struct _AHCI_FIS_DMA_SETUP
14 {
15 ULONG ULONG0_1; // FIS_TYPE_DMA_SETUP
16 // Port multiplier
17 // Reserved
18 // Data transfer direction, 1 - device to host
19 // Interrupt bit
20 // Auto-activate. Specifies if DMA Activate FIS is needed
21 UCHAR Reserved[2]; // Reserved
22 ULONG DmaBufferLow; // DMA Buffer Identifier. Used to Identify DMA buffer in host memory. SATA Spec says host specific and not in Spec. Trying AHCI spec might work.
23 ULONG DmaBufferHigh;
24 ULONG Reserved2; //More reserved
25 ULONG DmaBufferOffset; //Byte offset into buffer. First 2 bits must be 0
26 ULONG TranferCount; //Number of bytes to transfer. Bit 0 must be 0
27 ULONG Reserved3; //Reserved
28 } AHCI_FIS_DMA_SETUP;
29
30 typedef struct _AHCI_PIO_SETUP_FIS
31 {
32 UCHAR FisType; //0x5F
33 UCHAR Reserved1 :5;
34 UCHAR D :1; // 1 is write (device to host)
35 UCHAR I :1;
36 UCHAR Reserved2 :1;
37 UCHAR Status;
38 UCHAR Error;
39
40 UCHAR SectorNumber;
41 UCHAR CylLow;
42 UCHAR CylHigh;
43 UCHAR Dev_Head;
44
45 UCHAR SectorNumb_Exp;
46 UCHAR CylLow_Exp;
47 UCHAR CylHigh_Exp;
48 UCHAR Reserved3;
49
50 UCHAR SectorCount;
51 UCHAR SectorCount_Exp;
52 UCHAR Reserved4;
53 UCHAR E_Status;
54
55 USHORT TransferCount;
56 UCHAR Reserved5[2];
57
58 } AHCI_PIO_SETUP_FIS;
59
60 typedef struct _AHCI_D2H_REGISTER_FIS
61 {
62 UCHAR FisType; // 0x34
63 UCHAR Reserved1 :6;
64 UCHAR I:1;
65 UCHAR Reserved2 :1;
66 UCHAR Status;
67 UCHAR Error;
68
69 UCHAR SectorNumber;
70 UCHAR CylLow;
71 UCHAR CylHigh;
72 UCHAR Dev_Head;
73
74 UCHAR SectorNum_Exp;
75 UCHAR CylLow_Exp;
76 UCHAR CylHigh_Exp;
77 UCHAR Reserved;
78
79 UCHAR SectorCount;
80 UCHAR SectorCount_Exp;
81 UCHAR Reserved3[2];
82
83 UCHAR Reserved4[4];
84 } AHCI_D2H_REGISTER_FIS;
85
86 typedef struct _AHCI_SET_DEVICE_BITS_FIS {
87
88 UCHAR FisType; //0xA1
89
90 UCHAR PMPort: 4;
91 UCHAR Reserved1 :2;
92 UCHAR I :1;
93 UCHAR N :1;
94
95 UCHAR Status_Lo :3;
96 UCHAR Reserved2 :1;
97 UCHAR Status_Hi :3;
98 UCHAR Reserved3 :1;
99
100 UCHAR Error;
101
102 UCHAR Reserved5[4];
103 } AHCI_SET_DEVICE_BITS_FIS;
104
105 // 4.2.2
106 typedef struct _AHCI_COMMAND_HEADER
107 {
108 ULONG HEADER_DESCRIPTION; // DW 0
109 ULONG PRDBC; // DW 1
110 ULONG CTBA0; // DW 2
111 ULONG CTBA_U0; // DW 3
112 ULONG Reserved[4]; // DW 4-7
113 } AHCI_COMMAND_HEADER, *PAHCI_COMMAND_HEADER;
114
115 // Received FIS
116 typedef struct _AHCI_RECEIVED_FIS
117 {
118 AHCI_FIS_DMA_SETUP DmaSetupFIS; // 0x00 -- DMA Setup FIS
119 ULONG pad0; // 4 BYTE padding
120 AHCI_PIO_SETUP_FIS PioSetupFIS; // 0x20 -- PIO Setup FIS
121 ULONG pad1[3]; // 12 BYTE padding
122 AHCI_D2H_REGISTER_FIS RegisterFIS; // 0x40 -- Register – Device to Host FIS
123 ULONG pad2; // 4 BYTE padding
124 AHCI_SET_DEVICE_BITS_FIS SetDeviceFIS; // 0x58 -- Set Device Bit FIS
125 ULONG UnknowFIS[16]; // 0x60 -- Unknown FIS
126 ULONG Reserved[24]; // 0xA0 -- Reserved
127 } AHCI_RECEIVED_FIS, *PAHCI_RECEIVED_FIS;
128
129 typedef struct _AHCI_PORT
130 {
131 ULONG CLB; // 0x00, command list base address, 1K-byte aligned
132 ULONG CLBU; // 0x04, command list base address upper 32 bits
133 ULONG FB; // 0x08, FIS base address, 256-byte aligned
134 ULONG FBU; // 0x0C, FIS base address upper 32 bits
135 ULONG IS; // 0x10, interrupt status
136 ULONG IE; // 0x14, interrupt enable
137 ULONG CMD; // 0x18, command and status
138 ULONG RSV0; // 0x1C, Reserved
139 ULONG TFD; // 0x20, task file data
140 ULONG SIG; // 0x24, signature
141 ULONG SSTS; // 0x28, SATA status (SCR0:SStatus)
142 ULONG SCTL; // 0x2C, SATA control (SCR2:SControl)
143 ULONG SERR; // 0x30, SATA error (SCR1:SError)
144 ULONG SACT; // 0x34, SATA active (SCR3:SActive)
145 ULONG CI; // 0x38, command issue
146 ULONG SNTF; // 0x3C, SATA notification (SCR4:SNotification)
147 ULONG FBS; // 0x40, FIS-based switch control
148 ULONG RSV1[11]; // 0x44 ~ 0x6F, Reserved
149 ULONG Vendor[4]; // 0x70 ~ 0x7F, vendor specific
150 } AHCI_PORT, *PAHCI_PORT;
151
152 typedef struct _AHCI_MEMORY_REGISTERS
153 {
154 // 0x00 - 0x2B, Generic Host Control
155 ULONG CAP; // 0x00, Host capability
156 ULONG GHC; // 0x04, Global host control
157 ULONG IS; // 0x08, Interrupt status
158 ULONG PI; // 0x0C, Port implemented
159 ULONG VS; // 0x10, Version
160 ULONG CCC_CTL; // 0x14, Command completion coalescing control
161 ULONG CCC_PTS; // 0x18, Command completion coalescing ports
162 ULONG EM_LOC; // 0x1C, Enclosure management location
163 ULONG EM_CTL; // 0x20, Enclosure management control
164 ULONG CAP2; // 0x24, Host capabilities extended
165 ULONG BOHC; // 0x28, BIOS/OS handoff control and status
166
167 // 0x2C - 0x9F, Reserved
168 ULONG Reserved[0xA0-0x2C];
169
170 // 0xA0 - 0xFF, Vendor specific registers
171 ULONG VendorSpecific[0x100-0xA0];
172
173 AHCI_PORT PortList[32];//1~32
174
175 } AHCI_MEMORY_REGISTERS, *PAHCI_MEMORY_REGISTERS;
176
177 struct _AHCI_ADAPTER_EXTENSION;
178
179 typedef struct _AHCI_PORT_EXTENSION
180 {
181 ULONG PortNumber;
182 struct _AHCI_ADAPTER_EXTENSION* AdapterExtension;
183 PAHCI_COMMAND_HEADER CommandList;
184 PAHCI_RECEIVED_FIS ReceivedFIS;
185 PAHCI_PORT Port;
186 } AHCI_PORT_EXTENSION, *PAHCI_PORT_EXTENSION;
187
188 typedef struct _AHCI_ADAPTER_EXTENSION
189 {
190 ULONG AdapterNumber;
191 ULONG SystemIoBusNumber;
192 ULONG SlotNumber;
193 ULONG AhciBaseAddress;
194 ULONG IS; // Interrupt status
195 ULONG PortImplemented;
196
197 USHORT VendorID;
198 USHORT DeviceID;
199 USHORT RevisionID;
200
201 ULONG Version;
202 ULONG CAP;
203 ULONG CAP2;
204
205 PVOID NonCachedExtension;
206
207 PAHCI_MEMORY_REGISTERS ABAR_Address;
208 PAHCI_PORT_EXTENSION PortExtension[32];
209 } AHCI_ADAPTER_EXTENSION, *PAHCI_ADAPTER_EXTENSION;
210
211 typedef struct _AHCI_SRB_EXTENSION
212 {
213 ULONG AdapterNumber;
214 } AHCI_SRB_EXTENSION;