2 * Copyright (c) 2007 by Aleksey Bragin
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #define OHCI_DEVICE_NAME "\\Device\\OHCI"
22 #define OHCI_DOS_DEVICE_NAME "\\DosDevices\\OHCI"
24 /* Host Controller Operational Registers */
26 #define OHCI_REVISION 0x0
27 #define OHCI_CONTROL 0x4
28 #define OHCI_CMDSTATUS 0x8
29 #define OHCI_INTRSTATUS 0xc
30 #define OHCI_INTRENABLE 0x10
31 #define OHCI_INTRDISABLE 0x14
33 /* OHCI CONTROL AND STATUS REGISTER MASKS */
36 * HcControl (control) register masks
38 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
39 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
40 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
41 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
42 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
43 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
44 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
45 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
46 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
48 /* pre-shifted values for HCFS */
49 # define OHCI_USB_RESET (0 << 6)
50 # define OHCI_USB_RESUME (1 << 6)
51 # define OHCI_USB_OPER (2 << 6)
52 # define OHCI_USB_SUSPEND (3 << 6)
55 * HcCommandStatus (cmdstatus) register masks
57 #define OHCI_HCR (1 << 0) /* host controller reset */
58 #define OHCI_CLF (1 << 1) /* control list filled */
59 #define OHCI_BLF (1 << 2) /* bulk list filled */
60 #define OHCI_OCR (1 << 3) /* ownership change request */
61 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
64 * masks used with interrupt registers:
65 * HcInterruptStatus (intrstatus)
66 * HcInterruptEnable (intrenable)
67 * HcInterruptDisable (intrdisable)
69 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
70 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
71 #define OHCI_INTR_SF (1 << 2) /* start frame */
72 #define OHCI_INTR_RD (1 << 3) /* resume detect */
73 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
74 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
75 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
76 #define OHCI_INTR_OC (1 << 30) /* ownership change */
77 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
80 /* OHCI ROOT HUB REGISTER MASKS */
82 /* roothub.portstatus [i] bits */
83 #define RH_PS_CCS 0x00000001 /* current connect status */
84 #define RH_PS_PES 0x00000002 /* port enable status*/
85 #define RH_PS_PSS 0x00000004 /* port suspend status */
86 #define RH_PS_POCI 0x00000008 /* port over current indicator */
87 #define RH_PS_PRS 0x00000010 /* port reset status */
88 #define RH_PS_PPS 0x00000100 /* port power status */
89 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
90 #define RH_PS_CSC 0x00010000 /* connect status change */
91 #define RH_PS_PESC 0x00020000 /* port enable status change */
92 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
93 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
94 #define RH_PS_PRSC 0x00100000 /* port reset status change */
96 /* roothub.status bits */
97 #define RH_HS_LPS 0x00000001 /* local power status */
98 #define RH_HS_OCI 0x00000002 /* over current indicator */
99 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
100 #define RH_HS_LPSC 0x00010000 /* local power status change */
101 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
102 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
104 /* roothub.b masks */
105 #define RH_B_DR 0x0000ffff /* device removable flags */
106 #define RH_B_PPCM 0xffff0000 /* port power control mask */
108 /* roothub.a masks */
109 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
110 #define RH_A_PSM (1 << 8) /* power switching mode */
111 #define RH_A_NPS (1 << 9) /* no power switching */
112 #define RH_A_DT (1 << 10) /* device type (mbz) */
113 #define RH_A_OCPM (1 << 11) /* over current protection mode */
114 #define RH_A_NOCP (1 << 12) /* no over current protection */
115 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
118 * OHCI Endpoint Descriptor (ED) ... holds TD queue
119 * See OHCI spec, section 4.2
121 * This is a "Queue Head" for those transfers, which is why
122 * both EHCI and UHCI call similar structures a "QH".
124 typedef struct _OHCI_ED
{
125 /* first fields are hardware-specified */
126 ULONG hwINFO
; /* endpoint config bitmap */
127 /* info bits defined by hcd */
128 #define ED_DEQUEUE (1 << 27)
129 /* info bits defined by the hardware */
130 #define ED_ISO (1 << 15)
131 #define ED_SKIP (1 << 14)
132 #define ED_LOWSPEED (1 << 13)
133 #define ED_OUT (0x01 << 11)
134 #define ED_IN (0x02 << 11)
135 ULONG hwTailP
; /* tail of TD list */
136 ULONG hwHeadP
; /* head of TD list (hc r/w) */
137 #define ED_C (0x02) /* toggle carry */
138 #define ED_H (0x01) /* halted */
139 ULONG hwNextED
; /* next ED in list */
141 /* rest are purely for the driver's use */
143 dma_addr_t dma
; /* addr of ED */
144 struct _OHCI_TD
*dummy
; /* next TD to activate */
146 /* host's view of schedule */
147 struct _OHCI_ED
*ed_next
; /* on schedule or rm_list */
148 struct _OHCI_ED
*ed_prev
; /* for non-interrupt EDs */
149 struct list_head td_list
; /* "shadow list" of our TDs */
151 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
152 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
154 UCHAR state
; /* ED_{IDLE,UNLINK,OPER} */
155 #define ED_IDLE 0x00 /* NOT linked to HC */
156 #define ED_UNLINK 0x01 /* being unlinked from hc */
157 #define ED_OPER 0x02 /* IS linked to hc */
159 UCHAR type
; /* PIPE_{BULK,...} */
161 /* periodic scheduling params (for intr and iso) */
165 USHORT last_iso
; /* iso only */
167 /* HC may see EDs on rm_list until next frame (frame_no == tick) */
170 } OHCI_ED
, *POHCI_ED
;
172 #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */
176 * OHCI Transfer Descriptor (TD) ... one per transfer segment
177 * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt)
180 typedef struct _OHCI_TD
{
181 /* first fields are hardware-specified */
182 ULONG hwINFO
; /* transfer info bitmask */
184 /* hwINFO bits for both general and iso tds: */
185 #define TD_CC 0xf0000000 /* condition code */
186 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
187 //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
188 #define TD_DI 0x00E00000 /* frames before interrupt */
189 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
190 /* these two bits are available for definition/use by HCDs in both
191 * general and iso tds ... others are available for only one type
193 #define TD_DONE 0x00020000 /* retired to donelist */
194 #define TD_ISO 0x00010000 /* copy of ED_ISO */
196 /* hwINFO bits for general tds: */
197 #define TD_EC 0x0C000000 /* error count */
198 #define TD_T 0x03000000 /* data toggle state */
199 #define TD_T_DATA0 0x02000000 /* DATA0 */
200 #define TD_T_DATA1 0x03000000 /* DATA1 */
201 #define TD_T_TOGGLE 0x00000000 /* uses ED_C */
202 #define TD_DP 0x00180000 /* direction/pid */
203 #define TD_DP_SETUP 0x00000000 /* SETUP pid */
204 #define TD_DP_IN 0x00100000 /* IN pid */
205 #define TD_DP_OUT 0x00080000 /* OUT pid */
206 /* 0x00180000 rsvd */
207 #define TD_R 0x00040000 /* round: short packets OK? */
209 /* (no hwINFO #defines yet for iso tds) */
211 ULONG hwCBP
; /* Current Buffer Pointer (or 0) */
212 ULONG hwNextTD
; /* Next TD Pointer */
213 ULONG hwBE
; /* Memory Buffer End Pointer */
215 /* PSW is only for ISO. Only 1 PSW entry is used, but on
216 * big-endian PPC hardware that's the second entry.
219 USHORT hwPSW
[MAXPSW
];
221 /* rest are purely for the driver's use */
225 struct td
*td_hash
; /* dma-->td hashtable */
226 struct td
*next_dl_td
;
229 dma_addr_t td_dma
; /* addr of this TD */
230 dma_addr_t data_dma
; /* addr of data it points to */
232 struct list_head td_list
; /* "shadow list", TDs on same ED */
234 } OHCI_TD
, *POHCI_TD
;
237 * The HCCA (Host Controller Communications Area) is a 256 byte
238 * structure defined section 4.4.1 of the OHCI spec. The HC is
239 * told the base address of it. It must be 256-byte aligned.
241 typedef struct _OHCI_HCCA
244 ULONG int_table
[NUM_INTS
]; /* periodic schedule */
247 * OHCI defines u16 frame_no, followed by u16 zero pad.
248 * Since some processors can't do 16 bit bus accesses,
249 * portable access must be a 32 bits wide.
251 ULONG frame_no
; /* current frame number */
252 ULONG done_head
; /* info returned for an interrupt */
253 UCHAR reserved_for_hc
[116];
254 UCHAR what
[4]; /* spec only identifies 252 bytes :) */
255 } OHCI_HCCA
, *POHCI_HCCA
;
258 * This is the structure of the OHCI controller's memory mapped I/O region.
259 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
260 * Layout is in section 7 (and appendix B) of the spec.
262 typedef struct _OHCI_REGS
264 /* control and status registers (section 7.1) */
272 /* memory pointers (section 7.2) */
274 ULONG ed_periodcurrent
;
275 ULONG ed_controlhead
;
276 ULONG ed_controlcurrent
;
278 ULONG ed_bulkcurrent
;
281 /* frame counters (section 7.3) */
288 /* Root hub ports (section 7.4) */
289 struct ohci_roothub_regs
{
293 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */
294 ULONG portstatus
[MAX_ROOT_PORTS
];
297 /* and optional "legacy support" registers (appendix B) at 0x0100 */
298 } OHCI_REGS
, *POHCI_REGS
;
300 typedef struct _OHCI_DEV
304 PHYSICAL_ADDRESS ohci_reg_base
; // io space
306 PBYTE port_base
; // note: added by ehci_caps.length, operational regs base addr, not the actural base
307 struct _OHCI_REGS
*regs
;
308 struct _OHCI_HCCA
*hcca
;
312 PHYSICAL_ADDRESS hcca_logic_addr
;
313 PHYSICAL_ADDRESS td_logic_addr
;
314 PHYSICAL_ADDRESS ed_logic_addr
;
318 LIST_HEAD urb_list
; // active urb-list
321 //for iso and int bandwidth claim, bandwidth schedule
323 KSPIN_LOCK pending_endp_list_lock
; //lock to access the following two
324 LIST_HEAD pending_endp_list
;
325 UHCI_PENDING_ENDP_POOL pending_endp_pool
;
327 KTIMER reset_timer
; //used to reset the host controller
328 struct _OHCI_DEVICE_EXTENSION
*pdev_ext
;
329 PUSB_DEV root_hub
; //root hub
330 } OHCI_DEV
, *POHCI_DEV
;
332 typedef struct _OHCI_DEVICE_EXTENSION
334 DEVEXT_HEADER dev_ext_hdr
;
335 PDEVICE_OBJECT pdev_obj
;
336 PDRIVER_OBJECT pdrvr_obj
;
340 PADAPTER_OBJECT padapter
;
342 PCM_RESOURCE_LIST res_list
;
343 ULONG pci_addr
; // bus number | slot number | funciton number
344 UHCI_INTERRUPT res_interrupt
;
348 EHCI_MEMORY res_memory
;
351 PKINTERRUPT ohci_int
;
353 } OHCI_DEVICE_EXTENSION
, *POHCI_DEVICE_EXTENSION
;
355 #define ohci_from_hcd( hCD ) ( struct_ptr( ( hCD ), OHCI_DEV, hcd_interf ) )
357 #endif /* __OHCI_H__ */