drivers/usb/usbehci/hardware.h

   1 #pragma once
   2
   3 #include <ntddk.h>
   4
   5 /* USB Command Register */
   6 #define EHCI_USBCMD         0x00
   7 #define EHCI_USBSTS         0x04
   8 #define EHCI_USBINTR            0x08
   9 #define EHCI_FRINDEX            0x0C
  10 #define EHCI_CTRLDSSEGMENT      0x10
  11 #define EHCI_PERIODICLISTBASE       0x14
  12 #define EHCI_ASYNCLISTBASE      0x18
  13 #define EHCI_CONFIGFLAG         0x40
  14 #define EHCI_PORTSC         0x44
  15
  16 /* USB Interrupt Register Flags 32 Bits */
  17 #define EHCI_USBINTR_INTE       0x01
  18 #define EHCI_USBINTR_ERR        0x02
  19 #define EHCI_USBINTR_PC         0x04
  20 #define EHCI_USBINTR_FLROVR     0x08
  21 #define EHCI_USBINTR_HSERR      0x10
  22 #define EHCI_USBINTR_ASYNC      0x20
  23 /* Bits 6:31 Reserved */
  24
  25 /* Status Register Flags 32 Bits */
  26 #define EHCI_STS_INT            0x01
  27 #define EHCI_STS_ERR            0x02
  28 #define EHCI_STS_PCD            0x04
  29 #define EHCI_STS_FLR            0x08
  30 #define EHCI_STS_FATAL          0x10
  31 #define EHCI_STS_IAA            0x20
  32 /* Bits 11:6 Reserved */
  33 #define EHCI_STS_HALT           0x1000
  34 #define EHCI_STS_RECL           0x2000
  35 #define EHCI_STS_PSS            0x4000
  36 #define EHCI_STS_ASS            0x8000
  37 #define EHCI_ERROR_INT ( EHCI_STS_FATAL | EHCI_STS_ERR )
  38
  39
  40 /* Last bit in QUEUE ELEMENT TRANSFER DESCRIPTOR Next Pointer */
  41 /* Used for Queue Element Transfer Descriptor Pointers
  42    and Queue Head Horizontal Link Pointers */
  43 #define TERMINATE_POINTER       0x01
  44
  45 /* QUEUE ELEMENT TRANSFER DESCRIPTOR, Token defines and structs */
  46
  47 /* PIDCodes for QETD_TOKEN
  48 OR with QUEUE_TRANSFER_DESCRIPTOR Token.PIDCode*/
  49 #define PID_CODE_OUT_TOKEN      0x00
  50 #define PID_CODE_IN_TOKEN       0x01
  51 #define PID_CODE_SETUP_TOKEN    0x02
  52
  53 /* Split Transaction States
  54 OR with QUEUE_TRANSFER_DESCRIPTOR Token.SplitTransactionState */
  55 #define DO_START_SPLIT          0x00
  56 #define DO_COMPLETE_SPLIT       0x01
  57
  58 /* Ping States, OR with QUEUE_TRANSFER_DESCRIPTOR Token. */
  59 #define PING_STATE_DO_OUT       0x00
  60 #define PING_STATE_DO_PING      0x01
  61
  62 typedef struct _PERIODICFRAMELIST
  63 {
  64     PULONG VirtualAddr;
  65     PHYSICAL_ADDRESS PhysicalAddr;
  66     ULONG Size;
  67 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
  68
  69
  70 /* QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN */
  71 typedef struct _QETD_TOKEN_BITS
  72 {
  73     ULONG PingState:1;
  74     ULONG SplitTransactionState:1;
  75     ULONG MissedMicroFrame:1;
  76     ULONG TransactionError:1;
  77     ULONG BabbleDetected:1;
  78     ULONG DataBufferError:1;
  79     ULONG Halted:1;
  80     ULONG Active:1;
  81     ULONG PIDCode:2;
  82     ULONG ErrorCounter:2;
  83     ULONG CurrentPage:3;
  84     ULONG InterruptOnComplete:1;
  85     ULONG TotalBytesToTransfer:15;
  86     ULONG DataToggle:1;
  87 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
  88
  89 /* QUEUE ELEMENT TRANSFER DESCRIPTOR */
  90 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
  91 {
  92     //Hardware
  93     ULONG NextPointer;
  94     ULONG AlternateNextPointer;
  95     union
  96     {
  97         QETD_TOKEN_BITS Bits;
  98         ULONG DWord;
  99     } Token;
 100     ULONG BufferPointer[5];
 101
 102     //Software
 103     ULONG PhysicalAddr;
 104     struct _QUEUE_TRANSFER_DESCRIPTOR *PreviousDescriptor;
 105     struct _QUEUE_TRANSFER_DESCRIPTOR *NextDescriptor;
 106 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 107
 108 /* EndPointSpeeds of END_POINT_CHARACTERISTICS */
 109 #define QH_ENDPOINT_FULLSPEED       0x00
 110 #define QH_ENDPOINT_LOWSPEED        0x01
 111 #define QH_ENDPOINT_HIGHSPEED       0x02
 112
 113 typedef struct _END_POINT_CHARACTERISTICS
 114 {
 115     ULONG DeviceAddress:7;
 116     ULONG InactiveOnNextTransaction:1;
 117     ULONG EndPointNumber:4;
 118     ULONG EndPointSpeed:2;
 119     ULONG QEDTDataToggleControl:1;
 120     ULONG HeadOfReclamation:1;
 121     ULONG MaximumPacketLength:11;
 122     ULONG ControlEndPointFlag:1;
 123     ULONG NakCountReload:4;
 124 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 125
 126 typedef struct _END_POINT_CAPABILITIES
 127 {
 128     ULONG InterruptScheduleMask:8;
 129     ULONG SplitCompletionMask:8;
 130     ULONG HubAddr:6;
 131     ULONG PortNumber:6;
 132     /* Multi */
 133     ULONG NumberOfTransactionPerFrame:2;
 134 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 135
 136
 137 /* QUEUE HEAD defines and structs */
 138
 139 /* QUEUE HEAD Select Types, OR with QUEUE_HEAD HorizontalLinkPointer */
 140 #define QH_TYPE_IDT         0x00
 141 #define QH_TYPE_QH          0x02
 142 #define QH_TYPE_SITD            0x04
 143 #define QH_TYPE_FSTN            0x06
 144
 145 /* QUEUE HEAD */
 146 typedef struct _QUEUE_HEAD
 147 {
 148     //Hardware
 149     ULONG HorizontalLinkPointer;
 150     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 151     END_POINT_CAPABILITIES EndPointCapabilities;
 152     /* TERMINATE_POINTER not valid for this member */
 153     ULONG CurrentLinkPointer;
 154     /* TERMINATE_POINTER valid */
 155     ULONG NextPointer;
 156     /* TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTER */
 157     ULONG AlternateNextPointer;
 158     /* Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid */
 159     union
 160     {
 161         QETD_TOKEN_BITS Bits;
 162         ULONG DWord;
 163     } Token;
 164     ULONG BufferPointer[5];
 165
 166     //Software
 167     ULONG PhysicalAddr;
 168     struct _QUEUE_HEAD *PreviousQueueHead;
 169     struct _QUEUE_HEAD *NextQueueHead;
 170     PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
 171     PIRP IrpToComplete;
 172         PMDL MdlToFree;
 173     PKEVENT Event;
 174 } QUEUE_HEAD, *PQUEUE_HEAD;
 175
 176 /* USBCMD register 32 bits */
 177 typedef struct _EHCI_USBCMD_CONTENT
 178 {
 179     ULONG Run : 1;
 180     ULONG HCReset : 1;
 181     ULONG FrameListSize : 2;
 182     ULONG PeriodicEnable : 1;
 183     ULONG AsyncEnable : 1;
 184     ULONG DoorBell : 1;
 185     ULONG LightReset : 1;
 186     ULONG AsyncParkCount : 2;
 187     ULONG Reserved : 1;
 188     ULONG AsyncParkEnable : 1;
 189     ULONG Reserved1 : 4;
 190     ULONG IntThreshold : 8;
 191     ULONG Reserved2 : 8;
 192
 193 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 194
 195 typedef struct _EHCI_USBSTS_CONTENT
 196 {
 197     ULONG USBInterrupt:1;
 198     ULONG ErrorInterrupt:1;
 199     ULONG DetectChangeInterrupt:1;
 200     ULONG FrameListRolloverInterrupt:1;
 201     ULONG HostSystemErrorInterrupt:1;
 202     ULONG AsyncAdvanceInterrupt:1;
 203     ULONG Reserved:6;
 204     ULONG HCHalted:1;
 205     ULONG Reclamation:1;
 206     ULONG PeriodicScheduleStatus:1;
 207     ULONG AsynchronousScheduleStatus:1;
 208 } EHCI_USBSTS_CONTEXT, *PEHCI_USBSTS_CONTEXT;
 209
 210 typedef struct _EHCI_USBPORTSC_CONTENT
 211 {
 212     ULONG CurrentConnectStatus:1;
 213     ULONG ConnectStatusChange:1;
 214     ULONG PortEnabled:1;
 215     ULONG PortEnableChanged:1;
 216     ULONG OverCurrentActive:1;
 217     ULONG OverCurrentChange:1;
 218     ULONG ForcePortResume:1;
 219     ULONG Suspend:1;
 220     ULONG PortReset:1;
 221     ULONG Reserved:1;
 222     ULONG LineStatus:2;
 223     ULONG PortPower:1;
 224     ULONG PortOwner:1;
 225 } EHCI_USBPORTSC_CONTENT, *PEHCI_USBPORTSC_CONTENT;
 226
 227 typedef struct _EHCI_HCS_CONTENT
 228 {
 229     ULONG PortCount : 4;
 230     ULONG PortPowerControl: 1;
 231     ULONG Reserved : 2;
 232     ULONG PortRouteRules : 1;
 233     ULONG PortPerCHC : 4;
 234     ULONG CHCCount : 4;
 235     ULONG PortIndicator : 1;
 236     ULONG Reserved2 : 3;
 237     ULONG DbgPortNum : 4;
 238     ULONG Reserved3 : 8;
 239
 240 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 241
 242 typedef struct _EHCI_HCC_CONTENT
 243 {
 244     ULONG CurAddrBits : 1;
 245     ULONG VarFrameList : 1;
 246     ULONG ParkMode : 1;
 247     ULONG Reserved : 1;
 248     ULONG IsoSchedThreshold : 4;
 249     ULONG EECPCapable : 8;
 250     ULONG Reserved2 : 16;
 251
 252 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 253
 254 typedef struct _EHCI_CAPS {
 255     UCHAR Length;
 256     UCHAR Reserved;
 257     USHORT HCIVersion;
 258     union
 259     {
 260         EHCI_HCS_CONTENT HCSParams;
 261         ULONG HCSParamsLong;
 262     };
 263     ULONG HCCParams;
 264     UCHAR PortRoute [8];
 265 } EHCI_CAPS, *PEHCI_CAPS;
 266
 267 typedef struct _EHCI_HOST_CONTROLLER
 268 {
 269     ULONG OpRegisters;
 270     EHCI_CAPS ECHICaps;
 271     PVOID CommonBufferVA;
 272     PHYSICAL_ADDRESS CommonBufferPA;
 273     ULONG CommonBufferSize;
 274     PQUEUE_HEAD AsyncListQueue;
 275     KSPIN_LOCK Lock;
 276 } EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
 277
 278 ULONG
 279 ReadControllerStatus(PEHCI_HOST_CONTROLLER hcd);
 280
 281 VOID
 282 ClearControllerStatus(PEHCI_HOST_CONTROLLER hcd, ULONG Status);
 283
 284 VOID
 285 GetCapabilities(PEHCI_CAPS PCap, ULONG CapRegister);
 286
 287 VOID
 288 ResetPort(PEHCI_HOST_CONTROLLER hcd, UCHAR Port);
 289
 290 VOID
 291 StartEhci(PEHCI_HOST_CONTROLLER hcd);
 292
 293 VOID
 294 StopEhci(PEHCI_HOST_CONTROLLER hcd);
 295
 296 VOID
 297 SetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr);
 298
 299 ULONG
 300 GetAsyncListQueueRegister(PEHCI_HOST_CONTROLLER hcd);
 301
 302 VOID
 303 SetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd, ULONG PhysicalAddr);
 304
 305 ULONG
 306 GetPeriodicFrameListRegister(PEHCI_HOST_CONTROLLER hcd);
 307