[EHCI]
[reactos.git] / drivers / usb / usbehci_new / hardware.cpp
1 /*
2 * PROJECT: ReactOS Universal Serial Bus Bulk Enhanced Host Controller Interface
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: drivers/usb/usbehci/hcd_controller.cpp
5 * PURPOSE: USB EHCI device driver.
6 * PROGRAMMERS:
7 * Michael Martin (michael.martin@reactos.org)
8 * Johannes Anderwald (johannes.anderwald@reactos.org)
9 */
10
11 #define INITGUID
12 #include "usbehci.h"
13 #include "hardware.h"
14
15 typedef VOID __stdcall HD_INIT_CALLBACK(IN PVOID CallBackContext);
16
17 BOOLEAN
18 NTAPI
19 InterruptServiceRoutine(
20 IN PKINTERRUPT Interrupt,
21 IN PVOID ServiceContext);
22
23 VOID
24 NTAPI
25 EhciDefferedRoutine(
26 IN PKDPC Dpc,
27 IN PVOID DeferredContext,
28 IN PVOID SystemArgument1,
29 IN PVOID SystemArgument2);
30
31 VOID
32 NTAPI
33 StatusChangeWorkItemRoutine(PVOID Context);
34
35 class CUSBHardwareDevice : public IUSBHardwareDevice
36 {
37 public:
38 STDMETHODIMP QueryInterface( REFIID InterfaceId, PVOID* Interface);
39
40 STDMETHODIMP_(ULONG) AddRef()
41 {
42 InterlockedIncrement(&m_Ref);
43 return m_Ref;
44 }
45 STDMETHODIMP_(ULONG) Release()
46 {
47 InterlockedDecrement(&m_Ref);
48
49 if (!m_Ref)
50 {
51 delete this;
52 return 0;
53 }
54 return m_Ref;
55 }
56 // com
57 NTSTATUS Initialize(PDRIVER_OBJECT DriverObject, PDEVICE_OBJECT FunctionalDeviceObject, PDEVICE_OBJECT PhysicalDeviceObject, PDEVICE_OBJECT LowerDeviceObject);
58 NTSTATUS PnpStart(PCM_RESOURCE_LIST RawResources, PCM_RESOURCE_LIST TranslatedResources);
59 NTSTATUS PnpStop(void);
60 NTSTATUS HandlePower(PIRP Irp);
61 NTSTATUS GetDeviceDetails(PUSHORT VendorId, PUSHORT DeviceId, PULONG NumberOfPorts, PULONG Speed);
62 NTSTATUS GetDMA(OUT struct IDMAMemoryManager **m_DmaManager);
63 NTSTATUS GetUSBQueue(OUT struct IUSBQueue **OutUsbQueue);
64
65 NTSTATUS StartController();
66 NTSTATUS StopController();
67 NTSTATUS ResetController();
68 NTSTATUS ResetPort(ULONG PortIndex);
69
70 NTSTATUS GetPortStatus(ULONG PortId, OUT USHORT *PortStatus, OUT USHORT *PortChange);
71 NTSTATUS ClearPortStatus(ULONG PortId, ULONG Status);
72 NTSTATUS SetPortFeature(ULONG PortId, ULONG Feature);
73
74 VOID SetAsyncListRegister(ULONG PhysicalAddress);
75 VOID SetPeriodicListRegister(ULONG PhysicalAddress);
76 struct _QUEUE_HEAD * GetAsyncListQueueHead();
77 ULONG GetPeriodicListRegister();
78
79 VOID SetStatusChangeEndpointCallBack(PVOID CallBack, PVOID Context);
80
81 KIRQL AcquireDeviceLock(void);
82 VOID ReleaseDeviceLock(KIRQL OldLevel);
83 // set command
84 VOID SetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd);
85
86 // get command
87 VOID GetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd);
88
89
90 // local
91 BOOLEAN InterruptService();
92
93 // friend function
94 friend BOOLEAN NTAPI InterruptServiceRoutine(IN PKINTERRUPT Interrupt, IN PVOID ServiceContext);
95 friend VOID NTAPI EhciDefferedRoutine(IN PKDPC Dpc, IN PVOID DeferredContext, IN PVOID SystemArgument1, IN PVOID SystemArgument2);
96 friend VOID NTAPI StatusChangeWorkItemRoutine(PVOID Context);
97 // constructor / destructor
98 CUSBHardwareDevice(IUnknown *OuterUnknown){}
99 virtual ~CUSBHardwareDevice(){}
100
101 protected:
102 LONG m_Ref; // reference count
103 PDRIVER_OBJECT m_DriverObject; // driver object
104 PDEVICE_OBJECT m_PhysicalDeviceObject; // pdo
105 PDEVICE_OBJECT m_FunctionalDeviceObject; // fdo (hcd controller)
106 PDEVICE_OBJECT m_NextDeviceObject; // lower device object
107 KSPIN_LOCK m_Lock; // hardware lock
108 PKINTERRUPT m_Interrupt; // interrupt object
109 KDPC m_IntDpcObject; // dpc object for deferred isr processing
110 PVOID VirtualBase; // virtual base for memory manager
111 PHYSICAL_ADDRESS PhysicalAddress; // physical base for memory manager
112 PULONG m_Base; // EHCI operational port base registers
113 PDMA_ADAPTER m_Adapter; // dma adapter object
114 ULONG m_MapRegisters; // map registers count
115 EHCI_CAPS m_Capabilities; // EHCI caps
116 USHORT m_VendorID; // vendor id
117 USHORT m_DeviceID; // device id
118 PQUEUE_HEAD AsyncQueueHead; // async queue head terminator
119 PUSBQUEUE m_UsbQueue; // usb request queue
120 PDMAMEMORYMANAGER m_MemoryManager; // memory manager
121 HD_INIT_CALLBACK* m_SCECallBack; // status change callback routine
122 PVOID m_SCEContext; // status change callback routine context
123 BOOLEAN m_DoorBellRingInProgress; // door bell ring in progress
124 WORK_QUEUE_ITEM m_StatusChangeWorkItem; // work item for status change callback
125 ULONG m_SyncFramePhysAddr; // periodic frame list physical address
126 BOOLEAN m_ResetInProgress[16]; // set when a reset is in progress
127 BUS_INTERFACE_STANDARD m_BusInterface; // pci bus interface
128
129 // read register
130 ULONG EHCI_READ_REGISTER_ULONG(ULONG Offset);
131
132 // write register
133 VOID EHCI_WRITE_REGISTER_ULONG(ULONG Offset, ULONG Value);
134 };
135
136 //=================================================================================================
137 // COM
138 //
139 NTSTATUS
140 STDMETHODCALLTYPE
141 CUSBHardwareDevice::QueryInterface(
142 IN REFIID refiid,
143 OUT PVOID* Output)
144 {
145 if (IsEqualGUIDAligned(refiid, IID_IUnknown))
146 {
147 *Output = PVOID(PUNKNOWN(this));
148 PUNKNOWN(*Output)->AddRef();
149 return STATUS_SUCCESS;
150 }
151
152 return STATUS_UNSUCCESSFUL;
153 }
154
155 NTSTATUS
156 CUSBHardwareDevice::Initialize(
157 PDRIVER_OBJECT DriverObject,
158 PDEVICE_OBJECT FunctionalDeviceObject,
159 PDEVICE_OBJECT PhysicalDeviceObject,
160 PDEVICE_OBJECT LowerDeviceObject)
161 {
162 PCI_COMMON_CONFIG PciConfig;
163 NTSTATUS Status;
164 ULONG BytesRead;
165
166 DPRINT1("CUSBHardwareDevice::Initialize\n");
167
168 //
169 // Create DMAMemoryManager for use with QueueHeads and Transfer Descriptors.
170 //
171 Status = CreateDMAMemoryManager(&m_MemoryManager);
172 if (!NT_SUCCESS(Status))
173 {
174 DPRINT1("Failed to create DMAMemoryManager Object\n");
175 return Status;
176 }
177
178 //
179 // Create the UsbQueue class that will handle the Asynchronous and Periodic Schedules
180 //
181 Status = CreateUSBQueue(&m_UsbQueue);
182 if (!NT_SUCCESS(Status))
183 {
184 DPRINT1("Failed to create UsbQueue!\n");
185 return Status;
186 }
187
188 //
189 // store device objects
190 //
191 m_DriverObject = DriverObject;
192 m_FunctionalDeviceObject = FunctionalDeviceObject;
193 m_PhysicalDeviceObject = PhysicalDeviceObject;
194 m_NextDeviceObject = LowerDeviceObject;
195
196 //
197 // initialize device lock
198 //
199 KeInitializeSpinLock(&m_Lock);
200
201 //
202 // intialize status change work item
203 //
204 ExInitializeWorkItem(&m_StatusChangeWorkItem, StatusChangeWorkItemRoutine, PVOID(this));
205
206 m_VendorID = 0;
207 m_DeviceID = 0;
208
209 Status = GetBusInterface(PhysicalDeviceObject, &m_BusInterface);
210 if (!NT_SUCCESS(Status))
211 {
212 DPRINT1("Failed to get BusInteface!\n");
213 return Status;
214 }
215
216 BytesRead = (*m_BusInterface.GetBusData)(m_BusInterface.Context,
217 PCI_WHICHSPACE_CONFIG,
218 &PciConfig,
219 0,
220 PCI_COMMON_HDR_LENGTH);
221
222 if (BytesRead != PCI_COMMON_HDR_LENGTH)
223 {
224 DPRINT1("Failed to get pci config information!\n");
225 return STATUS_SUCCESS;
226 }
227
228 m_VendorID = PciConfig.VendorID;
229 m_DeviceID = PciConfig.DeviceID;
230
231
232 if (PciConfig.Command & PCI_ENABLE_BUS_MASTER)
233 {
234 //
235 // master is enabled
236 //
237 return STATUS_SUCCESS;
238 }
239
240 DPRINT1("PCI Configuration shows this as a non Bus Mastering device! Enabling...\n");
241
242 PciConfig.Command |= PCI_ENABLE_BUS_MASTER;
243 m_BusInterface.SetBusData(m_BusInterface.Context, PCI_WHICHSPACE_CONFIG, &PciConfig, 0, PCI_COMMON_HDR_LENGTH);
244
245 BytesRead = (*m_BusInterface.GetBusData)(m_BusInterface.Context,
246 PCI_WHICHSPACE_CONFIG,
247 &PciConfig,
248 0,
249 PCI_COMMON_HDR_LENGTH);
250
251 if (BytesRead != PCI_COMMON_HDR_LENGTH)
252 {
253 DPRINT1("Failed to get pci config information!\n");
254 ASSERT(FALSE);
255 return STATUS_SUCCESS;
256 }
257
258 if (!(PciConfig.Command & PCI_ENABLE_BUS_MASTER))
259 {
260 PciConfig.Command |= PCI_ENABLE_BUS_MASTER;
261 DPRINT1("Failed to enable master\n");
262 return STATUS_UNSUCCESSFUL;
263 }
264 return STATUS_SUCCESS;
265 }
266
267 VOID
268 CUSBHardwareDevice::SetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd)
269 {
270 PULONG Register;
271 Register = (PULONG)UsbCmd;
272 WRITE_REGISTER_ULONG((PULONG)((ULONG)m_Base + EHCI_USBCMD), *Register);
273 }
274
275 VOID
276 CUSBHardwareDevice::GetCommandRegister(PEHCI_USBCMD_CONTENT UsbCmd)
277 {
278 PULONG Register;
279 Register = (PULONG)UsbCmd;
280 *Register = READ_REGISTER_ULONG((PULONG)((ULONG)m_Base + EHCI_USBCMD));
281 }
282
283 ULONG
284 CUSBHardwareDevice::EHCI_READ_REGISTER_ULONG(ULONG Offset)
285 {
286 return READ_REGISTER_ULONG((PULONG)((ULONG)m_Base + Offset));
287 }
288
289 VOID
290 CUSBHardwareDevice::EHCI_WRITE_REGISTER_ULONG(ULONG Offset, ULONG Value)
291 {
292 WRITE_REGISTER_ULONG((PULONG)((ULONG)m_Base + Offset), Value);
293 }
294
295 NTSTATUS
296 CUSBHardwareDevice::PnpStart(
297 PCM_RESOURCE_LIST RawResources,
298 PCM_RESOURCE_LIST TranslatedResources)
299 {
300 ULONG Index, Count;
301 PCM_PARTIAL_RESOURCE_DESCRIPTOR ResourceDescriptor;
302 DEVICE_DESCRIPTION DeviceDescription;
303 PHYSICAL_ADDRESS AsyncPhysicalAddress;
304 PVOID ResourceBase;
305 NTSTATUS Status;
306 UCHAR Value;
307 UCHAR PortCount;
308
309 DPRINT1("CUSBHardwareDevice::PnpStart\n");
310 for(Index = 0; Index < TranslatedResources->List[0].PartialResourceList.Count; Index++)
311 {
312 //
313 // get resource descriptor
314 //
315 ResourceDescriptor = &TranslatedResources->List[0].PartialResourceList.PartialDescriptors[Index];
316
317 switch(ResourceDescriptor->Type)
318 {
319 case CmResourceTypeInterrupt:
320 {
321 KeInitializeDpc(&m_IntDpcObject,
322 EhciDefferedRoutine,
323 this);
324
325 Status = IoConnectInterrupt(&m_Interrupt,
326 InterruptServiceRoutine,
327 (PVOID)this,
328 NULL,
329 ResourceDescriptor->u.Interrupt.Vector,
330 (KIRQL)ResourceDescriptor->u.Interrupt.Level,
331 (KIRQL)ResourceDescriptor->u.Interrupt.Level,
332 (KINTERRUPT_MODE)(ResourceDescriptor->Flags & CM_RESOURCE_INTERRUPT_LATCHED),
333 (ResourceDescriptor->ShareDisposition != CmResourceShareDeviceExclusive),
334 ResourceDescriptor->u.Interrupt.Affinity,
335 FALSE);
336
337 if (!NT_SUCCESS(Status))
338 {
339 //
340 // failed to register interrupt
341 //
342 DPRINT1("IoConnect Interrupt failed with %x\n", Status);
343 return Status;
344 }
345 break;
346 }
347 case CmResourceTypeMemory:
348 {
349 //
350 // get resource base
351 //
352 ResourceBase = MmMapIoSpace(ResourceDescriptor->u.Memory.Start, ResourceDescriptor->u.Memory.Length, MmNonCached);
353 if (!ResourceBase)
354 {
355 //
356 // failed to map registers
357 //
358 DPRINT1("MmMapIoSpace failed\n");
359 return STATUS_INSUFFICIENT_RESOURCES;
360 }
361
362 //
363 // Get controllers capabilities
364 //
365 m_Capabilities.Length = READ_REGISTER_UCHAR((PUCHAR)ResourceBase + EHCI_CAPLENGTH);
366 m_Capabilities.HCIVersion = READ_REGISTER_USHORT((PUSHORT)((ULONG)ResourceBase + EHCI_HCIVERSION));
367 m_Capabilities.HCSParamsLong = READ_REGISTER_ULONG((PULONG)((ULONG)ResourceBase + EHCI_HCSPARAMS));
368 m_Capabilities.HCCParamsLong = READ_REGISTER_ULONG((PULONG)((ULONG)ResourceBase + EHCI_HCCPARAMS));
369
370 DPRINT1("Controller has %d Length\n", m_Capabilities.Length);
371 DPRINT1("Controller has %d Ports\n", m_Capabilities.HCSParams.PortCount);
372 DPRINT1("Controller EHCI Version %x\n", m_Capabilities.HCIVersion);
373 DPRINT1("Controler EHCI Caps HCSParamsLong %x\n", m_Capabilities.HCSParamsLong);
374 DPRINT1("Controler EHCI Caps HCCParamsLong %x\n", m_Capabilities.HCCParamsLong);
375 DPRINT1("Controler EHCI Caps PowerControl %x\n", m_Capabilities.HCSParams.PortPowerControl);
376
377 if (m_Capabilities.HCSParams.PortRouteRules)
378 {
379 Count = 0;
380 PortCount = max(m_Capabilities.HCSParams.PortCount/2, (m_Capabilities.HCSParams.PortCount+1)/2);
381 do
382 {
383 //
384 // each entry is a 4 bit field EHCI 2.2.5
385 //
386 Value = READ_REGISTER_UCHAR((PUCHAR)(ULONG)ResourceBase + EHCI_HCSP_PORTROUTE + Count);
387 m_Capabilities.PortRoute[Count*2] = (Value & 0xF0);
388
389 if ((Count*2) + 1 < m_Capabilities.HCSParams.PortCount)
390 m_Capabilities.PortRoute[(Count*2)+1] = (Value & 0x0F);
391
392 Count++;
393 }while(Count < PortCount);
394 }
395
396 //
397 // Set m_Base to the address of Operational Register Space
398 //
399 m_Base = (PULONG)((ULONG)ResourceBase + m_Capabilities.Length);
400 break;
401 }
402 }
403 }
404
405
406 //
407 // zero device description
408 //
409 RtlZeroMemory(&DeviceDescription, sizeof(DEVICE_DESCRIPTION));
410
411 //
412 // initialize device description
413 //
414 DeviceDescription.Version = DEVICE_DESCRIPTION_VERSION;
415 DeviceDescription.Master = TRUE;
416 DeviceDescription.ScatterGather = TRUE;
417 DeviceDescription.Dma32BitAddresses = TRUE;
418 DeviceDescription.DmaWidth = Width32Bits;
419 DeviceDescription.InterfaceType = PCIBus;
420 DeviceDescription.MaximumLength = MAXULONG;
421
422 //
423 // get dma adapter
424 //
425 m_Adapter = IoGetDmaAdapter(m_PhysicalDeviceObject, &DeviceDescription, &m_MapRegisters);
426 if (!m_Adapter)
427 {
428 //
429 // failed to get dma adapter
430 //
431 DPRINT1("Failed to acquire dma adapter\n");
432 return STATUS_INSUFFICIENT_RESOURCES;
433 }
434
435 //
436 // Create Common Buffer
437 //
438 VirtualBase = m_Adapter->DmaOperations->AllocateCommonBuffer(m_Adapter,
439 PAGE_SIZE * 4,
440 &PhysicalAddress,
441 FALSE);
442 if (!VirtualBase)
443 {
444 DPRINT1("Failed to allocate a common buffer\n");
445 return STATUS_INSUFFICIENT_RESOURCES;
446 }
447
448 //
449 // Stop the controller before modifying schedules
450 //
451 Status = StopController();
452 if (!NT_SUCCESS(Status))
453 return Status;
454
455 //
456 // Initialize the DMAMemoryManager
457 //
458 Status = m_MemoryManager->Initialize(this, &m_Lock, PAGE_SIZE * 4, VirtualBase, PhysicalAddress, 32);
459 if (!NT_SUCCESS(Status))
460 {
461 DPRINT1("Failed to initialize the DMAMemoryManager\n");
462 return Status;
463 }
464
465 //
466 // Create a queuehead for the Async Register
467 //
468 m_MemoryManager->Allocate(sizeof(QUEUE_HEAD), (PVOID*)&AsyncQueueHead, &AsyncPhysicalAddress);
469
470 AsyncQueueHead->AlternateNextPointer = TERMINATE_POINTER;
471 AsyncQueueHead->NextPointer = TERMINATE_POINTER;
472 AsyncQueueHead->PhysicalAddr = AsyncPhysicalAddress.LowPart;
473 AsyncQueueHead->HorizontalLinkPointer = AsyncQueueHead->PhysicalAddr | QH_TYPE_QH;
474 AsyncQueueHead->EndPointCharacteristics.QEDTDataToggleControl = FALSE;
475 AsyncQueueHead->Token.Bits.InterruptOnComplete = FALSE;
476 AsyncQueueHead->EndPointCharacteristics.HeadOfReclamation = TRUE;
477 AsyncQueueHead->Token.Bits.Halted = TRUE;
478 AsyncQueueHead->EndPointCharacteristics.MaximumPacketLength = 64;
479 AsyncQueueHead->EndPointCharacteristics.NakCountReload = 0;
480 AsyncQueueHead->EndPointCharacteristics.EndPointSpeed = QH_ENDPOINT_HIGHSPEED;
481 AsyncQueueHead->EndPointCapabilities.NumberOfTransactionPerFrame = 0x03;
482
483 InitializeListHead(&AsyncQueueHead->LinkedQueueHeads);
484
485 //
486 // Initialize the UsbQueue now that we have an AdapterObject.
487 //
488 Status = m_UsbQueue->Initialize(PUSBHARDWAREDEVICE(this), m_Adapter, m_MemoryManager, &m_Lock);
489 if (!NT_SUCCESS(Status))
490 {
491 DPRINT1("Failed to Initialize the UsbQueue\n");
492 return Status;
493 }
494
495 //
496 // Start the controller
497 //
498 DPRINT1("Starting Controller\n");
499 Status = StartController();
500
501 //
502 // done
503 //
504 return Status;
505 }
506
507 NTSTATUS
508 CUSBHardwareDevice::PnpStop(void)
509 {
510 UNIMPLEMENTED
511 return STATUS_NOT_IMPLEMENTED;
512 }
513
514 NTSTATUS
515 CUSBHardwareDevice::HandlePower(
516 PIRP Irp)
517 {
518 UNIMPLEMENTED
519 return STATUS_NOT_IMPLEMENTED;
520 }
521
522 NTSTATUS
523 CUSBHardwareDevice::GetDeviceDetails(
524 OUT OPTIONAL PUSHORT VendorId,
525 OUT OPTIONAL PUSHORT DeviceId,
526 OUT OPTIONAL PULONG NumberOfPorts,
527 OUT OPTIONAL PULONG Speed)
528 {
529 if (VendorId)
530 *VendorId = m_VendorID;
531 if (DeviceId)
532 *DeviceId = m_DeviceID;
533 if (NumberOfPorts)
534 *NumberOfPorts = m_Capabilities.HCSParams.PortCount;
535 //FIXME: What to returned here?
536 if (Speed)
537 *Speed = 0x200;
538 return STATUS_SUCCESS;
539 }
540
541 NTSTATUS CUSBHardwareDevice::GetDMA(
542 OUT struct IDMAMemoryManager **OutDMAMemoryManager)
543 {
544 if (!m_MemoryManager)
545 return STATUS_UNSUCCESSFUL;
546 *OutDMAMemoryManager = m_MemoryManager;
547 return STATUS_SUCCESS;
548 }
549
550 NTSTATUS
551 CUSBHardwareDevice::GetUSBQueue(
552 OUT struct IUSBQueue **OutUsbQueue)
553 {
554 if (!m_UsbQueue)
555 return STATUS_UNSUCCESSFUL;
556 *OutUsbQueue = m_UsbQueue;
557 return STATUS_SUCCESS;
558 }
559
560
561 NTSTATUS
562 CUSBHardwareDevice::StartController(void)
563 {
564 EHCI_USBCMD_CONTENT UsbCmd;
565 ULONG UsbSts, FailSafe, ExtendedCapsSupport, Caps, Index;
566 UCHAR Value;
567 LARGE_INTEGER Timeout;
568
569 //
570 // check caps
571 //
572 if (m_Capabilities.HCCParams.CurAddrBits)
573 {
574 //
575 // disable 64-bit addressing
576 //
577 EHCI_WRITE_REGISTER_ULONG(EHCI_CTRLDSSEGMENT, 0x0);
578 }
579
580 //
581 // are extended caps supported
582 //
583 ExtendedCapsSupport = (m_Capabilities.HCCParamsLong >> EHCI_ECP_SHIFT) & EHCI_ECP_MASK;
584 if (ExtendedCapsSupport)
585 {
586 DPRINT1("[EHCI] Extended Caps Support detected!\n");
587
588 //
589 // sanity check
590 //
591 ASSERT(ExtendedCapsSupport >= PCI_COMMON_HDR_LENGTH);
592 m_BusInterface.GetBusData(m_BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Caps, ExtendedCapsSupport, sizeof(ULONG));
593
594 //
595 // OS Handoff Synchronization support capability. EHCI 5.1
596 //
597 if ((Caps & EHCI_LEGSUP_CAPID_MASK) == EHCI_LEGSUP_CAPID)
598 {
599 //
600 // is it bios owned
601 //
602 if ((Caps & EHCI_LEGSUP_BIOSOWNED))
603 {
604 DPRINT1("[EHCI] Controller is BIOS owned, acquring control\n");
605
606 //
607 // acquire ownership
608 //
609 Value = 1;
610 m_BusInterface.SetBusData(m_BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, ExtendedCapsSupport+3, sizeof(UCHAR));
611
612 for(Index = 0; Index < 20; Index++)
613 {
614 //
615 // get status
616 //
617 m_BusInterface.GetBusData(m_BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Caps, ExtendedCapsSupport, sizeof(ULONG));
618 if ((Caps & EHCI_LEGSUP_BIOSOWNED))
619 {
620 //
621 // lets wait a bit
622 //
623 Timeout.QuadPart = 50;
624 DPRINT1("Waiting %d milliseconds for port reset\n", Timeout.LowPart);
625
626 //
627 // convert to 100 ns units (absolute)
628 //
629 Timeout.QuadPart *= -10000;
630
631 //
632 // perform the wait
633 //
634 KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
635 }
636 }
637 if ((Caps & EHCI_LEGSUP_BIOSOWNED))
638 {
639 //
640 // failed to aquire ownership
641 //
642 DPRINT1("[EHCI] failed to acquire ownership\n");
643 }
644 else if ((Caps & EHCI_LEGSUP_OSOWNED))
645 {
646 //
647 // HC OS Owned Semaphore EHCI 2.1.7
648 //
649 DPRINT1("[EHCI] acquired ownership\n");
650 }
651
652 //
653 // explictly clear the bios owned flag 2.1.7
654 //
655 Value = 0;
656 m_BusInterface.SetBusData(m_BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Value, ExtendedCapsSupport+2, sizeof(UCHAR));
657
658 //
659 // clear SMI interrupt EHCI 2.1.8
660 //
661 Caps = 4;
662 m_BusInterface.SetBusData(m_BusInterface.Context, PCI_WHICHSPACE_CONFIG, &Caps, ExtendedCapsSupport+4, sizeof(ULONG));
663
664
665 }
666 }
667 }
668
669
670
671 #if 1
672 //
673 // Stop the controller if its running
674 //
675 UsbSts = EHCI_READ_REGISTER_ULONG(EHCI_USBSTS);
676 if (!(UsbSts & EHCI_STS_HALT))
677 {
678 DPRINT1("Stopping Controller %x\n", UsbSts);
679 StopController();
680 }
681 #endif
682
683 //
684 // Enable Interrupts and start execution
685 //
686 ULONG Mask = EHCI_USBINTR_INTE | EHCI_USBINTR_ERR | EHCI_USBINTR_ASYNC | EHCI_USBINTR_HSERR | EHCI_USBINTR_PC;
687 EHCI_WRITE_REGISTER_ULONG(EHCI_USBINTR, Mask);
688
689 KeStallExecutionProcessor(10);
690
691 ULONG Status = EHCI_READ_REGISTER_ULONG(EHCI_USBINTR);
692
693 DPRINT1("Interrupt Mask %x\n", Status);
694 ASSERT((Status & Mask) == Mask);
695
696
697 //
698 // Assign the SyncList Register
699 //
700 EHCI_WRITE_REGISTER_ULONG(EHCI_PERIODICLISTBASE, m_SyncFramePhysAddr);
701
702 //
703 // Set Schedules to Enable and Interrupt Threshold to 1ms.
704 //
705 RtlZeroMemory(&UsbCmd, sizeof(EHCI_USBCMD_CONTENT));
706
707 UsbCmd.PeriodicEnable = TRUE;
708 UsbCmd.IntThreshold = 0x8; //1ms
709 UsbCmd.Run = TRUE;
710 UsbCmd.FrameListSize = 0x0; //1024
711 SetCommandRegister(&UsbCmd);
712
713 //
714 // Wait for execution to start
715 //
716 for (FailSafe = 100; FailSafe > 1; FailSafe--)
717 {
718 KeStallExecutionProcessor(10);
719 UsbSts = EHCI_READ_REGISTER_ULONG(EHCI_USBSTS);
720
721 if (!(UsbSts & EHCI_STS_HALT))
722 {
723 break;
724 }
725 }
726
727
728 if (UsbSts & EHCI_STS_HALT)
729 {
730 DPRINT1("Could not start execution on the controller\n");
731 return STATUS_UNSUCCESSFUL;
732 }
733
734 //
735 // Assign the AsyncList Register
736 //
737 EHCI_WRITE_REGISTER_ULONG(EHCI_ASYNCLISTBASE, AsyncQueueHead->PhysicalAddr);
738
739 //
740 // get command register
741 //
742 GetCommandRegister(&UsbCmd);
743
744 //
745 // preserve bits
746 //
747 UsbCmd.AsyncEnable = TRUE;
748
749 //
750 // enable async
751 //
752 SetCommandRegister(&UsbCmd);
753
754 //
755 // Wait for execution to start
756 //
757 for (FailSafe = 100; FailSafe > 1; FailSafe--)
758 {
759 KeStallExecutionProcessor(10);
760 UsbSts = EHCI_READ_REGISTER_ULONG(EHCI_USBSTS);
761
762 if ((UsbSts & EHCI_STS_ASS))
763 {
764 break;
765 }
766 }
767
768 if (!(UsbSts & EHCI_STS_ASS))
769 {
770 DPRINT1("Failed to enable async schedule UsbSts %x\n", UsbSts);
771 ASSERT(FALSE);
772 return STATUS_UNSUCCESSFUL;
773 }
774
775 DPRINT1("UsbSts %x\n", UsbSts);
776 GetCommandRegister(&UsbCmd);
777
778 DPRINT1("UsbCmd.PeriodicEnable %x\n", UsbCmd.PeriodicEnable);
779 DPRINT1("UsbCmd.AsyncEnable %x\n", UsbCmd.AsyncEnable);
780 DPRINT1("UsbCmd.IntThreshold %x\n", UsbCmd.IntThreshold);
781 DPRINT1("UsbCmd.Run %x\n", UsbCmd.Run);
782 DPRINT1("UsbCmd.FrameListSize %x\n", UsbCmd.FrameListSize);
783
784 //
785 // Set port routing to EHCI controller
786 //
787 EHCI_WRITE_REGISTER_ULONG(EHCI_CONFIGFLAG, 1);
788
789 DPRINT1("EHCI Started!\n");
790 return STATUS_SUCCESS;
791 }
792
793 NTSTATUS
794 CUSBHardwareDevice::StopController(void)
795 {
796 EHCI_USBCMD_CONTENT UsbCmd;
797 ULONG UsbSts, FailSafe;
798
799 //
800 // Disable Interrupts and stop execution
801 //
802 EHCI_WRITE_REGISTER_ULONG (EHCI_USBINTR, 0);
803
804 GetCommandRegister(&UsbCmd);
805 UsbCmd.Run = FALSE;
806 SetCommandRegister(&UsbCmd);
807
808 for (FailSafe = 100; FailSafe > 1; FailSafe--)
809 {
810 KeStallExecutionProcessor(10);
811 UsbSts = EHCI_READ_REGISTER_ULONG(EHCI_USBSTS);
812 if (UsbSts & EHCI_STS_HALT)
813 {
814 break;
815 }
816 }
817
818 if (!(UsbSts & EHCI_STS_HALT))
819 {
820 DPRINT1("EHCI ERROR: Controller is not responding to Stop request!\n");
821 return STATUS_UNSUCCESSFUL;
822 }
823
824 return STATUS_SUCCESS;
825 }
826
827 NTSTATUS
828 CUSBHardwareDevice::ResetController(void)
829 {
830 UNIMPLEMENTED
831 return STATUS_NOT_IMPLEMENTED;
832 }
833
834 NTSTATUS
835 CUSBHardwareDevice::ResetPort(
836 IN ULONG PortIndex)
837 {
838 ULONG PortStatus;
839 LARGE_INTEGER Timeout;
840
841 if (PortIndex > m_Capabilities.HCSParams.PortCount)
842 return STATUS_UNSUCCESSFUL;
843
844 PortStatus = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex));
845 //
846 // check slow speed line before reset
847 //
848 if (PortStatus & EHCI_PRT_SLOWSPEEDLINE)
849 {
850 DPRINT1("Non HighSpeed device. Releasing Ownership\n");
851 EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex), EHCI_PRT_RELEASEOWNERSHIP);
852 return STATUS_DEVICE_NOT_CONNECTED;
853 }
854
855 ASSERT(PortStatus & EHCI_PRT_CONNECTED);
856
857 //
858 // Reset and clean enable
859 //
860 PortStatus |= EHCI_PRT_RESET;
861 PortStatus &= ~EHCI_PRT_ENABLED;
862 EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex), PortStatus);
863
864 //
865 // delay is 20 ms for port reset as per USB 2.0 spec
866 //
867 Timeout.QuadPart = 20;
868 DPRINT1("Waiting %d milliseconds for port reset\n", Timeout.LowPart);
869
870 //
871 // convert to 100 ns units (absolute)
872 //
873 Timeout.QuadPart *= -10000;
874
875 //
876 // perform the wait
877 //
878 KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
879
880 //
881 // Clear reset
882 //
883 PortStatus = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex));
884 PortStatus &= ~EHCI_PRT_RESET;
885 EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex), PortStatus);
886
887 do
888 {
889 //
890 // wait
891 //
892 KeStallExecutionProcessor(100);
893
894 //
895 // Check that the port reset
896 //
897 PortStatus = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex));
898 if (!(PortStatus & EHCI_PRT_RESET))
899 break;
900 } while (TRUE);
901
902 //
903 // delay is 10 ms
904 //
905 Timeout.QuadPart = 10;
906 DPRINT1("Waiting %d milliseconds for port to recover after reset\n", Timeout.LowPart);
907
908 //
909 // convert to 100 ns units (absolute)
910 //
911 Timeout.QuadPart *= -10000;
912
913 //
914 // perform the wait
915 //
916 KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
917
918 //
919 // check slow speed line after reset
920 //
921 PortStatus = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex));
922 if (PortStatus & EHCI_PRT_SLOWSPEEDLINE)
923 {
924 DPRINT1("Non HighSpeed device. Releasing Ownership\n");
925 EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC + (4 * PortIndex), EHCI_PRT_RELEASEOWNERSHIP);
926 return STATUS_DEVICE_NOT_CONNECTED;
927 }
928
929 //
930 // this must be enabled now
931 //
932 ASSERT(PortStatus & EHCI_PRT_ENABLED);
933
934 return STATUS_SUCCESS;
935 }
936
937 NTSTATUS
938 CUSBHardwareDevice::GetPortStatus(
939 ULONG PortId,
940 OUT USHORT *PortStatus,
941 OUT USHORT *PortChange)
942 {
943 ULONG Value;
944 USHORT Status = 0, Change = 0;
945
946 if (PortId > m_Capabilities.HCSParams.PortCount)
947 return STATUS_UNSUCCESSFUL;
948
949 //
950 // Get the value of the Port Status and Control Register
951 //
952 Value = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortId));
953
954 //
955 // If the PowerPortControl is 0 then host controller does not have power control switches
956 if (!m_Capabilities.HCSParams.PortPowerControl)
957 {
958 Status |= USB_PORT_STATUS_POWER;
959 }
960 else
961 {
962 // Check the value of PortPower
963 if (Value & EHCI_PRT_POWER)
964 {
965 Status |= USB_PORT_STATUS_POWER;
966 }
967 }
968
969 // Get Connected Status
970 if (Value & EHCI_PRT_CONNECTED)
971 {
972 Status |= USB_PORT_STATUS_CONNECT;
973
974 // Get Speed. If SlowSpeedLine flag is there then its a slow speed device
975 if (Value & EHCI_PRT_SLOWSPEEDLINE)
976 Status |= USB_PORT_STATUS_LOW_SPEED;
977 else
978 Status |= USB_PORT_STATUS_HIGH_SPEED;
979 }
980
981 // Get Enabled Status
982 if (Value & EHCI_PRT_ENABLED)
983 Status |= USB_PORT_STATUS_ENABLE;
984
985 // Is it suspended?
986 if (Value & EHCI_PRT_SUSPEND)
987 Status |= USB_PORT_STATUS_SUSPEND;
988
989 // a overcurrent is active?
990 if (Value & EHCI_PRT_OVERCURRENTACTIVE)
991 Status |= USB_PORT_STATUS_OVER_CURRENT;
992
993 // In a reset state?
994 if ((Value & EHCI_PRT_RESET) || m_ResetInProgress[PortId])
995 {
996 Status |= USB_PORT_STATUS_RESET;
997 Change |= USB_PORT_STATUS_RESET;
998 }
999
1000 //
1001 // FIXME: Is the Change here correct?
1002 //
1003 if (Value & EHCI_PRT_CONNECTSTATUSCHANGE)
1004 Change |= USB_PORT_STATUS_CONNECT;
1005
1006 if (Value & EHCI_PRT_ENABLEDSTATUSCHANGE)
1007 Change |= USB_PORT_STATUS_ENABLE;
1008
1009 *PortStatus = Status;
1010 *PortChange = Change;
1011
1012 return STATUS_SUCCESS;
1013 }
1014
1015 NTSTATUS
1016 CUSBHardwareDevice::ClearPortStatus(
1017 ULONG PortId,
1018 ULONG Status)
1019 {
1020 ULONG Value;
1021
1022 DPRINT("CUSBHardwareDevice::ClearPortStatus PortId %x Feature %x\n", PortId, Status);
1023
1024 if (PortId > m_Capabilities.HCSParams.PortCount)
1025 return STATUS_UNSUCCESSFUL;
1026
1027 if (Status == C_PORT_RESET)
1028 {
1029 //
1030 // update port status
1031 //
1032 m_ResetInProgress[PortId] = FALSE;
1033 }
1034
1035 if (Status == C_PORT_CONNECTION)
1036 {
1037 LARGE_INTEGER Timeout;
1038
1039 //
1040 // reset status change bits
1041 //
1042 Value = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortId));
1043 Value |= EHCI_PRT_CONNECTSTATUSCHANGE | EHCI_PRT_ENABLEDSTATUSCHANGE;
1044 EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC + (4 * PortId), Value);
1045
1046 //
1047 // delay is 100 ms
1048 //
1049 Timeout.QuadPart = 100;
1050 DPRINT1("Waiting %d milliseconds for port to stabilize after connection\n", Timeout.LowPart);
1051
1052 //
1053 // convert to 100 ns units (absolute)
1054 //
1055 Timeout.QuadPart *= -10000;
1056
1057 //
1058 // perform the wait
1059 //
1060 KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
1061 }
1062
1063 return STATUS_SUCCESS;
1064 }
1065
1066
1067 NTSTATUS
1068 CUSBHardwareDevice::SetPortFeature(
1069 ULONG PortId,
1070 ULONG Feature)
1071 {
1072 ULONG Value;
1073
1074 DPRINT("CUSBHardwareDevice::SetPortFeature\n");
1075
1076 if (PortId > m_Capabilities.HCSParams.PortCount)
1077 return STATUS_UNSUCCESSFUL;
1078
1079 Value = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortId));
1080
1081 if (Feature == PORT_ENABLE)
1082 {
1083 //
1084 // FIXME: EHCI Ports can only be disabled via reset
1085 //
1086 DPRINT1("PORT_ENABLE not supported for EHCI\n");
1087 }
1088
1089 if (Feature == PORT_RESET)
1090 {
1091 ResetPort(PortId);
1092
1093 //
1094 // update cached settings
1095 //
1096 m_ResetInProgress[PortId] = TRUE;
1097
1098 //
1099 // is there a status change callback
1100 //
1101 if (m_SCECallBack != NULL)
1102 {
1103 //
1104 // issue callback
1105 //
1106 m_SCECallBack(m_SCEContext);
1107 }
1108 }
1109
1110 if (Feature == PORT_POWER)
1111 {
1112 if (m_Capabilities.HCSParams.PortPowerControl)
1113 {
1114 ULONG Value;
1115 LARGE_INTEGER Timeout;
1116
1117 //
1118 // enable port power
1119 //
1120 Value = EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * PortId)) | EHCI_PRT_POWER;
1121 EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC, Value);
1122
1123 //
1124 // delay is 20 ms
1125 //
1126 Timeout.QuadPart = 20;
1127 DPRINT1("Waiting %d milliseconds for port power up\n", Timeout.LowPart);
1128
1129 //
1130 // convert to 100 ns units (absolute)
1131 //
1132 Timeout.QuadPart *= -10000;
1133
1134 //
1135 // perform the wait
1136 //
1137 KeDelayExecutionThread(KernelMode, FALSE, &Timeout);
1138 }
1139 }
1140 return STATUS_SUCCESS;
1141 }
1142
1143 VOID
1144 CUSBHardwareDevice::SetAsyncListRegister(
1145 ULONG PhysicalAddress)
1146 {
1147 EHCI_WRITE_REGISTER_ULONG(EHCI_ASYNCLISTBASE, PhysicalAddress);
1148 }
1149
1150 VOID
1151 CUSBHardwareDevice::SetPeriodicListRegister(
1152 ULONG PhysicalAddress)
1153 {
1154 //
1155 // store physical address
1156 //
1157 m_SyncFramePhysAddr = PhysicalAddress;
1158 }
1159
1160 struct _QUEUE_HEAD *
1161 CUSBHardwareDevice::GetAsyncListQueueHead()
1162 {
1163 return AsyncQueueHead;
1164 }
1165
1166 ULONG CUSBHardwareDevice::GetPeriodicListRegister()
1167 {
1168 UNIMPLEMENTED
1169 return NULL;
1170 }
1171
1172 VOID CUSBHardwareDevice::SetStatusChangeEndpointCallBack(
1173 PVOID CallBack,
1174 PVOID Context)
1175 {
1176 m_SCECallBack = (HD_INIT_CALLBACK*)CallBack;
1177 m_SCEContext = Context;
1178 }
1179
1180 KIRQL
1181 CUSBHardwareDevice::AcquireDeviceLock(void)
1182 {
1183 KIRQL OldLevel;
1184
1185 //
1186 // acquire lock
1187 //
1188 KeAcquireSpinLock(&m_Lock, &OldLevel);
1189
1190 //
1191 // return old irql
1192 //
1193 return OldLevel;
1194 }
1195
1196
1197 VOID
1198 CUSBHardwareDevice::ReleaseDeviceLock(
1199 KIRQL OldLevel)
1200 {
1201 KeReleaseSpinLock(&m_Lock, OldLevel);
1202 }
1203
1204 BOOLEAN
1205 NTAPI
1206 InterruptServiceRoutine(
1207 IN PKINTERRUPT Interrupt,
1208 IN PVOID ServiceContext)
1209 {
1210 CUSBHardwareDevice *This;
1211 ULONG CStatus;
1212
1213 This = (CUSBHardwareDevice*) ServiceContext;
1214 CStatus = This->EHCI_READ_REGISTER_ULONG(EHCI_USBSTS);
1215
1216 CStatus &= (EHCI_ERROR_INT | EHCI_STS_INT | EHCI_STS_IAA | EHCI_STS_PCD | EHCI_STS_FLR);
1217 //
1218 // Check that it belongs to EHCI
1219 //
1220 if (!CStatus)
1221 return FALSE;
1222
1223 //
1224 // Clear the Status
1225 //
1226 This->EHCI_WRITE_REGISTER_ULONG(EHCI_USBSTS, CStatus);
1227
1228 if (CStatus & EHCI_STS_FATAL)
1229 {
1230 This->StopController();
1231 DPRINT1("EHCI: Host System Error!\n");
1232 return TRUE;
1233 }
1234
1235 if (CStatus & EHCI_ERROR_INT)
1236 {
1237 DPRINT1("EHCI Status = 0x%x\n", CStatus);
1238 }
1239
1240 if (CStatus & EHCI_STS_HALT)
1241 {
1242 DPRINT1("Host Error Unexpected Halt\n");
1243 // FIXME: Reset controller\n");
1244 return TRUE;
1245 }
1246
1247 KeInsertQueueDpc(&This->m_IntDpcObject, This, (PVOID)CStatus);
1248 return TRUE;
1249 }
1250
1251 VOID NTAPI
1252 EhciDefferedRoutine(
1253 IN PKDPC Dpc,
1254 IN PVOID DeferredContext,
1255 IN PVOID SystemArgument1,
1256 IN PVOID SystemArgument2)
1257 {
1258 CUSBHardwareDevice *This;
1259 ULONG CStatus, PortStatus, PortCount, i, ShouldRingDoorBell;
1260 NTSTATUS Status = STATUS_SUCCESS;
1261 EHCI_USBCMD_CONTENT UsbCmd;
1262
1263 This = (CUSBHardwareDevice*) SystemArgument1;
1264 CStatus = (ULONG) SystemArgument2;
1265
1266 DPRINT("CStatus %x\n", CStatus);
1267
1268 //
1269 // check for completion of async schedule
1270 //
1271 if (CStatus & (EHCI_STS_RECL| EHCI_STS_INT | EHCI_ERROR_INT))
1272 {
1273 //
1274 // check if there is a door bell ring in progress
1275 //
1276 if (This->m_DoorBellRingInProgress == FALSE)
1277 {
1278 if (CStatus & EHCI_ERROR_INT)
1279 {
1280 //
1281 // controller reported error
1282 //
1283 DPRINT1("CStatus %x\n", CStatus);
1284 Status = STATUS_UNSUCCESSFUL;
1285 PC_ASSERT(FALSE);
1286 return;
1287 }
1288
1289 //
1290 // inform IUSBQueue of a completed queue head
1291 //
1292 This->m_UsbQueue->InterruptCallback(Status, &ShouldRingDoorBell);
1293
1294 //
1295 // was a queue head completed?
1296 //
1297 if (ShouldRingDoorBell)
1298 {
1299 //
1300 // set door ring bell in progress status flag
1301 //
1302 This->m_DoorBellRingInProgress = TRUE;
1303
1304 //
1305 // get command register
1306 //
1307 This->GetCommandRegister(&UsbCmd);
1308
1309 //
1310 // set door rang bell bit
1311 //
1312 UsbCmd.DoorBell = TRUE;
1313
1314 //
1315 // update command status
1316 //
1317 This->SetCommandRegister(&UsbCmd);
1318 }
1319 }
1320 }
1321
1322 //
1323 // check if the controller has acknowledged the door bell
1324 //
1325 if (CStatus & EHCI_STS_IAA)
1326 {
1327 //
1328 // controller has acknowledged, assert we rang the bell
1329 //
1330 PC_ASSERT(This->m_DoorBellRingInProgress == TRUE);
1331
1332 //
1333 // now notify IUSBQueue that it can free completed requests
1334 //
1335 This->m_UsbQueue->CompleteAsyncRequests();
1336
1337 //
1338 // door ring bell completed
1339 //
1340 This->m_DoorBellRingInProgress = FALSE;
1341 }
1342
1343 This->GetDeviceDetails(NULL, NULL, &PortCount, NULL);
1344 if (CStatus & EHCI_STS_PCD)
1345 {
1346 for (i = 0; i < PortCount; i++)
1347 {
1348 PortStatus = This->EHCI_READ_REGISTER_ULONG(EHCI_PORTSC + (4 * i));
1349
1350 //
1351 // Device connected or removed
1352 //
1353 if (PortStatus & EHCI_PRT_CONNECTSTATUSCHANGE)
1354 {
1355 if (PortStatus & EHCI_PRT_CONNECTED)
1356 {
1357 DPRINT1("Device connected on port %d\n", i);
1358
1359 //
1360 //FIXME: Determine device speed
1361 //
1362 if (This->m_Capabilities.HCSParams.CHCCount)
1363 {
1364 if (PortStatus & EHCI_PRT_ENABLED)
1365 {
1366 DPRINT1("Misbeaving controller. Port should be disabled at this point\n");
1367 }
1368
1369 if (PortStatus & EHCI_PRT_SLOWSPEEDLINE)
1370 {
1371 DPRINT1("Non HighSpeed device connected. Release ownership\n");
1372 This->EHCI_WRITE_REGISTER_ULONG(EHCI_PORTSC + (4 * i), EHCI_PRT_RELEASEOWNERSHIP);
1373 continue;
1374 }
1375 }
1376 }
1377 else
1378 {
1379 DPRINT1("Device disconnected on port %d\n", i);
1380 }
1381
1382 //
1383 // is there a status change callback
1384 //
1385 if (This->m_SCECallBack != NULL)
1386 {
1387 //
1388 // queue work item for processing
1389 //
1390 ExQueueWorkItem(&This->m_StatusChangeWorkItem, DelayedWorkQueue);
1391 }
1392
1393 //
1394 // FIXME: This needs to be saved somewhere
1395 //
1396 }
1397 }
1398 }
1399 return;
1400 }
1401
1402 VOID
1403 NTAPI
1404 StatusChangeWorkItemRoutine(
1405 PVOID Context)
1406 {
1407 //
1408 // cast to hardware object
1409 //
1410 CUSBHardwareDevice * This = (CUSBHardwareDevice*)Context;
1411
1412 //
1413 // is there a callback
1414 //
1415 if (This->m_SCECallBack)
1416 {
1417 //
1418 // issue callback
1419 //
1420 This->m_SCECallBack(This->m_SCEContext);
1421 }
1422
1423 }
1424
1425 NTSTATUS
1426 CreateUSBHardware(
1427 PUSBHARDWAREDEVICE *OutHardware)
1428 {
1429 PUSBHARDWAREDEVICE This;
1430
1431 This = new(NonPagedPool, TAG_USBEHCI) CUSBHardwareDevice(0);
1432
1433 if (!This)
1434 return STATUS_INSUFFICIENT_RESOURCES;
1435
1436 This->AddRef();
1437
1438 // return result
1439 *OutHardware = (PUSBHARDWAREDEVICE)This;
1440
1441 return STATUS_SUCCESS;
1442 }