drivers/usb/usbehci_new/hardware.h

   1 #pragma once
   2
   3 #include <ntddk.h>
   4
   5
   6 //
   7 // Host Controller Capability Registers
   8 //
   9 #define EHCI_CAPLENGTH                  0x00
  10 #define EHCI_HCIVERSION                 0x02
  11 #define EHCI_HCSPARAMS                  0x04
  12 #define EHCI_HCCPARAMS                  0x08
  13 #define EHCI_HCSP_PORTROUTE             0x0c
  14
  15
  16 //
  17 // Extended Capabilities
  18 //
  19 #define EHCI_ECP_SHIFT                  8
  20 #define EHCI_ECP_MASK                   0xff
  21 #define EHCI_LEGSUP_CAPID_MASK          0xff
  22 #define EHCI_LEGSUP_CAPID               0x01
  23 #define EHCI_LEGSUP_OSOWNED             (1 << 24)
  24 #define EHCI_LEGSUP_BIOSOWNED           (1 << 16)
  25
  26
  27 //
  28 // EHCI Operational Registers
  29 //
  30 #define EHCI_USBCMD                     0x00
  31 #define EHCI_USBSTS                     0x04
  32 #define EHCI_USBINTR                    0x08
  33 #define EHCI_FRINDEX                    0x0C
  34 #define EHCI_CTRLDSSEGMENT              0x10
  35 #define EHCI_PERIODICLISTBASE           0x14
  36 #define EHCI_ASYNCLISTBASE              0x18
  37 #define EHCI_CONFIGFLAG                 0x40
  38 #define EHCI_PORTSC                     0x44
  39
  40 //
  41 // Interrupt Register Flags
  42 //
  43 #define EHCI_USBINTR_INTE               0x01
  44 #define EHCI_USBINTR_ERR                0x02
  45 #define EHCI_USBINTR_PC                 0x04
  46 #define EHCI_USBINTR_FLROVR             0x08
  47 #define EHCI_USBINTR_HSERR              0x10
  48 #define EHCI_USBINTR_ASYNC              0x20
  49 // Bits 6:31 Reserved
  50
  51 //
  52 // Status Register Flags
  53 //
  54 #define EHCI_STS_INT                    0x01
  55 #define EHCI_STS_ERR                    0x02
  56 #define EHCI_STS_PCD                    0x04
  57 #define EHCI_STS_FLR                    0x08
  58 #define EHCI_STS_FATAL                  0x10
  59 #define EHCI_STS_IAA                    0x20
  60 // Bits 11:6 Reserved
  61 #define EHCI_STS_HALT                   0x1000
  62 #define EHCI_STS_RECL                   0x2000
  63 #define EHCI_STS_PSS                    0x4000
  64 #define EHCI_STS_ASS                    0x8000
  65 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
  66
  67 //
  68 // Port Register Flags
  69 //
  70 #define EHCI_PRT_CONNECTED              0x01
  71 #define EHCI_PRT_CONNECTSTATUSCHANGE    0x02
  72 #define EHCI_PRT_ENABLED                0x04
  73 #define EHCI_PRT_ENABLEDSTATUSCHANGE    0x08
  74 #define EHCI_PRT_OVERCURRENTACTIVE      0x10
  75 #define EHCI_PRT_OVERCURRENTCHANGE      0x20
  76 #define EHCI_PRT_FORCERESUME            0x40
  77 #define EHCI_PRT_SUSPEND                0x80
  78 #define EHCI_PRT_RESET                  0x100
  79 #define EHCI_PRT_SLOWSPEEDLINE          0x400
  80 #define EHCI_PRT_POWER                  0x1000
  81 #define EHCI_PRT_RELEASEOWNERSHIP       0x2000
  82
  83 #define EHCI_PORTSC_DATAMASK    0xffffffd1
  84 //
  85 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
  86 //
  87 #define TERMINATE_POINTER       0x01
  88
  89 //
  90 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
  91 //
  92
  93 //
  94 // Token Flags
  95 //
  96 #define PID_CODE_OUT_TOKEN      0x00
  97 #define PID_CODE_IN_TOKEN       0x01
  98 #define PID_CODE_SETUP_TOKEN    0x02
  99
 100 #define DO_START_SPLIT          0x00
 101 #define DO_COMPLETE_SPLIT       0x01
 102
 103 #define PING_STATE_DO_OUT       0x00
 104 #define PING_STATE_DO_PING      0x01
 105
 106 typedef struct _PERIODICFRAMELIST
 107 {
 108     PULONG VirtualAddr;
 109     PHYSICAL_ADDRESS PhysicalAddr;
 110     ULONG Size;
 111 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
 112
 113 //
 114 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
 115 //
 116 typedef struct _QETD_TOKEN_BITS
 117 {
 118     ULONG PingState:1;
 119     ULONG SplitTransactionState:1;
 120     ULONG MissedMicroFrame:1;
 121     ULONG TransactionError:1;
 122     ULONG BabbleDetected:1;
 123     ULONG DataBufferError:1;
 124     ULONG Halted:1;
 125     ULONG Active:1;
 126     ULONG PIDCode:2;
 127     ULONG ErrorCounter:2;
 128     ULONG CurrentPage:3;
 129     ULONG InterruptOnComplete:1;
 130     ULONG TotalBytesToTransfer:15;
 131     ULONG DataToggle:1;
 132 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
 133
 134 //
 135 // QUEUE ELEMENT TRANSFER DESCRIPTOR
 136 //
 137 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
 138 {
 139     //Hardware
 140     ULONG NextPointer;
 141     ULONG AlternateNextPointer;
 142     union
 143     {
 144         QETD_TOKEN_BITS Bits;
 145         ULONG DWord;
 146     } Token;
 147     ULONG BufferPointer[5];
 148
 149     //Software
 150     ULONG PhysicalAddr;
 151     LIST_ENTRY LinkedDescriptors;
 152     ULONG TotalBytesToTransfer;
 153 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 154
 155 //
 156 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
 157 //
 158 #define QH_ENDPOINT_FULLSPEED       0x00
 159 #define QH_ENDPOINT_LOWSPEED        0x01
 160 #define QH_ENDPOINT_HIGHSPEED       0x02
 161 typedef struct _END_POINT_CHARACTERISTICS
 162 {
 163     ULONG DeviceAddress:7;
 164     ULONG InactiveOnNextTransaction:1;
 165     ULONG EndPointNumber:4;
 166     ULONG EndPointSpeed:2;
 167     ULONG QEDTDataToggleControl:1;
 168     ULONG HeadOfReclamation:1;
 169     ULONG MaximumPacketLength:11;
 170     ULONG ControlEndPointFlag:1;
 171     ULONG NakCountReload:4;
 172 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 173
 174 //
 175 // Capabilities
 176 //
 177 typedef struct _END_POINT_CAPABILITIES
 178 {
 179     ULONG InterruptScheduleMask:8;
 180     ULONG SplitCompletionMask:8;
 181     ULONG HubAddr:6;
 182     ULONG PortNumber:6;
 183     ULONG NumberOfTransactionPerFrame:2;
 184 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 185
 186 //
 187 // QUEUE HEAD Flags and Struct
 188 //
 189 #define QH_TYPE_IDT             0x00
 190 #define QH_TYPE_QH              0x02
 191 #define QH_TYPE_SITD            0x04
 192 #define QH_TYPE_FSTN            0x06
 193
 194 typedef struct _QUEUE_HEAD
 195 {
 196     //Hardware
 197     ULONG HorizontalLinkPointer;
 198     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 199     END_POINT_CAPABILITIES EndPointCapabilities;
 200     // TERMINATE_POINTER not valid for this member
 201     ULONG CurrentLinkPointer;
 202     // TERMINATE_POINTER valid
 203     ULONG NextPointer;
 204     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
 205     ULONG AlternateNextPointer;
 206     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
 207     union
 208     {
 209         QETD_TOKEN_BITS Bits;
 210         ULONG DWord;
 211     } Token;
 212     ULONG BufferPointer[5];
 213
 214     //Software
 215     ULONG PhysicalAddr;
 216     LIST_ENTRY LinkedQueueHeads;
 217     PVOID Request;
 218 } QUEUE_HEAD, *PQUEUE_HEAD;
 219
 220 //
 221 // Command register content
 222 //
 223 typedef struct _EHCI_USBCMD_CONTENT
 224 {
 225     ULONG Run : 1;
 226     ULONG HCReset : 1;
 227     ULONG FrameListSize : 2;
 228     ULONG PeriodicEnable : 1;
 229     ULONG AsyncEnable : 1;
 230     ULONG DoorBell : 1;
 231     ULONG LightReset : 1;
 232     ULONG AsyncParkCount : 2;
 233     ULONG Reserved : 1;
 234     ULONG AsyncParkEnable : 1;
 235     ULONG Reserved1 : 4;
 236     ULONG IntThreshold : 8;
 237     ULONG Reserved2 : 8;
 238 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 239
 240 typedef struct _EHCI_HCS_CONTENT
 241 {
 242     ULONG PortCount : 4;
 243     ULONG PortPowerControl: 1;
 244     ULONG Reserved : 2;
 245     ULONG PortRouteRules : 1;
 246     ULONG PortPerCHC : 4;
 247     ULONG CHCCount : 4;
 248     ULONG PortIndicator : 1;
 249     ULONG Reserved2 : 3;
 250     ULONG DbgPortNum : 4;
 251     ULONG Reserved3 : 8;
 252
 253 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 254
 255 typedef struct _EHCI_HCC_CONTENT
 256 {
 257     ULONG CurAddrBits : 1;
 258     ULONG VarFrameList : 1;
 259     ULONG ParkMode : 1;
 260     ULONG Reserved : 1;
 261     ULONG IsoSchedThreshold : 4;
 262     ULONG EECPCapable : 8;
 263     ULONG Reserved2 : 16;
 264
 265 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 266
 267 typedef struct _EHCI_CAPS {
 268     UCHAR Length;
 269     UCHAR Reserved;
 270     USHORT HCIVersion;
 271     union
 272     {
 273         EHCI_HCS_CONTENT HCSParams;
 274         ULONG HCSParamsLong;
 275     };
 276     union
 277     {
 278         EHCI_HCC_CONTENT HCCParams;
 279         ULONG HCCParamsLong;
 280     };
 281     UCHAR PortRoute [15];
 282 } EHCI_CAPS, *PEHCI_CAPS;
 283
 284
 285 typedef struct
 286 {
 287     PKSPIN_LOCK Lock;
 288     RTL_BITMAP Bitmap;
 289     PULONG BitmapBuffer;
 290     ULONG BlockSize;
 291     PVOID VirtualBase;
 292     PHYSICAL_ADDRESS PhysicalBase;
 293     ULONG Length;
 294 }DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
 295
 296 typedef struct _EHCI_HOST_CONTROLLER
 297 {
 298     ULONG OpRegisters;
 299     EHCI_CAPS ECHICaps;
 300     PVOID CommonBufferVA;
 301     PHYSICAL_ADDRESS CommonBufferPA;
 302     ULONG CommonBufferSize;
 303     PQUEUE_HEAD AsyncListQueue;
 304     KSPIN_LOCK Lock;
 305     LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
 306 } EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
 307
 308 typedef struct
 309 {
 310     ULONG PortStatus;
 311     ULONG PortChange;
 312 }EHCI_PORT_STATUS;
 313