drivers/usb/usbehci_new/hardware.h

   1 #pragma once
   2
   3 #include <ntddk.h>
   4
   5
   6 //
   7 // Host Controller Capability Registers
   8 //
   9 #define EHCI_CAPLENGTH                  0x00
  10 #define EHCI_HCIVERSION                 0x02
  11 #define EHCI_HCSPARAMS                  0x04
  12 #define EHCI_HCCPARAMS                  0x08
  13 #define EHCI_HCSP_PORTROUTE             0x0c
  14
  15 //
  16 // EHCI Operational Registers
  17 //
  18 #define EHCI_USBCMD                     0x00
  19 #define EHCI_USBSTS                     0x04
  20 #define EHCI_USBINTR                    0x08
  21 #define EHCI_FRINDEX                    0x0C
  22 #define EHCI_CTRLDSSEGMENT              0x10
  23 #define EHCI_PERIODICLISTBASE           0x14
  24 #define EHCI_ASYNCLISTBASE              0x18
  25 #define EHCI_CONFIGFLAG                 0x40
  26 #define EHCI_PORTSC                     0x44
  27
  28 //
  29 // Interrupt Register Flags
  30 //
  31 #define EHCI_USBINTR_INTE               0x01
  32 #define EHCI_USBINTR_ERR                0x02
  33 #define EHCI_USBINTR_PC                 0x04
  34 #define EHCI_USBINTR_FLROVR             0x08
  35 #define EHCI_USBINTR_HSERR              0x10
  36 #define EHCI_USBINTR_ASYNC              0x20
  37 // Bits 6:31 Reserved
  38
  39 //
  40 // Status Register Flags
  41 //
  42 #define EHCI_STS_INT                    0x01
  43 #define EHCI_STS_ERR                    0x02
  44 #define EHCI_STS_PCD                    0x04
  45 #define EHCI_STS_FLR                    0x08
  46 #define EHCI_STS_FATAL                  0x10
  47 #define EHCI_STS_IAA                    0x20
  48 // Bits 11:6 Reserved
  49 #define EHCI_STS_HALT                   0x1000
  50 #define EHCI_STS_RECL                   0x2000
  51 #define EHCI_STS_PSS                    0x4000
  52 #define EHCI_STS_ASS                    0x8000
  53 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
  54
  55 //
  56 // Port Register Flags
  57 //
  58 #define EHCI_PRT_CONNECTED              0x01
  59 #define EHCI_PRT_CONNECTSTATUSCHANGE    0x02
  60 #define EHCI_PRT_ENABLED                0x04
  61 #define EHCI_PRT_ENABLEDSTATUSCHANGE    0x08
  62 #define EHCI_PRT_OVERCURRENTACTIVE      0x10
  63 #define EHCI_PRT_OVERCURRENTCHANGE      0x20
  64 #define EHCI_PRT_FORCERESUME            0x40
  65 #define EHCI_PRT_SUSPEND                0x80
  66 #define EHCI_PRT_RESET                  0x100
  67 #define EHCI_PRT_SLOWSPEEDLINE          0x400
  68 #define EHCI_PRT_POWER                  0x1000
  69 #define EHCI_PRT_RELEASEOWNERSHIP       0x2000
  70
  71 #define EHCI_PORTSC_DATAMASK    0xffffffd1
  72 //
  73 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
  74 //
  75 #define TERMINATE_POINTER       0x01
  76
  77 //
  78 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
  79 //
  80
  81 //
  82 // Token Flags
  83 //
  84 #define PID_CODE_OUT_TOKEN      0x00
  85 #define PID_CODE_IN_TOKEN       0x01
  86 #define PID_CODE_SETUP_TOKEN    0x02
  87
  88 #define DO_START_SPLIT          0x00
  89 #define DO_COMPLETE_SPLIT       0x01
  90
  91 #define PING_STATE_DO_OUT       0x00
  92 #define PING_STATE_DO_PING      0x01
  93
  94 typedef struct _PERIODICFRAMELIST
  95 {
  96     PULONG VirtualAddr;
  97     PHYSICAL_ADDRESS PhysicalAddr;
  98     ULONG Size;
  99 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
 100
 101 //
 102 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
 103 //
 104 typedef struct _QETD_TOKEN_BITS
 105 {
 106     ULONG PingState:1;
 107     ULONG SplitTransactionState:1;
 108     ULONG MissedMicroFrame:1;
 109     ULONG TransactionError:1;
 110     ULONG BabbleDetected:1;
 111     ULONG DataBufferError:1;
 112     ULONG Halted:1;
 113     ULONG Active:1;
 114     ULONG PIDCode:2;
 115     ULONG ErrorCounter:2;
 116     ULONG CurrentPage:3;
 117     ULONG InterruptOnComplete:1;
 118     ULONG TotalBytesToTransfer:15;
 119     ULONG DataToggle:1;
 120 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
 121
 122 //
 123 // QUEUE ELEMENT TRANSFER DESCRIPTOR
 124 //
 125 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
 126 {
 127     //Hardware
 128     ULONG NextPointer;
 129     ULONG AlternateNextPointer;
 130     union
 131     {
 132         QETD_TOKEN_BITS Bits;
 133         ULONG DWord;
 134     } Token;
 135     ULONG BufferPointer[5];
 136
 137     //Software
 138     ULONG PhysicalAddr;
 139     LIST_ENTRY LinkedDescriptors;
 140     ULONG TotalBytesToTransfer;
 141 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 142
 143 //
 144 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
 145 //
 146 #define QH_ENDPOINT_FULLSPEED       0x00
 147 #define QH_ENDPOINT_LOWSPEED        0x01
 148 #define QH_ENDPOINT_HIGHSPEED       0x02
 149 typedef struct _END_POINT_CHARACTERISTICS
 150 {
 151     ULONG DeviceAddress:7;
 152     ULONG InactiveOnNextTransaction:1;
 153     ULONG EndPointNumber:4;
 154     ULONG EndPointSpeed:2;
 155     ULONG QEDTDataToggleControl:1;
 156     ULONG HeadOfReclamation:1;
 157     ULONG MaximumPacketLength:11;
 158     ULONG ControlEndPointFlag:1;
 159     ULONG NakCountReload:4;
 160 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 161
 162 //
 163 // Capabilities
 164 //
 165 typedef struct _END_POINT_CAPABILITIES
 166 {
 167     ULONG InterruptScheduleMask:8;
 168     ULONG SplitCompletionMask:8;
 169     ULONG HubAddr:6;
 170     ULONG PortNumber:6;
 171     ULONG NumberOfTransactionPerFrame:2;
 172 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 173
 174 //
 175 // QUEUE HEAD Flags and Struct
 176 //
 177 #define QH_TYPE_IDT             0x00
 178 #define QH_TYPE_QH              0x02
 179 #define QH_TYPE_SITD            0x04
 180 #define QH_TYPE_FSTN            0x06
 181
 182 typedef struct _QUEUE_HEAD
 183 {
 184     //Hardware
 185     ULONG HorizontalLinkPointer;
 186     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 187     END_POINT_CAPABILITIES EndPointCapabilities;
 188     // TERMINATE_POINTER not valid for this member
 189     ULONG CurrentLinkPointer;
 190     // TERMINATE_POINTER valid
 191     ULONG NextPointer;
 192     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
 193     ULONG AlternateNextPointer;
 194     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
 195     union
 196     {
 197         QETD_TOKEN_BITS Bits;
 198         ULONG DWord;
 199     } Token;
 200     ULONG BufferPointer[5];
 201
 202     //Software
 203     ULONG PhysicalAddr;
 204     LIST_ENTRY LinkedQueueHeads;
 205     PVOID Request;
 206 } QUEUE_HEAD, *PQUEUE_HEAD;
 207
 208 //
 209 // Command register content
 210 //
 211 typedef struct _EHCI_USBCMD_CONTENT
 212 {
 213     ULONG Run : 1;
 214     ULONG HCReset : 1;
 215     ULONG FrameListSize : 2;
 216     ULONG PeriodicEnable : 1;
 217     ULONG AsyncEnable : 1;
 218     ULONG DoorBell : 1;
 219     ULONG LightReset : 1;
 220     ULONG AsyncParkCount : 2;
 221     ULONG Reserved : 1;
 222     ULONG AsyncParkEnable : 1;
 223     ULONG Reserved1 : 4;
 224     ULONG IntThreshold : 8;
 225     ULONG Reserved2 : 8;
 226 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 227
 228 typedef struct _EHCI_HCS_CONTENT
 229 {
 230     ULONG PortCount : 4;
 231     ULONG PortPowerControl: 1;
 232     ULONG Reserved : 2;
 233     ULONG PortRouteRules : 1;
 234     ULONG PortPerCHC : 4;
 235     ULONG CHCCount : 4;
 236     ULONG PortIndicator : 1;
 237     ULONG Reserved2 : 3;
 238     ULONG DbgPortNum : 4;
 239     ULONG Reserved3 : 8;
 240
 241 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 242
 243 typedef struct _EHCI_HCC_CONTENT
 244 {
 245     ULONG CurAddrBits : 1;
 246     ULONG VarFrameList : 1;
 247     ULONG ParkMode : 1;
 248     ULONG Reserved : 1;
 249     ULONG IsoSchedThreshold : 4;
 250     ULONG EECPCapable : 8;
 251     ULONG Reserved2 : 16;
 252
 253 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 254
 255 typedef struct _EHCI_CAPS {
 256     UCHAR Length;
 257     UCHAR Reserved;
 258     USHORT HCIVersion;
 259     union
 260     {
 261         EHCI_HCS_CONTENT HCSParams;
 262         ULONG HCSParamsLong;
 263     };
 264     union
 265     {
 266         EHCI_HCC_CONTENT HCCParams;
 267         ULONG HCCParamsLong;
 268     };
 269     UCHAR PortRoute [15];
 270 } EHCI_CAPS, *PEHCI_CAPS;
 271
 272
 273 typedef struct
 274 {
 275     PKSPIN_LOCK Lock;
 276     RTL_BITMAP Bitmap;
 277     PULONG BitmapBuffer;
 278     ULONG BlockSize;
 279     PVOID VirtualBase;
 280     PHYSICAL_ADDRESS PhysicalBase;
 281     ULONG Length;
 282 }DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
 283
 284 typedef struct _EHCI_HOST_CONTROLLER
 285 {
 286     ULONG OpRegisters;
 287     EHCI_CAPS ECHICaps;
 288     PVOID CommonBufferVA;
 289     PHYSICAL_ADDRESS CommonBufferPA;
 290     ULONG CommonBufferSize;
 291     PQUEUE_HEAD AsyncListQueue;
 292     KSPIN_LOCK Lock;
 293     LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
 294 } EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
 295
 296 typedef struct
 297 {
 298     ULONG PortStatus;
 299     ULONG PortChange;
 300 }EHCI_PORT_STATUS;
 301