drivers/usb/usbehci_new/hardware.h

   1 #pragma once
   2
   3 #include <ntddk.h>
   4
   5 //
   6 // EHCI Operational Registers
   7 //
   8 #define EHCI_USBCMD                     0x00
   9 #define EHCI_USBSTS                     0x04
  10 #define EHCI_USBINTR                    0x08
  11 #define EHCI_FRINDEX                    0x0C
  12 #define EHCI_CTRLDSSEGMENT              0x10
  13 #define EHCI_PERIODICLISTBASE           0x14
  14 #define EHCI_ASYNCLISTBASE              0x18
  15 #define EHCI_CONFIGFLAG                 0x40
  16 #define EHCI_PORTSC                     0x44
  17
  18 //
  19 // Interrupt Register Flags
  20 //
  21 #define EHCI_USBINTR_INTE               0x01
  22 #define EHCI_USBINTR_ERR                0x02
  23 #define EHCI_USBINTR_PC                 0x04
  24 #define EHCI_USBINTR_FLROVR             0x08
  25 #define EHCI_USBINTR_HSERR              0x10
  26 #define EHCI_USBINTR_ASYNC              0x20
  27 // Bits 6:31 Reserved
  28
  29 //
  30 // Status Register Flags
  31 //
  32 #define EHCI_STS_INT                    0x01
  33 #define EHCI_STS_ERR                    0x02
  34 #define EHCI_STS_PCD                    0x04
  35 #define EHCI_STS_FLR                    0x08
  36 #define EHCI_STS_FATAL                  0x10
  37 #define EHCI_STS_IAA                    0x20
  38 // Bits 11:6 Reserved
  39 #define EHCI_STS_HALT                   0x1000
  40 #define EHCI_STS_RECL                   0x2000
  41 #define EHCI_STS_PSS                    0x4000
  42 #define EHCI_STS_ASS                    0x8000
  43 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
  44
  45 //
  46 // Port Register Flags
  47 //
  48 #define EHCI_PRT_CONNECTED              0x01
  49 #define EHCI_PRT_CONNECTSTATUSCHANGE    0x02
  50 #define EHCI_PRT_ENABLED                0x04
  51 #define EHCI_PRT_ENABLEDSTATUSCHANGE    0x08
  52 #define EHCI_PRT_OVERCURRENTACTIVE      0x10
  53 #define EHCI_PRT_OVERCURRENTCHANGE      0x20
  54 #define EHCI_PRT_FORCERESUME            0x40
  55 #define EHCI_PRT_SUSPEND                0x80
  56 #define EHCI_PRT_RESET                  0x100
  57 #define EHCI_PRT_SLOWSPEEDLINE          0x400
  58 #define EHCI_PRT_POWER                  0x1000
  59 #define EHCI_PRT_RELEASEOWNERSHIP       0x2000
  60
  61 #define EHCI_PORTSC_DATAMASK    0xffffffd1
  62 //
  63 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
  64 //
  65 #define TERMINATE_POINTER       0x01
  66
  67 //
  68 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
  69 //
  70
  71 //
  72 // Token Flags
  73 //
  74 #define PID_CODE_OUT_TOKEN      0x00
  75 #define PID_CODE_IN_TOKEN       0x01
  76 #define PID_CODE_SETUP_TOKEN    0x02
  77
  78 #define DO_START_SPLIT          0x00
  79 #define DO_COMPLETE_SPLIT       0x01
  80
  81 #define PING_STATE_DO_OUT       0x00
  82 #define PING_STATE_DO_PING      0x01
  83
  84 typedef struct _PERIODICFRAMELIST
  85 {
  86     PULONG VirtualAddr;
  87     PHYSICAL_ADDRESS PhysicalAddr;
  88     ULONG Size;
  89 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
  90
  91 //
  92 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
  93 //
  94 typedef struct _QETD_TOKEN_BITS
  95 {
  96     ULONG PingState:1;
  97     ULONG SplitTransactionState:1;
  98     ULONG MissedMicroFrame:1;
  99     ULONG TransactionError:1;
 100     ULONG BabbleDetected:1;
 101     ULONG DataBufferError:1;
 102     ULONG Halted:1;
 103     ULONG Active:1;
 104     ULONG PIDCode:2;
 105     ULONG ErrorCounter:2;
 106     ULONG CurrentPage:3;
 107     ULONG InterruptOnComplete:1;
 108     ULONG TotalBytesToTransfer:15;
 109     ULONG DataToggle:1;
 110 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
 111
 112 //
 113 // QUEUE ELEMENT TRANSFER DESCRIPTOR
 114 //
 115 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
 116 {
 117     //Hardware
 118     ULONG NextPointer;
 119     ULONG AlternateNextPointer;
 120     union
 121     {
 122         QETD_TOKEN_BITS Bits;
 123         ULONG DWord;
 124     } Token;
 125     ULONG BufferPointer[5];
 126
 127     //Software
 128     ULONG PhysicalAddr;
 129     LIST_ENTRY LinkedDescriptors;
 130     ULONG TotalBytesToTransfer;
 131 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 132
 133 //
 134 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
 135 //
 136 #define QH_ENDPOINT_FULLSPEED       0x00
 137 #define QH_ENDPOINT_LOWSPEED        0x01
 138 #define QH_ENDPOINT_HIGHSPEED       0x02
 139 typedef struct _END_POINT_CHARACTERISTICS
 140 {
 141     ULONG DeviceAddress:7;
 142     ULONG InactiveOnNextTransaction:1;
 143     ULONG EndPointNumber:4;
 144     ULONG EndPointSpeed:2;
 145     ULONG QEDTDataToggleControl:1;
 146     ULONG HeadOfReclamation:1;
 147     ULONG MaximumPacketLength:11;
 148     ULONG ControlEndPointFlag:1;
 149     ULONG NakCountReload:4;
 150 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 151
 152 //
 153 // Capabilities
 154 //
 155 typedef struct _END_POINT_CAPABILITIES
 156 {
 157     ULONG InterruptScheduleMask:8;
 158     ULONG SplitCompletionMask:8;
 159     ULONG HubAddr:6;
 160     ULONG PortNumber:6;
 161     ULONG NumberOfTransactionPerFrame:2;
 162 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 163
 164 //
 165 // QUEUE HEAD Flags and Struct
 166 //
 167 #define QH_TYPE_IDT             0x00
 168 #define QH_TYPE_QH              0x02
 169 #define QH_TYPE_SITD            0x04
 170 #define QH_TYPE_FSTN            0x06
 171
 172 typedef struct _QUEUE_HEAD
 173 {
 174     //Hardware
 175     ULONG HorizontalLinkPointer;
 176     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 177     END_POINT_CAPABILITIES EndPointCapabilities;
 178     // TERMINATE_POINTER not valid for this member
 179     ULONG CurrentLinkPointer;
 180     // TERMINATE_POINTER valid
 181     ULONG NextPointer;
 182     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
 183     ULONG AlternateNextPointer;
 184     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
 185     union
 186     {
 187         QETD_TOKEN_BITS Bits;
 188         ULONG DWord;
 189     } Token;
 190     ULONG BufferPointer[5];
 191
 192     //Software
 193     ULONG PhysicalAddr;
 194     LIST_ENTRY LinkedQueueHeads;
 195     PVOID Request;
 196 } QUEUE_HEAD, *PQUEUE_HEAD;
 197
 198 //
 199 // Command register content
 200 //
 201 typedef struct _EHCI_USBCMD_CONTENT
 202 {
 203     ULONG Run : 1;
 204     ULONG HCReset : 1;
 205     ULONG FrameListSize : 2;
 206     ULONG PeriodicEnable : 1;
 207     ULONG AsyncEnable : 1;
 208     ULONG DoorBell : 1;
 209     ULONG LightReset : 1;
 210     ULONG AsyncParkCount : 2;
 211     ULONG Reserved : 1;
 212     ULONG AsyncParkEnable : 1;
 213     ULONG Reserved1 : 4;
 214     ULONG IntThreshold : 8;
 215     ULONG Reserved2 : 8;
 216 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 217
 218 typedef struct _EHCI_HCS_CONTENT
 219 {
 220     ULONG PortCount : 4;
 221     ULONG PortPowerControl: 1;
 222     ULONG Reserved : 2;
 223     ULONG PortRouteRules : 1;
 224     ULONG PortPerCHC : 4;
 225     ULONG CHCCount : 4;
 226     ULONG PortIndicator : 1;
 227     ULONG Reserved2 : 3;
 228     ULONG DbgPortNum : 4;
 229     ULONG Reserved3 : 8;
 230
 231 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 232
 233 typedef struct _EHCI_HCC_CONTENT
 234 {
 235     ULONG CurAddrBits : 1;
 236     ULONG VarFrameList : 1;
 237     ULONG ParkMode : 1;
 238     ULONG Reserved : 1;
 239     ULONG IsoSchedThreshold : 4;
 240     ULONG EECPCapable : 8;
 241     ULONG Reserved2 : 16;
 242
 243 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 244
 245 typedef struct _EHCI_CAPS {
 246     UCHAR Length;
 247     UCHAR Reserved;
 248     USHORT HCIVersion;
 249     union
 250     {
 251         EHCI_HCS_CONTENT HCSParams;
 252         ULONG HCSParamsLong;
 253     };
 254     union
 255     {
 256         EHCI_HCC_CONTENT HCCParams;
 257         ULONG HCCParamsLong;
 258     };
 259     UCHAR PortRoute [15];
 260 } EHCI_CAPS, *PEHCI_CAPS;
 261
 262
 263 typedef struct
 264 {
 265     PKSPIN_LOCK Lock;
 266     RTL_BITMAP Bitmap;
 267     PULONG BitmapBuffer;
 268     ULONG BlockSize;
 269     PVOID VirtualBase;
 270     PHYSICAL_ADDRESS PhysicalBase;
 271     ULONG Length;
 272 }DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
 273
 274 typedef struct _EHCI_HOST_CONTROLLER
 275 {
 276     ULONG OpRegisters;
 277     EHCI_CAPS ECHICaps;
 278     PVOID CommonBufferVA;
 279     PHYSICAL_ADDRESS CommonBufferPA;
 280     ULONG CommonBufferSize;
 281     PQUEUE_HEAD AsyncListQueue;
 282     KSPIN_LOCK Lock;
 283     LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
 284 } EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;
 285
 286 typedef struct
 287 {
 288     ULONG PortStatus;
 289     ULONG PortChange;
 290 }EHCI_PORT_STATUS;
 291