drivers/usb/usbehci_new/hardware.h

   1 #pragma once
   2
   3 #include <ntddk.h>
   4
   5 //
   6 // EHCI Operational Registers
   7 //
   8 #define EHCI_USBCMD                     0x00
   9 #define EHCI_USBSTS                     0x04
  10 #define EHCI_USBINTR                    0x08
  11 #define EHCI_FRINDEX                    0x0C
  12 #define EHCI_CTRLDSSEGMENT              0x10
  13 #define EHCI_PERIODICLISTBASE           0x14
  14 #define EHCI_ASYNCLISTBASE              0x18
  15 #define EHCI_CONFIGFLAG                 0x40
  16 #define EHCI_PORTSC                     0x44
  17
  18 //
  19 // Interrupt Register Flags
  20 //
  21 #define EHCI_USBINTR_INTE               0x01
  22 #define EHCI_USBINTR_ERR                0x02
  23 #define EHCI_USBINTR_PC                 0x04
  24 #define EHCI_USBINTR_FLROVR             0x08
  25 #define EHCI_USBINTR_HSERR              0x10
  26 #define EHCI_USBINTR_ASYNC              0x20
  27 // Bits 6:31 Reserved
  28
  29 //
  30 // Status Register Flags
  31 //
  32 #define EHCI_STS_INT                    0x01
  33 #define EHCI_STS_ERR                    0x02
  34 #define EHCI_STS_PCD                    0x04
  35 #define EHCI_STS_FLR                    0x08
  36 #define EHCI_STS_FATAL                  0x10
  37 #define EHCI_STS_IAA                    0x20
  38 // Bits 11:6 Reserved
  39 #define EHCI_STS_HALT                   0x1000
  40 #define EHCI_STS_RECL                   0x2000
  41 #define EHCI_STS_PSS                    0x4000
  42 #define EHCI_STS_ASS                    0x8000
  43 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
  44
  45 //
  46 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
  47 //
  48 #define TERMINATE_POINTER       0x01
  49
  50 //
  51 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
  52 //
  53
  54 //
  55 // Token Flags
  56 //
  57 #define PID_CODE_OUT_TOKEN      0x00
  58 #define PID_CODE_IN_TOKEN       0x01
  59 #define PID_CODE_SETUP_TOKEN    0x02
  60
  61 #define DO_START_SPLIT          0x00
  62 #define DO_COMPLETE_SPLIT       0x01
  63
  64 #define PING_STATE_DO_OUT       0x00
  65 #define PING_STATE_DO_PING      0x01
  66
  67 typedef struct _PERIODICFRAMELIST
  68 {
  69     PULONG VirtualAddr;
  70     PHYSICAL_ADDRESS PhysicalAddr;
  71     ULONG Size;
  72 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
  73
  74 //
  75 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
  76 //
  77 typedef struct _QETD_TOKEN_BITS
  78 {
  79     ULONG PingState:1;
  80     ULONG SplitTransactionState:1;
  81     ULONG MissedMicroFrame:1;
  82     ULONG TransactionError:1;
  83     ULONG BabbleDetected:1;
  84     ULONG DataBufferError:1;
  85     ULONG Halted:1;
  86     ULONG Active:1;
  87     ULONG PIDCode:2;
  88     ULONG ErrorCounter:2;
  89     ULONG CurrentPage:3;
  90     ULONG InterruptOnComplete:1;
  91     ULONG TotalBytesToTransfer:15;
  92     ULONG DataToggle:1;
  93 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
  94
  95 //
  96 // QUEUE ELEMENT TRANSFER DESCRIPTOR
  97 //
  98 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
  99 {
 100     //Hardware
 101     ULONG NextPointer;
 102     ULONG AlternateNextPointer;
 103     union
 104     {
 105         QETD_TOKEN_BITS Bits;
 106         ULONG DWord;
 107     } Token;
 108     ULONG BufferPointer[5];
 109
 110     //Software
 111     ULONG PhysicalAddr;
 112     struct _QUEUE_TRANSFER_DESCRIPTOR *PreviousDescriptor;
 113     struct _QUEUE_TRANSFER_DESCRIPTOR *NextDescriptor;
 114 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 115
 116 //
 117 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
 118 //
 119 #define QH_ENDPOINT_FULLSPEED       0x00
 120 #define QH_ENDPOINT_LOWSPEED        0x01
 121 #define QH_ENDPOINT_HIGHSPEED       0x02
 122 typedef struct _END_POINT_CHARACTERISTICS
 123 {
 124     ULONG DeviceAddress:7;
 125     ULONG InactiveOnNextTransaction:1;
 126     ULONG EndPointNumber:4;
 127     ULONG EndPointSpeed:2;
 128     ULONG QEDTDataToggleControl:1;
 129     ULONG HeadOfReclamation:1;
 130     ULONG MaximumPacketLength:11;
 131     ULONG ControlEndPointFlag:1;
 132     ULONG NakCountReload:4;
 133 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 134
 135 //
 136 // Capabilities
 137 //
 138 typedef struct _END_POINT_CAPABILITIES
 139 {
 140     ULONG InterruptScheduleMask:8;
 141     ULONG SplitCompletionMask:8;
 142     ULONG HubAddr:6;
 143     ULONG PortNumber:6;
 144     ULONG NumberOfTransactionPerFrame:2;
 145 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 146
 147 //
 148 // QUEUE HEAD Flags and Struct
 149 //
 150 #define QH_TYPE_IDT             0x00
 151 #define QH_TYPE_QH              0x02
 152 #define QH_TYPE_SITD            0x04
 153 #define QH_TYPE_FSTN            0x06
 154
 155 typedef struct _QUEUE_HEAD
 156 {
 157     //Hardware
 158     ULONG HorizontalLinkPointer;
 159     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 160     END_POINT_CAPABILITIES EndPointCapabilities;
 161     // TERMINATE_POINTER not valid for this member
 162     ULONG CurrentLinkPointer;
 163     // TERMINATE_POINTER valid
 164     ULONG NextPointer;
 165     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
 166     ULONG AlternateNextPointer;
 167     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
 168     union
 169     {
 170         QETD_TOKEN_BITS Bits;
 171         ULONG DWord;
 172     } Token;
 173     ULONG BufferPointer[5];
 174
 175     //Software
 176     ULONG PhysicalAddr;
 177     struct _QUEUE_HEAD *PreviousQueueHead;
 178     struct _QUEUE_HEAD *NextQueueHead;
 179     PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
 180     PIRP IrpToComplete;
 181     PMDL MdlToFree;
 182     PKEVENT Event;
 183 } QUEUE_HEAD, *PQUEUE_HEAD;
 184
 185 //
 186 // Command register content
 187 //
 188 typedef struct _EHCI_USBCMD_CONTENT
 189 {
 190     ULONG Run : 1;
 191     ULONG HCReset : 1;
 192     ULONG FrameListSize : 2;
 193     ULONG PeriodicEnable : 1;
 194     ULONG AsyncEnable : 1;
 195     ULONG DoorBell : 1;
 196     ULONG LightReset : 1;
 197     ULONG AsyncParkCount : 2;
 198     ULONG Reserved : 1;
 199     ULONG AsyncParkEnable : 1;
 200     ULONG Reserved1 : 4;
 201     ULONG IntThreshold : 8;
 202     ULONG Reserved2 : 8;
 203 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 204
 205 //
 206 // Status register content
 207 //
 208 typedef struct _EHCI_USBSTS_CONTENT
 209 {
 210     ULONG USBInterrupt:1;
 211     ULONG ErrorInterrupt:1;
 212     ULONG DetectChangeInterrupt:1;
 213     ULONG FrameListRolloverInterrupt:1;
 214     ULONG HostSystemErrorInterrupt:1;
 215     ULONG AsyncAdvanceInterrupt:1;
 216     ULONG Reserved:6;
 217     ULONG HCHalted:1;
 218     ULONG Reclamation:1;
 219     ULONG PeriodicScheduleStatus:1;
 220     ULONG AsynchronousScheduleStatus:1;
 221 } EHCI_USBSTS_CONTENT, *PEHCI_USBSTS_CONTENT;
 222
 223 typedef struct _EHCI_USBPORTSC_CONTENT
 224 {
 225     ULONG CurrentConnectStatus:1;
 226     ULONG ConnectStatusChange:1;
 227     ULONG PortEnabled:1;
 228     ULONG PortEnableChanged:1;
 229     ULONG OverCurrentActive:1;
 230     ULONG OverCurrentChange:1;
 231     ULONG ForcePortResume:1;
 232     ULONG Suspend:1;
 233     ULONG PortReset:1;
 234     ULONG Reserved:1;
 235     ULONG LineStatus:2;
 236     ULONG PortPower:1;
 237     ULONG PortOwner:1;
 238 } EHCI_USBPORTSC_CONTENT, *PEHCI_USBPORTSC_CONTENT;
 239
 240 typedef struct _EHCI_HCS_CONTENT
 241 {
 242     ULONG PortCount : 4;
 243     ULONG PortPowerControl: 1;
 244     ULONG Reserved : 2;
 245     ULONG PortRouteRules : 1;
 246     ULONG PortPerCHC : 4;
 247     ULONG CHCCount : 4;
 248     ULONG PortIndicator : 1;
 249     ULONG Reserved2 : 3;
 250     ULONG DbgPortNum : 4;
 251     ULONG Reserved3 : 8;
 252
 253 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 254
 255 typedef struct _EHCI_HCC_CONTENT
 256 {
 257     ULONG CurAddrBits : 1;
 258     ULONG VarFrameList : 1;
 259     ULONG ParkMode : 1;
 260     ULONG Reserved : 1;
 261     ULONG IsoSchedThreshold : 4;
 262     ULONG EECPCapable : 8;
 263     ULONG Reserved2 : 16;
 264
 265 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 266
 267 typedef struct _EHCI_CAPS {
 268     UCHAR Length;
 269     UCHAR Reserved;
 270     USHORT HCIVersion;
 271     union
 272     {
 273         EHCI_HCS_CONTENT HCSParams;
 274         ULONG HCSParamsLong;
 275     };
 276     union
 277     {
 278         EHCI_HCC_CONTENT HCCParams;
 279         ULONG HCCParamsLong;
 280     };
 281     UCHAR PortRoute [8];
 282 } EHCI_CAPS, *PEHCI_CAPS;
 283
 284
 285 typedef struct
 286 {
 287     PKSPIN_LOCK Lock;
 288     RTL_BITMAP Bitmap;
 289     PULONG BitmapBuffer;
 290     ULONG BlockSize;
 291     PVOID VirtualBase;
 292     PHYSICAL_ADDRESS PhysicalBase;
 293     ULONG Length;
 294 }DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
 295
 296 typedef struct _EHCI_HOST_CONTROLLER
 297 {
 298     ULONG OpRegisters;
 299     EHCI_CAPS ECHICaps;
 300     PVOID CommonBufferVA;
 301     PHYSICAL_ADDRESS CommonBufferPA;
 302     ULONG CommonBufferSize;
 303     PQUEUE_HEAD AsyncListQueue;
 304     KSPIN_LOCK Lock;
 305     LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
 306 } EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;