drivers/usb/usbehci_new/hardware.h

   1 #pragma once
   2
   3 #include <ntddk.h>
   4
   5 //
   6 // EHCI Operational Registers
   7 //
   8 #define EHCI_USBCMD                     0x00
   9 #define EHCI_USBSTS                     0x04
  10 #define EHCI_USBINTR                    0x08
  11 #define EHCI_FRINDEX                    0x0C
  12 #define EHCI_CTRLDSSEGMENT              0x10
  13 #define EHCI_PERIODICLISTBASE           0x14
  14 #define EHCI_ASYNCLISTBASE              0x18
  15 #define EHCI_CONFIGFLAG                 0x40
  16 #define EHCI_PORTSC                     0x44
  17
  18 //
  19 // Interrupt Register Flags
  20 //
  21 #define EHCI_USBINTR_INTE               0x01
  22 #define EHCI_USBINTR_ERR                0x02
  23 #define EHCI_USBINTR_PC                 0x04
  24 #define EHCI_USBINTR_FLROVR             0x08
  25 #define EHCI_USBINTR_HSERR              0x10
  26 #define EHCI_USBINTR_ASYNC              0x20
  27 // Bits 6:31 Reserved
  28
  29 //
  30 // Status Register Flags
  31 //
  32 #define EHCI_STS_INT                    0x01
  33 #define EHCI_STS_ERR                    0x02
  34 #define EHCI_STS_PCD                    0x04
  35 #define EHCI_STS_FLR                    0x08
  36 #define EHCI_STS_FATAL                  0x10
  37 #define EHCI_STS_IAA                    0x20
  38 // Bits 11:6 Reserved
  39 #define EHCI_STS_HALT                   0x1000
  40 #define EHCI_STS_RECL                   0x2000
  41 #define EHCI_STS_PSS                    0x4000
  42 #define EHCI_STS_ASS                    0x8000
  43 #define EHCI_ERROR_INT                  (EHCI_STS_FATAL | EHCI_STS_ERR)
  44
  45 //
  46 // Port Register Flags
  47 //
  48 #define EHCI_PRT_CONNECTED              0x01
  49 #define EHCI_PRT_CONNECTSTATUSCHANGE    0x02
  50 #define EHCI_PRT_ENABLED                0x04
  51 #define EHCI_PRT_ENABLEDSTATUSCHANGE    0x08
  52 #define EHCI_PRT_OVERCURRENTACTIVE      0x10
  53 #define EHCI_PRT_OVERCURRENTCHANGE      0x20
  54 #define EHCI_PRT_FORCERESUME            0x40
  55 #define EHCI_PRT_SUSPEND                0x80
  56 #define EHCI_PRT_RESET                  0x100
  57 #define EHCI_PRT_SLOWSPEEDLINE          0x400
  58 #define EHCI_PRT_POWER                  0x1000
  59 #define EHCI_PRT_RELEASEOWNERSHIP       0x2000
  60
  61 //
  62 // Terminate Pointer used for QueueHeads and Element Transfer Descriptors to mark Pointers as the end
  63 //
  64 #define TERMINATE_POINTER       0x01
  65
  66 //
  67 // QUEUE ELEMENT TRANSFER DESCRIPTOR, defines and structs
  68 //
  69
  70 //
  71 // Token Flags
  72 //
  73 #define PID_CODE_OUT_TOKEN      0x00
  74 #define PID_CODE_IN_TOKEN       0x01
  75 #define PID_CODE_SETUP_TOKEN    0x02
  76
  77 #define DO_START_SPLIT          0x00
  78 #define DO_COMPLETE_SPLIT       0x01
  79
  80 #define PING_STATE_DO_OUT       0x00
  81 #define PING_STATE_DO_PING      0x01
  82
  83 typedef struct _PERIODICFRAMELIST
  84 {
  85     PULONG VirtualAddr;
  86     PHYSICAL_ADDRESS PhysicalAddr;
  87     ULONG Size;
  88 } PERIODICFRAMELIST, *PPERIODICFRAMELIST;
  89
  90 //
  91 // QUEUE ELEMENT TRANSFER DESCRIPTOR TOKEN
  92 //
  93 typedef struct _QETD_TOKEN_BITS
  94 {
  95     ULONG PingState:1;
  96     ULONG SplitTransactionState:1;
  97     ULONG MissedMicroFrame:1;
  98     ULONG TransactionError:1;
  99     ULONG BabbleDetected:1;
 100     ULONG DataBufferError:1;
 101     ULONG Halted:1;
 102     ULONG Active:1;
 103     ULONG PIDCode:2;
 104     ULONG ErrorCounter:2;
 105     ULONG CurrentPage:3;
 106     ULONG InterruptOnComplete:1;
 107     ULONG TotalBytesToTransfer:15;
 108     ULONG DataToggle:1;
 109 } QETD_TOKEN_BITS, *PQETD_TOKEN_BITS;
 110
 111 //
 112 // QUEUE ELEMENT TRANSFER DESCRIPTOR
 113 //
 114 typedef struct _QUEUE_TRANSFER_DESCRIPTOR
 115 {
 116     //Hardware
 117     ULONG NextPointer;
 118     ULONG AlternateNextPointer;
 119     union
 120     {
 121         QETD_TOKEN_BITS Bits;
 122         ULONG DWord;
 123     } Token;
 124     ULONG BufferPointer[5];
 125
 126     //Software
 127     ULONG PhysicalAddr;
 128     LIST_ENTRY LinkedDescriptors;
 129 } QUEUE_TRANSFER_DESCRIPTOR, *PQUEUE_TRANSFER_DESCRIPTOR;
 130
 131 //
 132 // EndPointSpeeds Flags and END_POINT_CHARACTERISTICS
 133 //
 134 #define QH_ENDPOINT_FULLSPEED       0x00
 135 #define QH_ENDPOINT_LOWSPEED        0x01
 136 #define QH_ENDPOINT_HIGHSPEED       0x02
 137 typedef struct _END_POINT_CHARACTERISTICS
 138 {
 139     ULONG DeviceAddress:7;
 140     ULONG InactiveOnNextTransaction:1;
 141     ULONG EndPointNumber:4;
 142     ULONG EndPointSpeed:2;
 143     ULONG QEDTDataToggleControl:1;
 144     ULONG HeadOfReclamation:1;
 145     ULONG MaximumPacketLength:11;
 146     ULONG ControlEndPointFlag:1;
 147     ULONG NakCountReload:4;
 148 } END_POINT_CHARACTERISTICS, *PEND_POINT_CHARACTERISTICS;
 149
 150 //
 151 // Capabilities
 152 //
 153 typedef struct _END_POINT_CAPABILITIES
 154 {
 155     ULONG InterruptScheduleMask:8;
 156     ULONG SplitCompletionMask:8;
 157     ULONG HubAddr:6;
 158     ULONG PortNumber:6;
 159     ULONG NumberOfTransactionPerFrame:2;
 160 } END_POINT_CAPABILITIES, *PEND_POINT_CAPABILITIES;
 161
 162 //
 163 // QUEUE HEAD Flags and Struct
 164 //
 165 #define QH_TYPE_IDT             0x00
 166 #define QH_TYPE_QH              0x02
 167 #define QH_TYPE_SITD            0x04
 168 #define QH_TYPE_FSTN            0x06
 169
 170 typedef struct _QUEUE_HEAD
 171 {
 172     //Hardware
 173     ULONG HorizontalLinkPointer;
 174     END_POINT_CHARACTERISTICS EndPointCharacteristics;
 175     END_POINT_CAPABILITIES EndPointCapabilities;
 176     // TERMINATE_POINTER not valid for this member
 177     ULONG CurrentLinkPointer;
 178     // TERMINATE_POINTER valid
 179     ULONG NextPointer;
 180     // TERMINATE_POINTER valid, bits 1:4 is NAK_COUNTERd
 181     ULONG AlternateNextPointer;
 182     // Only DataToggle, InterruptOnComplete, ErrorCounter, PingState valid
 183     union
 184     {
 185         QETD_TOKEN_BITS Bits;
 186         ULONG DWord;
 187     } Token;
 188     ULONG BufferPointer[5];
 189
 190     //Software
 191     ULONG PhysicalAddr;
 192     LIST_ENTRY LinkedQueueHeads;
 193     PQUEUE_TRANSFER_DESCRIPTOR TransferDescriptor;
 194     PIRP IrpToComplete;
 195     PMDL Mdl;
 196     PKEVENT Event;
 197 } QUEUE_HEAD, *PQUEUE_HEAD;
 198
 199 //
 200 // Command register content
 201 //
 202 typedef struct _EHCI_USBCMD_CONTENT
 203 {
 204     ULONG Run : 1;
 205     ULONG HCReset : 1;
 206     ULONG FrameListSize : 2;
 207     ULONG PeriodicEnable : 1;
 208     ULONG AsyncEnable : 1;
 209     ULONG DoorBell : 1;
 210     ULONG LightReset : 1;
 211     ULONG AsyncParkCount : 2;
 212     ULONG Reserved : 1;
 213     ULONG AsyncParkEnable : 1;
 214     ULONG Reserved1 : 4;
 215     ULONG IntThreshold : 8;
 216     ULONG Reserved2 : 8;
 217 } EHCI_USBCMD_CONTENT, *PEHCI_USBCMD_CONTENT;
 218
 219 typedef struct _EHCI_HCS_CONTENT
 220 {
 221     ULONG PortCount : 4;
 222     ULONG PortPowerControl: 1;
 223     ULONG Reserved : 2;
 224     ULONG PortRouteRules : 1;
 225     ULONG PortPerCHC : 4;
 226     ULONG CHCCount : 4;
 227     ULONG PortIndicator : 1;
 228     ULONG Reserved2 : 3;
 229     ULONG DbgPortNum : 4;
 230     ULONG Reserved3 : 8;
 231
 232 } EHCI_HCS_CONTENT, *PEHCI_HCS_CONTENT;
 233
 234 typedef struct _EHCI_HCC_CONTENT
 235 {
 236     ULONG CurAddrBits : 1;
 237     ULONG VarFrameList : 1;
 238     ULONG ParkMode : 1;
 239     ULONG Reserved : 1;
 240     ULONG IsoSchedThreshold : 4;
 241     ULONG EECPCapable : 8;
 242     ULONG Reserved2 : 16;
 243
 244 } EHCI_HCC_CONTENT, *PEHCI_HCC_CONTENT;
 245
 246 typedef struct _EHCI_CAPS {
 247     UCHAR Length;
 248     UCHAR Reserved;
 249     USHORT HCIVersion;
 250     union
 251     {
 252         EHCI_HCS_CONTENT HCSParams;
 253         ULONG HCSParamsLong;
 254     };
 255     union
 256     {
 257         EHCI_HCC_CONTENT HCCParams;
 258         ULONG HCCParamsLong;
 259     };
 260     UCHAR PortRoute [8];
 261 } EHCI_CAPS, *PEHCI_CAPS;
 262
 263
 264 typedef struct
 265 {
 266     PKSPIN_LOCK Lock;
 267     RTL_BITMAP Bitmap;
 268     PULONG BitmapBuffer;
 269     ULONG BlockSize;
 270     PVOID VirtualBase;
 271     PHYSICAL_ADDRESS PhysicalBase;
 272     ULONG Length;
 273 }DMA_MEMORY_ALLOCATOR, *LPDMA_MEMORY_ALLOCATOR;
 274
 275 typedef struct _EHCI_HOST_CONTROLLER
 276 {
 277     ULONG OpRegisters;
 278     EHCI_CAPS ECHICaps;
 279     PVOID CommonBufferVA;
 280     PHYSICAL_ADDRESS CommonBufferPA;
 281     ULONG CommonBufferSize;
 282     PQUEUE_HEAD AsyncListQueue;
 283     KSPIN_LOCK Lock;
 284     LPDMA_MEMORY_ALLOCATOR DmaMemAllocator;
 285 } EHCI_HOST_CONTROLLER, *PEHCI_HOST_CONTROLLER;