[USBOHCI]
[reactos.git] / drivers / usb / usbohci / hardware.cpp
1 /*
2 * PROJECT: ReactOS Universal Serial Bus Bulk Enhanced Host Controller Interface
3 * LICENSE: GPL - See COPYING in the top level directory
4 * FILE: drivers/usb/usbohci/hcd_controller.cpp
5 * PURPOSE: USB OHCI device driver.
6 * PROGRAMMERS:
7 * Michael Martin (michael.martin@reactos.org)
8 * Johannes Anderwald (johannes.anderwald@reactos.org)
9 */
10
11 #define INITGUID
12 #include "usbohci.h"
13 #include "hardware.h"
14
15 typedef VOID __stdcall HD_INIT_CALLBACK(IN PVOID CallBackContext);
16
17 BOOLEAN
18 NTAPI
19 InterruptServiceRoutine(
20 IN PKINTERRUPT Interrupt,
21 IN PVOID ServiceContext);
22
23 VOID
24 NTAPI
25 OhciDefferedRoutine(
26 IN PKDPC Dpc,
27 IN PVOID DeferredContext,
28 IN PVOID SystemArgument1,
29 IN PVOID SystemArgument2);
30
31 VOID
32 NTAPI
33 StatusChangeWorkItemRoutine(PVOID Context);
34
35 class CUSBHardwareDevice : public IUSBHardwareDevice
36 {
37 public:
38 STDMETHODIMP QueryInterface( REFIID InterfaceId, PVOID* Interface);
39
40 STDMETHODIMP_(ULONG) AddRef()
41 {
42 InterlockedIncrement(&m_Ref);
43 return m_Ref;
44 }
45 STDMETHODIMP_(ULONG) Release()
46 {
47 InterlockedDecrement(&m_Ref);
48
49 if (!m_Ref)
50 {
51 delete this;
52 return 0;
53 }
54 return m_Ref;
55 }
56 // com
57 NTSTATUS Initialize(PDRIVER_OBJECT DriverObject, PDEVICE_OBJECT FunctionalDeviceObject, PDEVICE_OBJECT PhysicalDeviceObject, PDEVICE_OBJECT LowerDeviceObject);
58 NTSTATUS PnpStart(PCM_RESOURCE_LIST RawResources, PCM_RESOURCE_LIST TranslatedResources);
59 NTSTATUS PnpStop(void);
60 NTSTATUS HandlePower(PIRP Irp);
61 NTSTATUS GetDeviceDetails(PUSHORT VendorId, PUSHORT DeviceId, PULONG NumberOfPorts, PULONG Speed);
62 NTSTATUS GetBulkHeadEndpointDescriptor(struct _OHCI_ENDPOINT_DESCRIPTOR ** OutDescriptor);
63 NTSTATUS GetControlHeadEndpointDescriptor(struct _OHCI_ENDPOINT_DESCRIPTOR ** OutDescriptor);
64 NTSTATUS GetInterruptEndpointDescriptors(struct _OHCI_ENDPOINT_DESCRIPTOR *** OutDescriptor);
65 NTSTATUS GetIsochronousHeadEndpointDescriptor(struct _OHCI_ENDPOINT_DESCRIPTOR ** OutDescriptor);
66 VOID HeadEndpointDescriptorModified(ULONG HeadType);
67
68
69 NTSTATUS GetDMA(OUT struct IDMAMemoryManager **m_DmaManager);
70 NTSTATUS GetUSBQueue(OUT struct IUSBQueue **OutUsbQueue);
71
72 NTSTATUS StartController();
73 NTSTATUS StopController();
74 NTSTATUS ResetController();
75 NTSTATUS ResetPort(ULONG PortIndex);
76
77 NTSTATUS GetPortStatus(ULONG PortId, OUT USHORT *PortStatus, OUT USHORT *PortChange);
78 NTSTATUS ClearPortStatus(ULONG PortId, ULONG Status);
79 NTSTATUS SetPortFeature(ULONG PortId, ULONG Feature);
80
81 VOID SetStatusChangeEndpointCallBack(PVOID CallBack, PVOID Context);
82
83 KIRQL AcquireDeviceLock(void);
84 VOID ReleaseDeviceLock(KIRQL OldLevel);
85 virtual VOID GetCurrentFrameNumber(PULONG FrameNumber);
86 // local
87 BOOLEAN InterruptService();
88 NTSTATUS InitializeController();
89 NTSTATUS AllocateEndpointDescriptor(OUT POHCI_ENDPOINT_DESCRIPTOR *OutDescriptor);
90
91 // friend function
92 friend BOOLEAN NTAPI InterruptServiceRoutine(IN PKINTERRUPT Interrupt, IN PVOID ServiceContext);
93 friend VOID NTAPI OhciDefferedRoutine(IN PKDPC Dpc, IN PVOID DeferredContext, IN PVOID SystemArgument1, IN PVOID SystemArgument2);
94 friend VOID NTAPI StatusChangeWorkItemRoutine(PVOID Context);
95 // constructor / destructor
96 CUSBHardwareDevice(IUnknown *OuterUnknown){}
97 virtual ~CUSBHardwareDevice(){}
98
99 protected:
100 LONG m_Ref; // reference count
101 PDRIVER_OBJECT m_DriverObject; // driver object
102 PDEVICE_OBJECT m_PhysicalDeviceObject; // pdo
103 PDEVICE_OBJECT m_FunctionalDeviceObject; // fdo (hcd controller)
104 PDEVICE_OBJECT m_NextDeviceObject; // lower device object
105 KSPIN_LOCK m_Lock; // hardware lock
106 PKINTERRUPT m_Interrupt; // interrupt object
107 KDPC m_IntDpcObject; // dpc object for deferred isr processing
108 PVOID VirtualBase; // virtual base for memory manager
109 PHYSICAL_ADDRESS PhysicalAddress; // physical base for memory manager
110 PULONG m_Base; // OHCI operational port base registers
111 PDMA_ADAPTER m_Adapter; // dma adapter object
112 ULONG m_MapRegisters; // map registers count
113 USHORT m_VendorID; // vendor id
114 USHORT m_DeviceID; // device id
115 PUSBQUEUE m_UsbQueue; // usb request queue
116 POHCIHCCA m_HCCA; // hcca virtual base
117 PHYSICAL_ADDRESS m_HCCAPhysicalAddress; // hcca physical address
118 POHCI_ENDPOINT_DESCRIPTOR m_ControlEndpointDescriptor; // dummy control endpoint descriptor
119 POHCI_ENDPOINT_DESCRIPTOR m_BulkEndpointDescriptor; // dummy control endpoint descriptor
120 POHCI_ENDPOINT_DESCRIPTOR m_IsoEndpointDescriptor; // iso endpoint descriptor
121 POHCI_ENDPOINT_DESCRIPTOR m_InterruptEndpoints[OHCI_STATIC_ENDPOINT_COUNT]; // endpoints for interrupt / iso transfers
122 ULONG m_NumberOfPorts; // number of ports
123 OHCI_PORT_STATUS m_PortStatus[OHCI_MAX_PORT_COUNT]; // port change status
124 PDMAMEMORYMANAGER m_MemoryManager; // memory manager
125 HD_INIT_CALLBACK* m_SCECallBack; // status change callback routine
126 PVOID m_SCEContext; // status change callback routine context
127 WORK_QUEUE_ITEM m_StatusChangeWorkItem; // work item for status change callback
128 ULONG m_SyncFramePhysAddr; // periodic frame list physical address
129 ULONG m_IntervalValue; // periodic interval value
130 };
131
132 //=================================================================================================
133 // COM
134 //
135 NTSTATUS
136 STDMETHODCALLTYPE
137 CUSBHardwareDevice::QueryInterface(
138 IN REFIID refiid,
139 OUT PVOID* Output)
140 {
141 if (IsEqualGUIDAligned(refiid, IID_IUnknown))
142 {
143 *Output = PVOID(PUNKNOWN(this));
144 PUNKNOWN(*Output)->AddRef();
145 return STATUS_SUCCESS;
146 }
147
148 return STATUS_UNSUCCESSFUL;
149 }
150
151 NTSTATUS
152 CUSBHardwareDevice::Initialize(
153 PDRIVER_OBJECT DriverObject,
154 PDEVICE_OBJECT FunctionalDeviceObject,
155 PDEVICE_OBJECT PhysicalDeviceObject,
156 PDEVICE_OBJECT LowerDeviceObject)
157 {
158 BUS_INTERFACE_STANDARD BusInterface;
159 PCI_COMMON_CONFIG PciConfig;
160 NTSTATUS Status;
161 ULONG BytesRead;
162
163 DPRINT1("CUSBHardwareDevice::Initialize\n");
164
165 //
166 // Create DMAMemoryManager for use with QueueHeads and Transfer Descriptors.
167 //
168 Status = CreateDMAMemoryManager(&m_MemoryManager);
169 if (!NT_SUCCESS(Status))
170 {
171 DPRINT1("Failed to create DMAMemoryManager Object\n");
172 return Status;
173 }
174
175 //
176 // Create the UsbQueue class that will handle the Asynchronous and Periodic Schedules
177 //
178 Status = CreateUSBQueue(&m_UsbQueue);
179 if (!NT_SUCCESS(Status))
180 {
181 DPRINT1("Failed to create UsbQueue!\n");
182 return Status;
183 }
184
185 //
186 // store device objects
187 //
188 m_DriverObject = DriverObject;
189 m_FunctionalDeviceObject = FunctionalDeviceObject;
190 m_PhysicalDeviceObject = PhysicalDeviceObject;
191 m_NextDeviceObject = LowerDeviceObject;
192
193 //
194 // initialize device lock
195 //
196 KeInitializeSpinLock(&m_Lock);
197
198 //
199 // intialize status change work item
200 //
201 ExInitializeWorkItem(&m_StatusChangeWorkItem, StatusChangeWorkItemRoutine, PVOID(this));
202
203 m_VendorID = 0;
204 m_DeviceID = 0;
205
206 Status = GetBusInterface(PhysicalDeviceObject, &BusInterface);
207 if (!NT_SUCCESS(Status))
208 {
209 DPRINT1("Failed to get BusInteface!\n");
210 return Status;
211 }
212
213 BytesRead = (*BusInterface.GetBusData)(BusInterface.Context,
214 PCI_WHICHSPACE_CONFIG,
215 &PciConfig,
216 0,
217 PCI_COMMON_HDR_LENGTH);
218
219 if (BytesRead != PCI_COMMON_HDR_LENGTH)
220 {
221 DPRINT1("Failed to get pci config information!\n");
222 return STATUS_SUCCESS;
223 }
224
225 if (!(PciConfig.Command & PCI_ENABLE_BUS_MASTER))
226 {
227 DPRINT1("PCI Configuration shows this as a non Bus Mastering device!\n");
228 }
229
230 m_VendorID = PciConfig.VendorID;
231 m_DeviceID = PciConfig.DeviceID;
232
233 return STATUS_SUCCESS;
234 }
235
236 NTSTATUS
237 CUSBHardwareDevice::PnpStart(
238 PCM_RESOURCE_LIST RawResources,
239 PCM_RESOURCE_LIST TranslatedResources)
240 {
241 ULONG Index;
242 PCM_PARTIAL_RESOURCE_DESCRIPTOR ResourceDescriptor;
243 DEVICE_DESCRIPTION DeviceDescription;
244 PVOID ResourceBase;
245 NTSTATUS Status;
246 ULONG Version;
247
248 DPRINT1("CUSBHardwareDevice::PnpStart\n");
249 for(Index = 0; Index < TranslatedResources->List[0].PartialResourceList.Count; Index++)
250 {
251 //
252 // get resource descriptor
253 //
254 ResourceDescriptor = &TranslatedResources->List[0].PartialResourceList.PartialDescriptors[Index];
255
256 switch(ResourceDescriptor->Type)
257 {
258 case CmResourceTypeInterrupt:
259 {
260 KeInitializeDpc(&m_IntDpcObject,
261 OhciDefferedRoutine,
262 this);
263
264 Status = IoConnectInterrupt(&m_Interrupt,
265 InterruptServiceRoutine,
266 (PVOID)this,
267 NULL,
268 ResourceDescriptor->u.Interrupt.Vector,
269 (KIRQL)ResourceDescriptor->u.Interrupt.Level,
270 (KIRQL)ResourceDescriptor->u.Interrupt.Level,
271 (KINTERRUPT_MODE)(ResourceDescriptor->Flags & CM_RESOURCE_INTERRUPT_LATCHED),
272 (ResourceDescriptor->ShareDisposition != CmResourceShareDeviceExclusive),
273 ResourceDescriptor->u.Interrupt.Affinity,
274 FALSE);
275
276 if (!NT_SUCCESS(Status))
277 {
278 //
279 // failed to register interrupt
280 //
281 DPRINT1("IoConnect Interrupt failed with %x\n", Status);
282 return Status;
283 }
284 break;
285 }
286 case CmResourceTypeMemory:
287 {
288 //
289 // get resource base
290 //
291 ResourceBase = MmMapIoSpace(ResourceDescriptor->u.Memory.Start, ResourceDescriptor->u.Memory.Length, MmNonCached);
292 if (!ResourceBase)
293 {
294 //
295 // failed to map registers
296 //
297 DPRINT1("MmMapIoSpace failed\n");
298 return STATUS_INSUFFICIENT_RESOURCES;
299 }
300
301 //
302 // Get controllers capabilities
303 //
304 Version = READ_REGISTER_ULONG((PULONG)((ULONG_PTR)ResourceBase + OHCI_REVISION_OFFSET));
305
306 DPRINT1("Version %x\n", Version);
307
308 //
309 // Store Resource base
310 //
311 m_Base = (PULONG)ResourceBase;
312 break;
313 }
314 }
315 }
316
317
318 //
319 // zero device description
320 //
321 RtlZeroMemory(&DeviceDescription, sizeof(DEVICE_DESCRIPTION));
322
323 //
324 // initialize device description
325 //
326 DeviceDescription.Version = DEVICE_DESCRIPTION_VERSION;
327 DeviceDescription.Master = TRUE;
328 DeviceDescription.ScatterGather = TRUE;
329 DeviceDescription.Dma32BitAddresses = TRUE;
330 DeviceDescription.DmaWidth = Width32Bits;
331 DeviceDescription.InterfaceType = PCIBus;
332 DeviceDescription.MaximumLength = MAXULONG;
333
334 //
335 // get dma adapter
336 //
337 m_Adapter = IoGetDmaAdapter(m_PhysicalDeviceObject, &DeviceDescription, &m_MapRegisters);
338 if (!m_Adapter)
339 {
340 //
341 // failed to get dma adapter
342 //
343 DPRINT1("Failed to acquire dma adapter\n");
344 return STATUS_INSUFFICIENT_RESOURCES;
345 }
346
347 //
348 // Create Common Buffer
349 //
350 VirtualBase = m_Adapter->DmaOperations->AllocateCommonBuffer(m_Adapter,
351 PAGE_SIZE * 4,
352 &PhysicalAddress,
353 FALSE);
354 if (!VirtualBase)
355 {
356 DPRINT1("Failed to allocate a common buffer\n");
357 return STATUS_INSUFFICIENT_RESOURCES;
358 }
359
360 //
361 // Initialize the DMAMemoryManager
362 //
363 Status = m_MemoryManager->Initialize(this, &m_Lock, PAGE_SIZE * 4, VirtualBase, PhysicalAddress, 32);
364 if (!NT_SUCCESS(Status))
365 {
366 DPRINT1("Failed to initialize the DMAMemoryManager\n");
367 return Status;
368 }
369
370 //
371 // initializes the controller
372 //
373 Status = InitializeController();
374 if (!NT_SUCCESS(Status))
375 {
376 DPRINT1("Failed to Initialize the controller \n");
377 ASSERT(FALSE);
378 return Status;
379 }
380
381 //
382 // Initialize the UsbQueue now that we have an AdapterObject.
383 //
384 Status = m_UsbQueue->Initialize(PUSBHARDWAREDEVICE(this), m_Adapter, m_MemoryManager, NULL);
385 if (!NT_SUCCESS(Status))
386 {
387 DPRINT1("Failed to Initialize the UsbQueue\n");
388 return Status;
389 }
390
391
392 //
393 // Stop the controller before modifying schedules
394 //
395 Status = StopController();
396 if (!NT_SUCCESS(Status))
397 {
398 DPRINT1("Failed to stop the controller \n");
399 ASSERT(FALSE);
400 return Status;
401 }
402
403
404 //
405 // Start the controller
406 //
407 DPRINT1("Starting Controller\n");
408 Status = StartController();
409
410 //
411 // done
412 //
413 return Status;
414 }
415
416 NTSTATUS
417 CUSBHardwareDevice::PnpStop(void)
418 {
419 UNIMPLEMENTED
420 return STATUS_NOT_IMPLEMENTED;
421 }
422
423 NTSTATUS
424 CUSBHardwareDevice::HandlePower(
425 PIRP Irp)
426 {
427 UNIMPLEMENTED
428 return STATUS_NOT_IMPLEMENTED;
429 }
430
431 NTSTATUS
432 CUSBHardwareDevice::GetDeviceDetails(
433 OUT OPTIONAL PUSHORT VendorId,
434 OUT OPTIONAL PUSHORT DeviceId,
435 OUT OPTIONAL PULONG NumberOfPorts,
436 OUT OPTIONAL PULONG Speed)
437 {
438 if (VendorId)
439 {
440 //
441 // get vendor
442 //
443 *VendorId = m_VendorID;
444 }
445
446 if (DeviceId)
447 {
448 //
449 // get device id
450 //
451 *DeviceId = m_DeviceID;
452 }
453
454 if (NumberOfPorts)
455 {
456 //
457 // get number of ports
458 //
459 *NumberOfPorts = m_NumberOfPorts;
460 }
461
462 if (Speed)
463 {
464 //
465 // speed is 0x100
466 //
467 *Speed = 0x100;
468 }
469
470 return STATUS_SUCCESS;
471 }
472
473 NTSTATUS CUSBHardwareDevice::GetDMA(
474 OUT struct IDMAMemoryManager **OutDMAMemoryManager)
475 {
476 if (!m_MemoryManager)
477 return STATUS_UNSUCCESSFUL;
478 *OutDMAMemoryManager = m_MemoryManager;
479 return STATUS_SUCCESS;
480 }
481
482 NTSTATUS
483 CUSBHardwareDevice::GetUSBQueue(
484 OUT struct IUSBQueue **OutUsbQueue)
485 {
486 if (!m_UsbQueue)
487 return STATUS_UNSUCCESSFUL;
488 *OutUsbQueue = m_UsbQueue;
489 return STATUS_SUCCESS;
490 }
491
492
493 NTSTATUS
494 CUSBHardwareDevice::StartController(void)
495 {
496 ULONG Control, NumberOfPorts, Index, Descriptor, FrameInterval, Periodic;
497
498 //
499 // first write address of HCCA
500 //
501 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_HCCA_OFFSET), m_HCCAPhysicalAddress.LowPart);
502
503 //
504 // lets write physical address of dummy control endpoint descriptor
505 //
506 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_HEAD_ED_OFFSET), m_ControlEndpointDescriptor->PhysicalAddress.LowPart);
507
508 //
509 // lets write physical address of dummy bulk endpoint descriptor
510 //
511 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_BULK_HEAD_ED_OFFSET), m_BulkEndpointDescriptor->PhysicalAddress.LowPart);
512
513 //
514 // read control register
515 //
516 Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
517
518 //
519 // remove flags
520 //
521 Control &= ~(OHCI_CONTROL_BULK_SERVICE_RATIO_MASK | OHCI_ENABLE_LIST | OHCI_HC_FUNCTIONAL_STATE_MASK | OHCI_INTERRUPT_ROUTING);
522
523 //
524 // set command status flags
525 //
526 Control |= OHCI_ENABLE_LIST | OHCI_CONTROL_BULK_RATIO_1_4 | OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL;
527
528 //
529 // now start the controller
530 //
531 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), Control);
532
533 //
534 // wait a bit
535 //
536 KeStallExecutionProcessor(100);
537
538 //
539 // is the controller started
540 //
541 Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
542
543 //
544 // assert that the controller has been started
545 //
546 ASSERT((Control & OHCI_HC_FUNCTIONAL_STATE_MASK) == OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL);
547 ASSERT((Control & OHCI_ENABLE_LIST) == OHCI_ENABLE_LIST);
548
549 //
550 // get frame interval
551 //
552 FrameInterval = (READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET)) & OHCI_FRAME_INTERVAL_TOGGLE) ^ OHCI_FRAME_INTERVAL_TOGGLE;
553 FrameInterval |= OHCI_FSMPS(m_IntervalValue) | m_IntervalValue;
554
555 //
556 // write frame interval
557 //
558 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET), FrameInterval);
559
560 //
561 // 90 % periodic
562 //
563 Periodic = OHCI_PERIODIC(m_IntervalValue);
564 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_PERIODIC_START_OFFSET), Periodic);
565
566
567 //
568 // read descriptor
569 //
570 Descriptor = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_DESCRIPTOR_A_OFFSET));
571
572 //
573 // no over current protection
574 //
575 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_DESCRIPTOR_A_OFFSET), Descriptor | OHCI_RH_NO_OVER_CURRENT_PROTECTION);
576
577 //
578 // enable power on all ports
579 //
580 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_STATUS_OFFSET), OHCI_RH_LOCAL_POWER_STATUS_CHANGE);
581
582 //
583 // wait a bit
584 //
585 KeStallExecutionProcessor(10);
586
587 //
588 // write descriptor
589 //
590 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_DESCRIPTOR_A_OFFSET), Descriptor);
591
592
593
594 //
595 // retrieve number of ports
596 //
597 for(Index = 0; Index < 10; Index++)
598 {
599 //
600 // wait a bit
601 //
602 KeStallExecutionProcessor(10);
603
604 //
605 // read descriptor
606 //
607 Descriptor = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_DESCRIPTOR_A_OFFSET));
608
609 //
610 // get number of ports
611 //
612 NumberOfPorts = OHCI_RH_GET_PORT_COUNT(Descriptor);
613
614 //
615 // check if we have received the ports
616 //
617 if (NumberOfPorts)
618 break;
619 }
620
621 //
622 // sanity check
623 //
624 ASSERT(NumberOfPorts < OHCI_MAX_PORT_COUNT);
625
626 //
627 // store number of ports
628 //
629 m_NumberOfPorts = NumberOfPorts;
630
631 //
632 // print out number ports
633 //
634 DPRINT1("NumberOfPorts %lu\n", m_NumberOfPorts);
635
636
637 //
638 // now enable the interrupts
639 //
640 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_ENABLE_OFFSET), OHCI_NORMAL_INTERRUPTS | OHCI_MASTER_INTERRUPT_ENABLE);
641
642 //
643 // done
644 //
645 return STATUS_SUCCESS;
646 }
647
648 NTSTATUS
649 CUSBHardwareDevice::AllocateEndpointDescriptor(
650 OUT POHCI_ENDPOINT_DESCRIPTOR *OutDescriptor)
651 {
652 POHCI_ENDPOINT_DESCRIPTOR Descriptor;
653 PHYSICAL_ADDRESS DescriptorAddress;
654 NTSTATUS Status;
655
656 //
657 // allocate descriptor
658 //
659 Status = m_MemoryManager->Allocate(sizeof(OHCI_ENDPOINT_DESCRIPTOR), (PVOID*)&Descriptor, &DescriptorAddress);
660 if (!NT_SUCCESS(Status))
661 {
662 //
663 // failed to allocate descriptor
664 //
665 return Status;
666 }
667
668 //
669 // intialize descriptor
670 //
671 Descriptor->Flags = OHCI_ENDPOINT_SKIP;
672 Descriptor->HeadPhysicalDescriptor = 0;
673 Descriptor->NextPhysicalEndpoint = 0;
674 Descriptor->TailPhysicalDescriptor = 0;
675 Descriptor->PhysicalAddress.QuadPart = DescriptorAddress.QuadPart;
676
677 //
678 // store result
679 //
680 *OutDescriptor = Descriptor;
681
682 //
683 // done
684 //
685 return STATUS_SUCCESS;
686 }
687
688 NTSTATUS
689 CUSBHardwareDevice::GetBulkHeadEndpointDescriptor(
690 struct _OHCI_ENDPOINT_DESCRIPTOR ** OutDescriptor)
691 {
692 *OutDescriptor = m_BulkEndpointDescriptor;
693 return STATUS_SUCCESS;
694 }
695
696 NTSTATUS
697 CUSBHardwareDevice::GetInterruptEndpointDescriptors(
698 struct _OHCI_ENDPOINT_DESCRIPTOR *** OutDescriptor)
699 {
700 *OutDescriptor = m_InterruptEndpoints;
701 return STATUS_SUCCESS;
702 }
703
704 NTSTATUS
705 CUSBHardwareDevice::GetIsochronousHeadEndpointDescriptor(
706 struct _OHCI_ENDPOINT_DESCRIPTOR ** OutDescriptor)
707 {
708 //
709 // get descriptor
710 //
711 *OutDescriptor = m_IsoEndpointDescriptor;
712 return STATUS_SUCCESS;
713 }
714
715 VOID
716 CUSBHardwareDevice::HeadEndpointDescriptorModified(
717 ULONG Type)
718 {
719 ULONG Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET));
720
721 if (Type == USB_ENDPOINT_TYPE_CONTROL)
722 {
723 //
724 // notify controller
725 //
726 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET), Value | OHCI_CONTROL_LIST_FILLED);
727 }
728 else if (Type == USB_ENDPOINT_TYPE_BULK)
729 {
730 //
731 // notify controller
732 //
733 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET), Value | OHCI_BULK_LIST_FILLED);
734 }
735 }
736
737 NTSTATUS
738 CUSBHardwareDevice::GetControlHeadEndpointDescriptor(
739 struct _OHCI_ENDPOINT_DESCRIPTOR ** OutDescriptor)
740 {
741 *OutDescriptor = m_ControlEndpointDescriptor;
742 return STATUS_SUCCESS;
743 }
744
745 NTSTATUS
746 CUSBHardwareDevice::InitializeController()
747 {
748 NTSTATUS Status;
749 ULONG Index, Interval, IntervalIndex, InsertIndex;
750 POHCI_ENDPOINT_DESCRIPTOR Descriptor;
751
752 //
753 // first allocate the hcca area
754 //
755 Status = m_MemoryManager->Allocate(sizeof(OHCIHCCA), (PVOID*)&m_HCCA, &m_HCCAPhysicalAddress);
756 if (!NT_SUCCESS(Status))
757 {
758 //
759 // no memory
760 //
761 return Status;
762 }
763
764 //
765 // now allocate an endpoint for control transfers
766 // this endpoint will never be removed
767 //
768 Status = AllocateEndpointDescriptor(&m_ControlEndpointDescriptor);
769 if (!NT_SUCCESS(Status))
770 {
771 //
772 // no memory
773 //
774 return Status;
775 }
776
777 //
778 // now allocate an endpoint for bulk transfers
779 // this endpoint will never be removed
780 //
781 Status = AllocateEndpointDescriptor(&m_BulkEndpointDescriptor);
782 if (!NT_SUCCESS(Status))
783 {
784 //
785 // no memory
786 //
787 return Status;
788 }
789
790 //
791 // now allocate an endpoint for iso transfers
792 // this endpoint will never be removed
793 //
794 Status = AllocateEndpointDescriptor(&m_IsoEndpointDescriptor);
795 if (!NT_SUCCESS(Status))
796 {
797 //
798 // no memory
799 //
800 return Status;
801 }
802
803 //
804 // now allocate endpoint descriptors for iso / interrupt transfers interval is 1,2,4,8,16,32
805 //
806 for(Index = 0; Index < OHCI_STATIC_ENDPOINT_COUNT; Index++)
807 {
808 //
809 // allocate endpoint descriptor
810 //
811 Status = AllocateEndpointDescriptor(&Descriptor);
812 if (!NT_SUCCESS(Status))
813 {
814 //
815 // no memory
816 //
817 return Status;
818 }
819
820 //
821 // save in array
822 //
823 m_InterruptEndpoints[Index] = Descriptor;
824 }
825
826
827 //
828 // now link the descriptors, taken from Haiku
829 //
830 Interval = OHCI_BIGGEST_INTERVAL;
831 IntervalIndex = OHCI_STATIC_ENDPOINT_COUNT - 1;
832 while (Interval > 1)
833 {
834 InsertIndex = Interval / 2;
835 while (InsertIndex < OHCI_BIGGEST_INTERVAL)
836 {
837 //
838 // assign endpoint address
839 //
840 m_HCCA->InterruptTable[InsertIndex] = m_InterruptEndpoints[IntervalIndex]->PhysicalAddress.LowPart;
841 InsertIndex += Interval;
842 }
843
844 IntervalIndex--;
845 Interval /= 2;
846 }
847
848 //
849 // link all endpoint descriptors to first descriptor in array
850 //
851 m_HCCA->InterruptTable[0] = m_InterruptEndpoints[0]->PhysicalAddress.LowPart;
852 for (Index = 1; Index < OHCI_STATIC_ENDPOINT_COUNT; Index++)
853 {
854 //
855 // link descriptor
856 //
857 m_InterruptEndpoints[Index]->NextPhysicalEndpoint = m_InterruptEndpoints[0]->PhysicalAddress.LowPart;
858 }
859
860 //
861 // Now link the first endpoint to the isochronous endpoint
862 //
863 m_InterruptEndpoints[0]->NextPhysicalEndpoint = m_IsoEndpointDescriptor->PhysicalAddress.LowPart;
864
865 //
866 // set iso endpoint type
867 //
868 m_IsoEndpointDescriptor->Flags |= OHCI_ENDPOINT_ISOCHRONOUS_FORMAT;
869
870 //
871 // done
872 //
873 return STATUS_SUCCESS;
874 }
875
876 NTSTATUS
877 CUSBHardwareDevice::StopController(void)
878 {
879 ULONG Control, Reset;
880 ULONG Index, FrameInterval;
881
882 //
883 // first turn off all interrupts
884 //
885 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_DISABLE_OFFSET), OHCI_ALL_INTERRUPTS);
886
887 //
888 // check context
889 //
890 Control = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET));
891
892 //
893 // FIXME: support routing
894 //
895 ASSERT((Control & OHCI_INTERRUPT_ROUTING) == 0);
896
897 //
898 // have a break
899 //
900 KeStallExecutionProcessor(100);
901
902 //
903 // some controllers also depend on this
904 //
905 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_CONTROL_OFFSET), OHCI_HC_FUNCTIONAL_STATE_RESET);
906
907 //
908 // wait a bit
909 //
910 KeStallExecutionProcessor(100);
911
912 //
913 // read from interval
914 //
915 FrameInterval = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_FRAME_INTERVAL_OFFSET));
916
917 //
918 // store interval value for later
919 //
920 m_IntervalValue = OHCI_GET_INTERVAL_VALUE(FrameInterval);
921
922 //
923 // now reset controller
924 //
925 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET), OHCI_HOST_CONTROLLER_RESET);
926
927 //
928 // reset time is 10ms
929 //
930 for(Index = 0; Index < 10; Index++)
931 {
932 //
933 // wait a bit
934 //
935 KeStallExecutionProcessor(10);
936
937 //
938 // read command status
939 //
940 Reset = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_COMMAND_STATUS_OFFSET));
941
942 //
943 // was reset bit cleared
944 //
945 if ((Reset & OHCI_HOST_CONTROLLER_RESET) == 0)
946 {
947 //
948 // controller completed reset
949 //
950 return STATUS_SUCCESS;
951 }
952 }
953
954 //
955 // failed to reset controller
956 //
957 return STATUS_UNSUCCESSFUL;
958 }
959
960 NTSTATUS
961 CUSBHardwareDevice::ResetController(void)
962 {
963 UNIMPLEMENTED
964 return STATUS_NOT_IMPLEMENTED;
965 }
966
967 NTSTATUS
968 CUSBHardwareDevice::ResetPort(
969 IN ULONG PortIndex)
970 {
971 ASSERT(FALSE);
972
973 return STATUS_SUCCESS;
974 }
975
976 NTSTATUS
977 CUSBHardwareDevice::GetPortStatus(
978 ULONG PortId,
979 OUT USHORT *PortStatus,
980 OUT USHORT *PortChange)
981 {
982 //
983 // FIXME: should read status from hardware
984 //
985 *PortStatus = m_PortStatus[PortId].PortStatus;
986 *PortChange = m_PortStatus[PortId].PortChange;
987 return STATUS_SUCCESS;
988 }
989
990 NTSTATUS
991 CUSBHardwareDevice::ClearPortStatus(
992 ULONG PortId,
993 ULONG Status)
994 {
995 ULONG Value, Index = 0;
996
997 DPRINT("CUSBHardwareDevice::ClearPortStatus PortId %x Feature %x\n", PortId, Status);
998
999 if (PortId > m_NumberOfPorts)
1000 return STATUS_UNSUCCESSFUL;
1001
1002 Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)));
1003 KeStallExecutionProcessor(100);
1004
1005 if (Status == C_PORT_RESET)
1006 {
1007 do
1008 {
1009 //
1010 // read port status
1011 //
1012 Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)));
1013
1014 if ((Value & OHCI_RH_PORTSTATUS_PRS) == 0)
1015 {
1016 //
1017 // reset is complete
1018 //
1019 break;
1020 }
1021
1022 //
1023 // wait a bit
1024 //
1025 KeStallExecutionProcessor(100);
1026
1027 //DPRINT1("Value %x Index %lu\n", Value, Index);
1028
1029 }while(TRUE);
1030
1031 //
1032 // check if reset bit is still set
1033 //
1034 if (Value & OHCI_RH_PORTSTATUS_PRS)
1035 {
1036 //
1037 // reset failed
1038 //
1039 DPRINT1("PortId %lu Reset failed\n", PortId);
1040 return STATUS_UNSUCCESSFUL;
1041 }
1042
1043 //
1044 // sanity checks
1045 //
1046 ASSERT((Value & OHCI_RH_PORTSTATUS_PRS) == 0);
1047 ASSERT((Value & OHCI_RH_PORTSTATUS_PRSC));
1048
1049 //
1050 // clear reset bit complete
1051 //
1052 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)), OHCI_RH_PORTSTATUS_PRSC);
1053
1054 //
1055 // read status register
1056 //
1057 Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)));
1058
1059 //
1060 // reset complete bit should be cleared
1061 //
1062 ASSERT((Value & OHCI_RH_PORTSTATUS_PRSC) == 0);
1063
1064 //
1065 // update port status
1066 //
1067 m_PortStatus[PortId].PortChange &= ~USB_PORT_STATUS_RESET;
1068
1069 //
1070 // sanity check
1071 //
1072 ASSERT((Value & OHCI_RH_PORTSTATUS_PES));
1073
1074 //
1075 // port is enabled
1076 //
1077 m_PortStatus[PortId].PortStatus |= USB_PORT_STATUS_ENABLE;
1078
1079 //
1080 // re-enable root hub change
1081 //
1082 Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_ENABLE_OFFSET));
1083 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_INTERRUPT_ENABLE_OFFSET), Value | OHCI_ROOT_HUB_STATUS_CHANGE);
1084
1085 }
1086
1087 if (Status == C_PORT_CONNECTION)
1088 {
1089 //
1090 // clear bit
1091 //
1092 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)), OHCI_RH_PORTSTATUS_CSC);
1093 m_PortStatus[PortId].PortChange &= ~USB_PORT_STATUS_CONNECT;
1094 }
1095
1096
1097
1098 return STATUS_SUCCESS;
1099 }
1100
1101
1102 NTSTATUS
1103 CUSBHardwareDevice::SetPortFeature(
1104 ULONG PortId,
1105 ULONG Feature)
1106 {
1107 ULONG Value;
1108
1109 DPRINT1("CUSBHardwareDevice::SetPortFeature PortId %x Feature %x\n", PortId, Feature);
1110
1111 //
1112 // read port status
1113 //
1114 Value = READ_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)));
1115
1116
1117 if (Feature == PORT_ENABLE)
1118 {
1119 //
1120 // enable port
1121 //
1122 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)), OHCI_RH_PORTSTATUS_PES);
1123 return STATUS_SUCCESS;
1124 }
1125 else if (Feature == PORT_POWER)
1126 {
1127 //
1128 // enable power
1129 //
1130 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)), OHCI_RH_PORTSTATUS_PPS);
1131 return STATUS_SUCCESS;
1132 }
1133 else if (Feature == PORT_SUSPEND)
1134 {
1135 //
1136 // enable port
1137 //
1138 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)), OHCI_RH_PORTSTATUS_PSS);
1139 return STATUS_SUCCESS;
1140 }
1141 else if (Feature == PORT_RESET)
1142 {
1143 //
1144 // assert
1145 //
1146 ASSERT((Value & OHCI_RH_PORTSTATUS_CCS));
1147
1148 //
1149 // reset port
1150 //
1151 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)m_Base + OHCI_RH_PORT_STATUS(PortId)), OHCI_RH_PORTSTATUS_PRS);
1152
1153 //
1154 // wait
1155 //
1156 KeStallExecutionProcessor(100);
1157
1158 //
1159 // update cached settings
1160 //
1161 m_PortStatus[PortId].PortChange |= USB_PORT_STATUS_RESET;
1162 m_PortStatus[PortId].PortStatus &= ~USB_PORT_STATUS_ENABLE;
1163
1164 //
1165 // is there a status change callback
1166 //
1167 if (m_SCECallBack != NULL)
1168 {
1169 //
1170 // issue callback
1171 //
1172 m_SCECallBack(m_SCEContext);
1173 }
1174 }
1175 return STATUS_SUCCESS;
1176 }
1177
1178
1179
1180 VOID
1181 CUSBHardwareDevice::SetStatusChangeEndpointCallBack(
1182 PVOID CallBack,
1183 PVOID Context)
1184 {
1185 m_SCECallBack = (HD_INIT_CALLBACK*)CallBack;
1186 m_SCEContext = Context;
1187 }
1188
1189 KIRQL
1190 CUSBHardwareDevice::AcquireDeviceLock(void)
1191 {
1192 KIRQL OldLevel;
1193
1194 //
1195 // acquire lock
1196 //
1197 KeAcquireSpinLock(&m_Lock, &OldLevel);
1198
1199 //
1200 // return old irql
1201 //
1202 return OldLevel;
1203 }
1204
1205 VOID
1206 CUSBHardwareDevice::GetCurrentFrameNumber(
1207 PULONG FrameNumber)
1208 {
1209 //
1210 // store frame number
1211 //
1212 *FrameNumber = m_HCCA->CurrentFrameNumber;
1213 }
1214
1215 VOID
1216 CUSBHardwareDevice::ReleaseDeviceLock(
1217 KIRQL OldLevel)
1218 {
1219 KeReleaseSpinLock(&m_Lock, OldLevel);
1220 }
1221
1222 BOOLEAN
1223 NTAPI
1224 InterruptServiceRoutine(
1225 IN PKINTERRUPT Interrupt,
1226 IN PVOID ServiceContext)
1227 {
1228 CUSBHardwareDevice *This;
1229 ULONG DoneHead, Status, Acknowledge = 0;
1230
1231 //
1232 // get context
1233 //
1234 This = (CUSBHardwareDevice*) ServiceContext;
1235
1236 DPRINT("InterruptServiceRoutine\n");
1237
1238 //
1239 // get done head
1240 //
1241 DoneHead = This->m_HCCA->DoneHead;
1242
1243 //
1244 // check if zero
1245 //
1246 if (DoneHead == 0)
1247 {
1248 //
1249 // the interrupt was not caused by DoneHead update
1250 // check if something important happened
1251 //
1252 Status = READ_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_INTERRUPT_STATUS_OFFSET)) & READ_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_INTERRUPT_ENABLE_OFFSET)) & (~OHCI_WRITEBACK_DONE_HEAD);
1253 if (Status == 0)
1254 {
1255 //
1256 // nothing happened, appears to be shared interrupt
1257 //
1258 return FALSE;
1259 }
1260 }
1261 else
1262 {
1263 //
1264 // DoneHead update happened, check if there are other events too
1265 //
1266 Status = OHCI_WRITEBACK_DONE_HEAD;
1267
1268 //
1269 // since ed descriptors are 16 byte aligned, the controller sets the lower bits if there were other interrupt requests
1270 //
1271 if (DoneHead & OHCI_DONE_INTERRUPTS)
1272 {
1273 //
1274 // get other events
1275 //
1276 Status |= READ_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_INTERRUPT_STATUS_OFFSET)) & READ_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_INTERRUPT_ENABLE_OFFSET));
1277 }
1278 }
1279
1280 //
1281 // sanity check
1282 //
1283 ASSERT(Status != 0);
1284
1285 if (Status & OHCI_WRITEBACK_DONE_HEAD)
1286 {
1287 //
1288 // head completed
1289 //
1290 Acknowledge |= OHCI_WRITEBACK_DONE_HEAD;
1291 This->m_HCCA->DoneHead = 0;
1292 }
1293
1294 if (Status & OHCI_RESUME_DETECTED)
1295 {
1296 //
1297 // resume
1298 //
1299 DPRINT1("InterruptServiceRoutine> Resume\n");
1300 Acknowledge |= OHCI_RESUME_DETECTED;
1301 }
1302
1303
1304 if (Status & OHCI_UNRECOVERABLE_ERROR)
1305 {
1306 DPRINT1("InterruptServiceRoutine> Controller error\n");
1307
1308 //
1309 // halt controller
1310 //
1311 ASSERT(FALSE);
1312 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_CONTROL_OFFSET), OHCI_HC_FUNCTIONAL_STATE_RESET);
1313 }
1314
1315 if (Status & OHCI_ROOT_HUB_STATUS_CHANGE)
1316 {
1317 //
1318 // new device has arrived
1319 //
1320
1321 //
1322 // disable interrupt as it will fire untill the port has been reset
1323 //
1324 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_INTERRUPT_DISABLE_OFFSET), OHCI_ROOT_HUB_STATUS_CHANGE);
1325 Acknowledge |= OHCI_ROOT_HUB_STATUS_CHANGE;
1326 }
1327
1328 //
1329 // is there something to acknowledge
1330 //
1331 if (Acknowledge)
1332 {
1333 //
1334 // ack change
1335 //
1336 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_INTERRUPT_STATUS_OFFSET), Acknowledge);
1337 }
1338
1339 //
1340 // defer processing
1341 //
1342 DPRINT("Status %x Acknowledge %x\n", Status, Acknowledge);
1343 KeInsertQueueDpc(&This->m_IntDpcObject, (PVOID)Status, (PVOID)(DoneHead & ~1));
1344
1345 //
1346 // interrupt handled
1347 //
1348 return TRUE;
1349 }
1350
1351 VOID
1352 NTAPI
1353 OhciDefferedRoutine(
1354 IN PKDPC Dpc,
1355 IN PVOID DeferredContext,
1356 IN PVOID SystemArgument1,
1357 IN PVOID SystemArgument2)
1358 {
1359 CUSBHardwareDevice *This;
1360 ULONG CStatus, Index, PortStatus;
1361 POHCI_ENDPOINT_DESCRIPTOR EndpointDescriptor;
1362 ULONG DoneHead;
1363
1364 //
1365 // get parameters
1366 //
1367 This = (CUSBHardwareDevice*)DeferredContext;
1368 CStatus = (ULONG) SystemArgument1;
1369 DoneHead = (ULONG)SystemArgument2;
1370
1371 DPRINT("OhciDefferedRoutine Status %x\n", CStatus);
1372
1373 if (CStatus & OHCI_WRITEBACK_DONE_HEAD)
1374 {
1375 //
1376 // notify queue of event
1377 //
1378 This->m_UsbQueue->TransferDescriptorCompletionCallback(DoneHead);
1379 }
1380 if (CStatus & OHCI_ROOT_HUB_STATUS_CHANGE)
1381 {
1382 //
1383 // device connected, lets check which port
1384 //
1385 for(Index = 0; Index < This->m_NumberOfPorts; Index++)
1386 {
1387 //
1388 // read port status
1389 //
1390 PortStatus = READ_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_RH_PORT_STATUS(Index)));
1391
1392 //
1393 // check if there is a status change
1394 //
1395 if (PortStatus & OHCI_RH_PORTSTATUS_CSC)
1396 {
1397 //
1398 // did a device connect
1399 //
1400 if (PortStatus & OHCI_RH_PORTSTATUS_CCS)
1401 {
1402 //
1403 // device connected
1404 //
1405 DPRINT1("New device arrival at Port %d LowSpeed %x\n", Index, (PortStatus & OHCI_RH_PORTSTATUS_LSDA));
1406
1407 //
1408 // enable port
1409 //
1410 WRITE_REGISTER_ULONG((PULONG)((PUCHAR)This->m_Base + OHCI_RH_PORT_STATUS(Index)), OHCI_RH_PORTSTATUS_PES);
1411
1412
1413 //
1414 // store change
1415 //
1416 This->m_PortStatus[Index].PortStatus |= USB_PORT_STATUS_CONNECT;
1417 This->m_PortStatus[Index].PortChange |= USB_PORT_STATUS_CONNECT;
1418
1419 if ((PortStatus & OHCI_RH_PORTSTATUS_LSDA))
1420 {
1421 //
1422 // low speed device connected
1423 //
1424 This->m_PortStatus[Index].PortStatus |= USB_PORT_STATUS_LOW_SPEED;
1425 }
1426
1427 //
1428 // is there a status change callback
1429 //
1430 if (This->m_SCECallBack != NULL)
1431 {
1432 //
1433 // queue work item for processing
1434 //
1435 ExQueueWorkItem(&This->m_StatusChangeWorkItem, DelayedWorkQueue);
1436 }
1437 }
1438 else
1439 {
1440 //
1441 // device disconnected
1442 //
1443 DPRINT1("Device disconnected at Port %x\n", Index);
1444 }
1445 }
1446 }
1447 }
1448
1449
1450 }
1451
1452 VOID
1453 NTAPI
1454 StatusChangeWorkItemRoutine(
1455 PVOID Context)
1456 {
1457 //
1458 // cast to hardware object
1459 //
1460 CUSBHardwareDevice * This = (CUSBHardwareDevice*)Context;
1461
1462 //
1463 // is there a callback
1464 //
1465 if (This->m_SCECallBack)
1466 {
1467 //
1468 // issue callback
1469 //
1470 This->m_SCECallBack(This->m_SCEContext);
1471 }
1472
1473 }
1474
1475 NTSTATUS
1476 CreateUSBHardware(
1477 PUSBHARDWAREDEVICE *OutHardware)
1478 {
1479 PUSBHARDWAREDEVICE This;
1480
1481 This = new(NonPagedPool, TAG_USBOHCI) CUSBHardwareDevice(0);
1482
1483 if (!This)
1484 return STATUS_INSUFFICIENT_RESOURCES;
1485
1486 This->AddRef();
1487
1488 // return result
1489 *OutHardware = (PUSBHARDWAREDEVICE)This;
1490
1491 return STATUS_SUCCESS;
1492 }