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[USBPORT] Continue implementation USBPORT_AllocateBandwidthUSB2().
[reactos.git] / drivers / usb / usbohci / hardware.h
1 #pragma once
2
3 //
4 // OHCI Operational Registers
5 //
6
7 #define OHCI_REVISION_OFFSET (0x00)
8 #define OHCI_REVISION_LOW(rev) ((rev) & 0x0f)
9 #define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03)
10
11
12 //
13 // OHCI Control Register
14 //
15 #define OHCI_CONTROL_OFFSET (0x004)
16 #define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK (0x003)
17 #define OHCI_CONTROL_BULK_RATIO_1_1 (0x000)
18 #define OHCI_CONTROL_BULK_RATIO_1_2 (0x001)
19 #define OHCI_CONTROL_BULK_RATIO_1_3 (0x002)
20 #define OHCI_CONTROL_BULK_RATIO_1_4 (0x003)
21 #define OHCI_PERIODIC_LIST_ENABLE (0x004)
22 #define OHCI_ISOCHRONOUS_ENABLE (0x008)
23 #define OHCI_CONTROL_LIST_ENABLE (0x010)
24 #define OHCI_BULK_LIST_ENABLE (0x020)
25 #define OHCI_HC_FUNCTIONAL_STATE_MASK (0x0C0)
26 #define OHCI_HC_FUNCTIONAL_STATE_RESET (0x000)
27 #define OHCI_HC_FUNCTIONAL_STATE_RESUME (0x040)
28 #define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL (0x080)
29 #define OHCI_HC_FUNCTIONAL_STATE_SUSPEND (0x0c0)
30 #define OHCI_INTERRUPT_ROUTING (0x100)
31 #define OHCI_REMOTE_WAKEUP_CONNECTED (0x200)
32 #define OHCI_REMORE_WAKEUP_ENABLED (0x400)
33
34 //
35 // OHCI Command Status Register
36 //
37 #define OHCI_COMMAND_STATUS_OFFSET (0x08)
38 #define OHCI_HOST_CONTROLLER_RESET 0x00000001
39 #define OHCI_CONTROL_LIST_FILLED 0x00000002
40 #define OHCI_BULK_LIST_FILLED 0x00000004
41 #define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008
42 #define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000
43
44
45 //
46 // OHCI Interrupt Status Register
47 //
48 #define OHCI_INTERRUPT_STATUS_OFFSET 0x0c
49 #define OHCI_SCHEDULING_OVERRUN 0x00000001
50 #define OHCI_WRITEBACK_DONE_HEAD 0x00000002
51 #define OHCI_START_OF_FRAME 0x00000004
52 #define OHCI_RESUME_DETECTED 0x00000008
53 #define OHCI_UNRECOVERABLE_ERROR 0x00000010
54 #define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020
55 #define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040
56 #define OHCI_OWNERSHIP_CHANGE 0x40000000
57 #define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000
58
59
60 //
61 // OHCI Interrupt Enable Register
62 //
63 #define OHCI_INTERRUPT_ENABLE_OFFSET 0x10
64
65 //
66 // OHCI Interrupt Enable Register
67 //
68 #define OHCI_INTERRUPT_DISABLE_OFFSET 0x14
69
70 //
71 // OHCI HCCA Register
72 //
73 #define OHCI_HCCA_OFFSET 0x18
74 #define OHCI_PERIOD_CURRENT_ED_OFFSET 0x1c
75 #define OHCI_CONTROL_HEAD_ED_OFFSET 0x20
76 #define OHCI_CONTROL_CURRENT_ED_OFFSET 0x24
77 #define OHCI_BULK_HEAD_ED_OFFSET 0x28
78
79 //
80 // OHCI Root Hub Descriptor A register
81 //
82 #define OHCI_RH_DESCRIPTOR_A_OFFSET 0x48
83 #define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff)
84 #define OHCI_RH_POWER_SWITCHING_MODE 0x0100
85 #define OHCI_RH_NO_POWER_SWITCHING 0x0200
86 #define OHCI_RH_DEVICE_TYPE 0x0400
87 #define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800
88 #define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000
89 #define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24)
90
91 //
92 // Frame interval register (section 7.3.1)
93 //
94 #define OHCI_FRAME_INTERVAL_OFFSET 0x34
95 #define OHCI_GET_INTERVAL_VALUE(s) ((s) & 0x3fff)
96 #define OHCI_GET_FS_LARGEST_DATA_PACKET(s) (((s) >> 16) & 0x7fff)
97 #define OHCI_FRAME_INTERVAL_TOGGLE 0x80000000
98
99 //
100 // frame interval
101 //
102 #define OHCI_FRAME_INTERVAL_NUMBER_OFFSET 0x3C
103
104 //
105 // periodic start register
106 //
107 #define OHCI_PERIODIC_START_OFFSET 0x40
108 #define OHCI_PERIODIC(i) ((i) * 9 / 10)
109
110 //
111 // Root Hub Descriptor B register (section 7.4.2)
112 //
113
114 #define OHCI_RH_DESCRIPTOR_B_OFFSET 0x4c
115
116 //
117 // Root Hub status register (section 7.4.3)
118 //
119 #define OHCI_RH_STATUS_OFFSET 0x50
120 #define OHCI_RH_LOCAL_POWER_STATUS 0x00000001
121 #define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002
122 #define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000
123 #define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000
124 #define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000
125 #define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000
126
127 //
128 // Root Hub port status (n) register (section 7.4.4)
129 //
130 #define OHCI_RH_PORT_STATUS(n) (0x54 + (n) * 4)// 0 based indexing
131 #define OHCI_RH_PORTSTATUS_CCS 0x00000001
132 #define OHCI_RH_PORTSTATUS_PES 0x00000002
133 #define OHCI_RH_PORTSTATUS_PSS 0x00000004
134 #define OHCI_RH_PORTSTATUS_POCI 0x00000008
135 #define OHCI_RH_PORTSTATUS_PRS 0x00000010
136 #define OHCI_RH_PORTSTATUS_PPS 0x00000100
137 #define OHCI_RH_PORTSTATUS_LSDA 0x00000200
138 #define OHCI_RH_PORTSTATUS_CSC 0x00010000
139 #define OHCI_RH_PORTSTATUS_PESC 0x00020000
140 #define OHCI_RH_PORTSTATUS_PSSC 0x00040000
141 #define OHCI_RH_PORTSTATUS_OCIC 0x00080000
142 #define OHCI_RH_PORTSTATUS_PRSC 0x00100000
143
144 //
145 // Enable List
146 //
147
148 #define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \
149 | OHCI_ISOCHRONOUS_ENABLE \
150 | OHCI_CONTROL_LIST_ENABLE \
151 | OHCI_BULK_LIST_ENABLE)
152
153 //
154 // All interrupts
155 //
156 #define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
157 | OHCI_WRITEBACK_DONE_HEAD \
158 | OHCI_START_OF_FRAME \
159 | OHCI_RESUME_DETECTED \
160 | OHCI_UNRECOVERABLE_ERROR \
161 | OHCI_FRAME_NUMBER_OVERFLOW \
162 | OHCI_ROOT_HUB_STATUS_CHANGE \
163 | OHCI_OWNERSHIP_CHANGE)
164
165 //
166 // All normal interrupts
167 //
168 #define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
169 | OHCI_WRITEBACK_DONE_HEAD \
170 | OHCI_RESUME_DETECTED \
171 | OHCI_UNRECOVERABLE_ERROR \
172 | OHCI_ROOT_HUB_STATUS_CHANGE \
173 | OHCI_OWNERSHIP_CHANGE)
174
175 //
176 // FSMPS
177 //
178
179 #define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16)
180
181 //
182 // Periodic
183 //
184
185 #define OHCI_PERIODIC(i) ((i) * 9 / 10)
186
187 // --------------------------------
188 // HCCA structure (section 4.4)
189 // 256 bytes aligned
190 // --------------------------------
191
192 #define OHCI_NUMBER_OF_INTERRUPTS 32
193 #define OHCI_STATIC_ENDPOINT_COUNT 6
194 #define OHCI_BIGGEST_INTERVAL 32
195
196 typedef struct
197 {
198 ULONG InterruptTable[OHCI_NUMBER_OF_INTERRUPTS];
199 ULONG CurrentFrameNumber;
200 ULONG DoneHead;
201 UCHAR Reserved[120];
202 }OHCIHCCA, *POHCIHCCA;
203
204 #define OHCI_DONE_INTERRUPTS 1
205 #define OHCI_HCCA_SIZE 256
206 #define OHCI_HCCA_ALIGN 256
207 #define OHCI_PAGE_SIZE 0x1000
208 #define OHCI_PAGE(x) ((x) &~ 0xfff)
209 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
210
211
212 typedef struct _OHCI_ENDPOINT_DESCRIPTOR
213 {
214 // Hardware part
215 ULONG Flags;
216 ULONG TailPhysicalDescriptor;
217 ULONG HeadPhysicalDescriptor;
218 ULONG NextPhysicalEndpoint;
219
220 // Software part
221 PHYSICAL_ADDRESS PhysicalAddress;
222 PVOID HeadLogicalDescriptor;
223 PVOID NextDescriptor;
224 PVOID Request;
225 LIST_ENTRY DescriptorListEntry;
226 }OHCI_ENDPOINT_DESCRIPTOR, *POHCI_ENDPOINT_DESCRIPTOR;
227
228
229 #define OHCI_ENDPOINT_SKIP 0x00004000
230 #define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s)
231 #define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0xFF)
232 #define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf)
233 #define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7)
234 #define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff)
235 #define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16)
236 #define OHCI_ENDPOINT_LOW_SPEED 0x00002000
237 #define OHCI_ENDPOINT_FULL_SPEED 0x00000000
238 #define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800
239 #define OHCI_ENDPOINT_DIRECTION_IN 0x00001000
240 #define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000
241 #define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000
242 #define OHCI_ENDPOINT_HEAD_MASK 0xfffffffc
243 #define OHCI_ENDPOINT_HALTED 0x00000001
244 #define OHCI_ENDPOINT_TOGGLE_CARRY 0x00000002
245 #define OHCI_ENDPOINT_DIRECTION_DESCRIPTOR 0x00000000
246
247 //
248 // Maximum port count set by OHCI
249 //
250 #define OHCI_MAX_PORT_COUNT 15
251
252
253 typedef struct
254 {
255 ULONG PortStatus;
256 ULONG PortChange;
257 }OHCI_PORT_STATUS;
258
259
260 typedef struct
261 {
262 // Hardware part 16 bytes
263 ULONG Flags; // Flags field
264 ULONG BufferPhysical; // Physical buffer pointer
265 ULONG NextPhysicalDescriptor; // Physical pointer next descriptor
266 ULONG LastPhysicalByteAddress; // Physical pointer to buffer end
267 // Software part
268 PHYSICAL_ADDRESS PhysicalAddress; // Physical address of this descriptor
269 PVOID NextLogicalDescriptor;
270 ULONG BufferSize; // Size of the buffer
271 PVOID BufferLogical; // Logical pointer to the buffer
272 }OHCI_GENERAL_TD, *POHCI_GENERAL_TD;
273
274
275 #define OHCI_TD_BUFFER_ROUNDING 0x00040000
276 #define OHCI_TD_DIRECTION_PID_MASK 0x00180000
277 #define OHCI_TD_DIRECTION_PID_SETUP 0x00000000
278 #define OHCI_TD_DIRECTION_PID_OUT 0x00080000
279 #define OHCI_TD_DIRECTION_PID_IN 0x00100000
280 #define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
281 #define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21)
282 #define OHCI_TD_INTERRUPT_MASK 0x00e00000
283 #define OHCI_TD_TOGGLE_CARRY 0x00000000
284 #define OHCI_TD_TOGGLE_0 0x02000000
285 #define OHCI_TD_TOGGLE_1 0x03000000
286 #define OHCI_TD_TOGGLE_MASK 0x03000000
287 #define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3)
288 #define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28)
289 #define OHCI_TD_SET_CONDITION_CODE(x) ((x) << 28)
290 #define OHCI_TD_CONDITION_CODE_MASK 0xf0000000
291
292 #define OHCI_TD_INTERRUPT_IMMEDIATE 0x00
293 #define OHCI_TD_INTERRUPT_NONE 0x07
294
295 #define OHCI_TD_CONDITION_NO_ERROR 0x00
296 #define OHCI_TD_CONDITION_CRC_ERROR 0x01
297 #define OHCI_TD_CONDITION_BIT_STUFFING 0x02
298 #define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03
299 #define OHCI_TD_CONDITION_STALL 0x04
300 #define OHCI_TD_CONDITION_NO_RESPONSE 0x05
301 #define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
302 #define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07
303 #define OHCI_TD_CONDITION_DATA_OVERRUN 0x08
304 #define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09
305 #define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0c
306 #define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0d
307 #define OHCI_TD_CONDITION_NOT_ACCESSED 0x0f
308
309 // --------------------------------
310 // Isochronous transfer descriptor structure (section 4.3.2)
311 // --------------------------------
312
313 #define OHCI_ITD_NOFFSET 8
314
315 typedef struct _OHCI_ISO_TD_
316 {
317
318 // Hardware part 32 byte
319 ULONG Flags;
320 ULONG BufferPhysical; // Physical page number of byte 0
321 ULONG NextPhysicalDescriptor; // Next isochronous transfer descriptor
322 ULONG LastPhysicalByteAddress; // Physical buffer end
323 USHORT Offset[OHCI_ITD_NOFFSET]; // Buffer offsets
324
325 // Software part
326 PHYSICAL_ADDRESS PhysicalAddress; // Physical address of this descriptor
327 struct _OHCI_ISO_TD_ * NextLogicalDescriptor; // Logical pointer next descriptor
328 }OHCI_ISO_TD, *POHCI_ISO_TD;
329
330 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, Flags) == 0);
331 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, BufferPhysical) == 4);
332 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, NextPhysicalDescriptor) == 8);
333 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, LastPhysicalByteAddress) == 12);
334 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, Offset) == 16);
335 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, PhysicalAddress) == 32);
336 C_ASSERT(FIELD_OFFSET(OHCI_ISO_TD, NextLogicalDescriptor) == 40);
337 C_ASSERT(sizeof(OHCI_ISO_TD) == 48);
338
339 #define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff)
340 #define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff)
341 #define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
342 #define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21)
343 #define OHCI_ITD_NO_INTERRUPT 0x00e00000
344 #define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1)
345 #define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24)
346 #define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28)
347 #define OHCI_ITD_NO_CONDITION_CODE 0xf0000000
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