[USBOHCI]
[reactos.git] / drivers / usb / usbohci / hardware.h
1 #pragma once
2
3 #include <ntddk.h>
4
5 //
6 // OHCI Operational Registers
7 //
8
9 #define OHCI_REVISION_OFFSET (0x00)
10 #define OHCI_REVISION_LOW(rev) ((rev) & 0x0f)
11 #define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03)
12
13
14 //
15 // OHCI Control Register
16 //
17 #define OHCI_CONTROL_OFFSET (0x004)
18 #define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK (0x003)
19 #define OHCI_CONTROL_BULK_RATIO_1_1 (0x000)
20 #define OHCI_CONTROL_BULK_RATIO_1_2 (0x001)
21 #define OHCI_CONTROL_BULK_RATIO_1_3 (0x002)
22 #define OHCI_CONTROL_BULK_RATIO_1_4 (0x003)
23 #define OHCI_PERIODIC_LIST_ENABLE (0x004)
24 #define OHCI_ISOCHRONOUS_ENABLE (0x008)
25 #define OHCI_CONTROL_LIST_ENABLE (0x010)
26 #define OHCI_BULK_LIST_ENABLE (0x020)
27 #define OHCI_HC_FUNCTIONAL_STATE_MASK (0x0C0)
28 #define OHCI_HC_FUNCTIONAL_STATE_RESET (0x000)
29 #define OHCI_HC_FUNCTIONAL_STATE_RESUME (0x040)
30 #define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL (0x080)
31 #define OHCI_HC_FUNCTIONAL_STATE_SUSPEND (0x0c0)
32 #define OHCI_INTERRUPT_ROUTING (0x100)
33 #define OHCI_REMOTE_WAKEUP_CONNECTED (0x200)
34 #define OHCI_REMORE_WAKEUP_ENABLED (0x400)
35
36 //
37 // OHCI Command Status Register
38 //
39 #define OHCI_COMMAND_STATUS_OFFSET (0x08)
40 #define OHCI_HOST_CONTROLLER_RESET 0x00000001
41 #define OHCI_CONTROL_LIST_FILLED 0x00000002
42 #define OHCI_BULK_LIST_FILLED 0x00000004
43 #define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008
44 #define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000
45
46
47 //
48 // OHCI Interrupt Status Register
49 //
50 #define OHCI_INTERRUPT_STATUS_OFFSET 0x0c
51 #define OHCI_SCHEDULING_OVERRUN 0x00000001
52 #define OHCI_WRITEBACK_DONE_HEAD 0x00000002
53 #define OHCI_START_OF_FRAME 0x00000004
54 #define OHCI_RESUME_DETECTED 0x00000008
55 #define OHCI_UNRECOVERABLE_ERROR 0x00000010
56 #define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020
57 #define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040
58 #define OHCI_OWNERSHIP_CHANGE 0x40000000
59 #define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000
60
61
62 //
63 // OHCI Interrupt Enable Register
64 //
65 #define OHCI_INTERRUPT_ENABLE_OFFSET 0x10
66
67 //
68 // OHCI Interrupt Enable Register
69 //
70 #define OHCI_INTERRUPT_DISABLE_OFFSET 0x14
71
72 //
73 // OHCI HCCA Register
74 //
75 #define OHCI_HCCA_OFFSET 0x18
76 #define OHCI_PERIOD_CURRENT_ED_OFFSET 0x1c
77 #define OHCI_CONTROL_HEAD_ED_OFFSET 0x20
78 #define OHCI_CONTROL_CURRENT_ED_OFFSET 0x24
79 #define OHCI_BULK_HEAD_ED_OFFSET 0x28
80
81 //
82 // OHCI Root Hub Descriptor A register
83 //
84 #define OHCI_RH_DESCRIPTOR_A_OFFSET 0x48
85 #define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff)
86 #define OHCI_RH_POWER_SWITCHING_MODE 0x0100
87 #define OHCI_RH_NO_POWER_SWITCHING 0x0200
88 #define OHCI_RH_DEVICE_TYPE 0x0400
89 #define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800
90 #define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000
91 #define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24)
92
93 //
94 // Frame interval register (section 7.3.1)
95 //
96 #define OHCI_FRAME_INTERVAL_OFFSET 0x34
97 #define OHCI_GET_INTERVAL_VALUE(s) ((s) & 0x3fff)
98 #define OHCI_GET_FS_LARGEST_DATA_PACKET(s) (((s) >> 16) & 0x7fff)
99 #define OHCI_FRAME_INTERVAL_TOGGLE 0x80000000
100
101 //
102 // periodic start register
103 //
104 #define OHCI_PERIODIC_START_OFFSET 0x40
105 #define OHCI_PERIODIC(i) ((i) * 9 / 10)
106
107 //
108 // Root Hub Descriptor B register (section 7.4.2)
109 //
110
111 #define OHCI_RH_DESCRIPTOR_B 0x4c
112
113 //
114 // Root Hub status register (section 7.4.3)
115 //
116 #define OHCI_RH_STATUS_OFFSET 0x50
117 #define OHCI_RH_LOCAL_POWER_STATUS 0x00000001
118 #define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002
119 #define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000
120 #define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000
121 #define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000
122 #define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000
123
124 //
125 // Root Hub port status (n) register (section 7.4.4)
126 //
127 #define OHCI_RH_PORT_STATUS(n) (0x54 + (n) * 4)// 0 based indexing
128 #define OHCI_RH_PORTSTATUS_CCS 0x00000001
129 #define OHCI_RH_PORTSTATUS_PES 0x00000002
130 #define OHCI_RH_PORTSTATUS_PSS 0x00000004
131 #define OHCI_RH_PORTSTATUS_POCI 0x00000008
132 #define OHCI_RH_PORTSTATUS_PRS 0x00000010
133 #define OHCI_RH_PORTSTATUS_PPS 0x00000100
134 #define OHCI_RH_PORTSTATUS_LSDA 0x00000200
135 #define OHCI_RH_PORTSTATUS_CSC 0x00010000
136 #define OHCI_RH_PORTSTATUS_PESC 0x00020000
137 #define OHCI_RH_PORTSTATUS_PSSC 0x00040000
138 #define OHCI_RH_PORTSTATUS_OCIC 0x00080000
139 #define OHCI_RH_PORTSTATUS_PRSC 0x00100000
140
141 //
142 // Enable List
143 //
144
145 #define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \
146 | OHCI_ISOCHRONOUS_ENABLE \
147 | OHCI_CONTROL_LIST_ENABLE \
148 | OHCI_BULK_LIST_ENABLE)
149
150 //
151 // All interupts
152 //
153 #define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
154 | OHCI_WRITEBACK_DONE_HEAD \
155 | OHCI_START_OF_FRAME \
156 | OHCI_RESUME_DETECTED \
157 | OHCI_UNRECOVERABLE_ERROR \
158 | OHCI_FRAME_NUMBER_OVERFLOW \
159 | OHCI_ROOT_HUB_STATUS_CHANGE \
160 | OHCI_OWNERSHIP_CHANGE)
161
162 //
163 // All normal interupts
164 //
165 #define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
166 | OHCI_WRITEBACK_DONE_HEAD \
167 | OHCI_RESUME_DETECTED \
168 | OHCI_UNRECOVERABLE_ERROR \
169 | OHCI_ROOT_HUB_STATUS_CHANGE)
170
171 //
172 // FSMPS
173 //
174
175 #define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16)
176
177 //
178 // Periodic
179 //
180
181 #define OHCI_PERIODIC(i) ((i) * 9 / 10)
182
183 // --------------------------------
184 // HCCA structure (section 4.4)
185 // 256 bytes aligned
186 // --------------------------------
187
188 #define OHCI_NUMBER_OF_INTERRUPTS 32
189 #define OHCI_STATIC_ENDPOINT_COUNT 6
190 #define OHCI_BIGGEST_INTERVAL 32
191
192 typedef struct
193 {
194 ULONG InterruptTable[OHCI_NUMBER_OF_INTERRUPTS];
195 ULONG CurrentFrameNumber;
196 ULONG DoneHead;
197 UCHAR Reserved[120];
198 }OHCIHCCA, *POHCIHCCA;
199
200 #define OHCI_DONE_INTERRUPTS 1
201 #define OHCI_HCCA_SIZE 256
202 #define OHCI_HCCA_ALIGN 256
203 #define OHCI_PAGE_SIZE 0x1000
204 #define OHCI_PAGE(x) ((x) &~ 0xfff)
205 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
206
207
208 typedef struct _OHCI_ENDPOINT_DESCRIPTOR
209 {
210 // Hardware part
211 ULONG Flags;
212 ULONG TailPhysicalDescriptor;
213 ULONG HeadPhysicalDescriptor;
214 ULONG NextPhysicalEndpoint;
215
216 // Software part
217 PHYSICAL_ADDRESS PhysicalAddress;
218 PVOID HeadLogicalDescriptor;
219 PVOID NextDescriptor;
220 PVOID Request;
221 }OHCI_ENDPOINT_DESCRIPTOR, *POHCI_ENDPOINT_DESCRIPTOR;
222
223
224 #define OHCI_ENDPOINT_SKIP 0x00004000
225 #define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s)
226 #define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf)
227 #define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7)
228 #define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff)
229 #define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16)
230 #define OHCI_ENDPOINT_LOW_SPEED 0x00002000
231 #define OHCI_ENDPOINT_FULL_SPEED 0x00000000
232 #define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800
233 #define OHCI_ENDPOINT_DIRECTION_IN 0x00001000
234 #define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000
235 #define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000
236
237 //
238 // Maximum port count set by OHCI
239 //
240 #define OHCI_MAX_PORT_COUNT 15
241
242
243 typedef struct
244 {
245 ULONG PortStatus;
246 ULONG PortChange;
247 }OHCI_PORT_STATUS;
248
249
250 typedef struct
251 {
252 // Hardware part 16 bytes
253 ULONG Flags; // Flags field
254 ULONG BufferPhysical; // Physical buffer pointer
255 ULONG NextPhysicalDescriptor; // Physical pointer next descriptor
256 ULONG LastPhysicalByteAddress; // Physical pointer to buffer end
257 // Software part
258 PHYSICAL_ADDRESS PhysicalAddress; // Physical address of this descriptor
259 PVOID NextLogicalDescriptor;
260 ULONG BufferSize; // Size of the buffer
261 PVOID BufferLogical; // Logical pointer to the buffer
262 }OHCI_GENERAL_TD, *POHCI_GENERAL_TD;
263
264
265 #define OHCI_TD_BUFFER_ROUNDING 0x00040000
266 #define OHCI_TD_DIRECTION_PID_MASK 0x00180000
267 #define OHCI_TD_DIRECTION_PID_SETUP 0x00000000
268 #define OHCI_TD_DIRECTION_PID_OUT 0x00080000
269 #define OHCI_TD_DIRECTION_PID_IN 0x00100000
270 #define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
271 #define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21)
272 #define OHCI_TD_INTERRUPT_MASK 0x00e00000
273 #define OHCI_TD_TOGGLE_CARRY 0x00000000
274 #define OHCI_TD_TOGGLE_0 0x02000000
275 #define OHCI_TD_TOGGLE_1 0x03000000
276 #define OHCI_TD_TOGGLE_MASK 0x03000000
277 #define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3)
278 #define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28)
279 #define OHCI_TD_SET_CONDITION_CODE(x) ((x) << 28)
280 #define OHCI_TD_CONDITION_CODE_MASK 0xf0000000
281
282 #define OHCI_TD_INTERRUPT_IMMEDIATE 0x00
283 #define OHCI_TD_INTERRUPT_NONE 0x07
284
285 #define OHCI_TD_CONDITION_NO_ERROR 0x00
286 #define OHCI_TD_CONDITION_CRC_ERROR 0x01
287 #define OHCI_TD_CONDITION_BIT_STUFFING 0x02
288 #define OHCI_TD_CONDITION_TOGGLE_MISMATCH 0x03
289 #define OHCI_TD_CONDITION_STALL 0x04
290 #define OHCI_TD_CONDITION_NO_RESPONSE 0x05
291 #define OHCI_TD_CONDITION_PID_CHECK_FAILURE 0x06
292 #define OHCI_TD_CONDITION_UNEXPECTED_PID 0x07
293 #define OHCI_TD_CONDITION_DATA_OVERRUN 0x08
294 #define OHCI_TD_CONDITION_DATA_UNDERRUN 0x09
295 #define OHCI_TD_CONDITION_BUFFER_OVERRUN 0x0c
296 #define OHCI_TD_CONDITION_BUFFER_UNDERRUN 0x0d
297 #define OHCI_TD_CONDITION_NOT_ACCESSED 0x0f
298
299 // --------------------------------
300 // Isochronous transfer descriptor structure (section 4.3.2)
301 // --------------------------------
302
303 #define OHCI_ITD_NOFFSET 8
304
305 typedef struct _OHCI_ISO_TD_
306 {
307
308 // Hardware part 32 byte
309 ULONG Flags;
310 ULONG BufferPhysical; // Physical page number of byte 0
311 ULONG NextPhysicalDescriptor; // Next isochronous transfer descriptor
312 ULONG LastPhysicalByteAddress; // Physical buffer end
313 ULONG Offset[OHCI_ITD_NOFFSET]; // Buffer offsets
314
315 // Software part
316 PHYSICAL_ADDRESS PhysicalAddress; // Physical address of this descriptor
317 struct _OHCI_ISO_TD_ * NextLogicalDescriptor; // Logical pointer next descriptor
318 }OHCI_ISO_TD, *POHCI_ISO_TD;
319
320 #define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff)
321 #define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff)
322 #define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7)
323 #define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21)
324 #define OHCI_ITD_NO_INTERRUPT 0x00e00000
325 #define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1)
326 #define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24)
327 #define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28)
328 #define OHCI_ITD_NO_CONDITION_CODE 0xf0000000
329