6 // OHCI Operational Registers
9 #define OHCI_REVISION_OFFSET (0x00)
10 #define OHCI_REVISION_LOW(rev) ((rev) & 0x0f)
11 #define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03)
15 // OHCI Control Register
17 #define OHCI_CONTROL_OFFSET (0x004)
18 #define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK (0x003)
19 #define OHCI_CONTROL_BULK_RATIO_1_1 (0x000)
20 #define OHCI_CONTROL_BULK_RATIO_1_2 (0x001)
21 #define OHCI_CONTROL_BULK_RATIO_1_3 (0x002)
22 #define OHCI_CONTROL_BULK_RATIO_1_4 (0x003)
23 #define OHCI_PERIODIC_LIST_ENABLE (0x004)
24 #define OHCI_ISOCHRONOUS_ENABLE (0x008)
25 #define OHCI_CONTROL_LIST_ENABLE (0x010)
26 #define OHCI_BULK_LIST_ENABLE (0x020)
27 #define OHCI_HC_FUNCTIONAL_STATE_MASK (0x0C0)
28 #define OHCI_HC_FUNCTIONAL_STATE_RESET (0x000)
29 #define OHCI_HC_FUNCTIONAL_STATE_RESUME (0x040)
30 #define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL (0x080)
31 #define OHCI_HC_FUNCTIONAL_STATE_SUSPEND (0x0c0)
32 #define OHCI_INTERRUPT_ROUTING (0x100)
33 #define OHCI_REMOTE_WAKEUP_CONNECTED (0x200)
34 #define OHCI_REMORE_WAKEUP_ENABLED (0x400)
37 // OHCI Command Status Register
39 #define OHCI_COMMAND_STATUS_OFFSET (0x08)
40 #define OHCI_HOST_CONTROLLER_RESET 0x00000001
41 #define OHCI_CONTROL_LIST_FILLED 0x00000002
42 #define OHCI_BULK_LIST_FILLED 0x00000004
43 #define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008
44 #define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000
48 // OHCI Interrupt Status Register
50 #define OHCI_INTERRUPT_STATUS_OFFSET 0x0c
51 #define OHCI_SCHEDULING_OVERRUN 0x00000001
52 #define OHCI_WRITEBACK_DONE_HEAD 0x00000002
53 #define OHCI_START_OF_FRAME 0x00000004
54 #define OHCI_RESUME_DETECTED 0x00000008
55 #define OHCI_UNRECOVERABLE_ERROR 0x00000010
56 #define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020
57 #define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040
58 #define OHCI_OWNERSHIP_CHANGE 0x40000000
59 #define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000
63 // OHCI Interrupt Enable Register
65 #define OHCI_INTERRUPT_ENABLE_OFFSET 0x10
68 // OHCI Interrupt Enable Register
70 #define OHCI_INTERRUPT_DISABLE_OFFSET 0x14
75 #define OHCI_HCCA_OFFSET 0x18
76 #define OHCI_PERIOD_CURRENT_ED_OFFSET 0x1c
77 #define OHCI_CONTROL_HEAD_ED_OFFSET 0x20
78 #define OHCI_CONTROL_CURRENT_ED_OFFSET 0x24
79 #define OHCI_BULK_HEAD_ED_OFFSET 0x28
82 // OHCI Root Hub Descriptor A register
84 #define OHCI_RH_DESCRIPTOR_A_OFFSET 0x48
85 #define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff)
86 #define OHCI_RH_POWER_SWITCHING_MODE 0x0100
87 #define OHCI_RH_NO_POWER_SWITCHING 0x0200
88 #define OHCI_RH_DEVICE_TYPE 0x0400
89 #define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800
90 #define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000
91 #define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24)
95 // Root Hub Descriptor B register (section 7.4.2)
98 #define OHCI_RH_DESCRIPTOR_B 0x4c
101 // Root Hub status register (section 7.4.3)
103 #define OHCI_RH_STATUS 0x50
104 #define OHCI_RH_LOCAL_POWER_STATUS 0x00000001
105 #define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002
106 #define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000
107 #define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000
108 #define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000
109 #define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000
112 // Root Hub port status (n) register (section 7.4.4)
114 #define OHCI_RH_PORT_STATUS(n) (0x54 + (n) * 4)// 0 based indexing
115 #define OHCI_RH_PORTSTATUS_CCS 0x00000001
116 #define OHCI_RH_PORTSTATUS_PES 0x00000002
117 #define OHCI_RH_PORTSTATUS_PSS 0x00000004
118 #define OHCI_RH_PORTSTATUS_POCI 0x00000008
119 #define OHCI_RH_PORTSTATUS_PRS 0x00000010
120 #define OHCI_RH_PORTSTATUS_PPS 0x00000100
121 #define OHCI_RH_PORTSTATUS_LSDA 0x00000200
122 #define OHCI_RH_PORTSTATUS_CSC 0x00010000
123 #define OHCI_RH_PORTSTATUS_PESC 0x00020000
124 #define OHCI_RH_PORTSTATUS_PSSC 0x00040000
125 #define OHCI_RH_PORTSTATUS_OCIC 0x00080000
126 #define OHCI_RH_PORTSTATUS_PRSC 0x00100000
132 #define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \
133 | OHCI_ISOCHRONOUS_ENABLE \
134 | OHCI_CONTROL_LIST_ENABLE \
135 | OHCI_BULK_LIST_ENABLE)
140 #define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
141 | OHCI_WRITEBACK_DONE_HEAD \
142 | OHCI_START_OF_FRAME \
143 | OHCI_RESUME_DETECTED \
144 | OHCI_UNRECOVERABLE_ERROR \
145 | OHCI_FRAME_NUMBER_OVERFLOW \
146 | OHCI_ROOT_HUB_STATUS_CHANGE \
147 | OHCI_OWNERSHIP_CHANGE)
150 // All normal interupts
152 #define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \
153 | OHCI_WRITEBACK_DONE_HEAD \
154 | OHCI_RESUME_DETECTED \
155 | OHCI_UNRECOVERABLE_ERROR \
156 | OHCI_ROOT_HUB_STATUS_CHANGE)
162 #define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16)
168 #define OHCI_PERIODIC(i) ((i) * 9 / 10)
170 // --------------------------------
171 // HCCA structure (section 4.4)
173 // --------------------------------
175 #define OHCI_NUMBER_OF_INTERRUPTS 32
176 #define OHCI_STATIC_ENDPOINT_COUNT 6
177 #define OHCI_BIGGEST_INTERVAL 32
181 ULONG InterruptTable
[OHCI_NUMBER_OF_INTERRUPTS
];
182 ULONG CurrentFrameNumber
;
185 }OHCIHCCA
, *POHCIHCCA
;
187 #define OHCI_DONE_INTERRUPTS 1
188 #define OHCI_HCCA_SIZE 256
189 #define OHCI_HCCA_ALIGN 256
190 #define OHCI_PAGE_SIZE 0x1000
191 #define OHCI_PAGE(x) ((x) &~ 0xfff)
192 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff)
199 ULONG TailPhysicalDescriptor
;
200 ULONG HeadPhysicalDescriptor
;
201 ULONG NextPhysicalEndpoint
;
204 PHYSICAL_ADDRESS PhysicalAddress
;
205 }OHCI_ENDPOINT_DESCRIPTOR
, *POHCI_ENDPOINT_DESCRIPTOR
;
208 #define OHCI_ENDPOINT_SKIP 0x00004000
211 // Maximum port count set by OHCI
213 #define OHCI_MAX_PORT_COUNT 15
224 // Hardware part 16 bytes
225 uint32 flags
; // Flags field
226 uint32 buffer_physical
; // Physical buffer pointer
227 uint32 next_physical_descriptor
; // Physical pointer next descriptor
228 uint32 last_physical_byte_address
; // Physical pointer to buffer end
230 addr_t physical_address
; // Physical address of this descriptor
231 size_t buffer_size
; // Size of the buffer
232 void *buffer_logical
; // Logical pointer to the buffer
233 void *next_logical_descriptor
; // Logical pointer next descriptor