drivers/wdm/audio/hdaudbus/hda_controller_defs.h

   1 /*
   2  * Copyright 2007-2012, Haiku, Inc. All Rights Reserved.
   3  * Distributed under the terms of the MIT License.
   4  *
   5  * Authors:
   6  *              Ithamar Adema, ithamar AT unet DOT nl
   7  *              Axel Dörfler, axeld@pinc-software.de
   8  */
   9 #ifndef HDAC_REGS_H
  10 #define HDAC_REGS_H
  11
  12 #ifndef __REACTOS__
  13 #include <SupportDefs.h>
  14 #endif
  15
  16 /* Controller register definitions */
  17 #define HDAC_GLOBAL_CAP                                 0x00    // 16bits, GCAP
  18 #define GLOBAL_CAP_OUTPUT_STREAMS(cap)  (((cap) >> 12) & 15)
  19 #define GLOBAL_CAP_INPUT_STREAMS(cap)   (((cap) >> 8) & 15)
  20 #define GLOBAL_CAP_BIDIR_STREAMS(cap)   (((cap) >> 3) & 15)
  21 #define GLOBAL_CAP_NUM_SDO(cap)                 ((((cap) >> 1) & 3) ? (cap & 6) : 1)
  22 #define GLOBAL_CAP_64BIT(cap)                   (((cap) & 1) != 0)
  23
  24 #define HDAC_VERSION_MINOR                              0x02    // 8bits, VMIN
  25 #define HDAC_VERSION_MAJOR                              0x03    // 8bits, VMAJ
  26
  27 #define HDAC_GLOBAL_CONTROL                             0x08    // 32bits, GCTL
  28 #define GLOBAL_CONTROL_UNSOLICITED              (1 << 8)
  29         // accept unsolicited responses
  30 #define GLOBAL_CONTROL_FLUSH                    (1 << 1)
  31 #define GLOBAL_CONTROL_RESET                    (1 << 0)
  32
  33 #define HDAC_WAKE_ENABLE                                0x0c    // 16bits, WAKEEN
  34 #define HDAC_WAKE_ENABLE_MASK                   0x7fff
  35 #define HDAC_STATE_STATUS                               0x0e    // 16bits, STATESTS
  36
  37 #define HDAC_INTR_CONTROL                               0x20    // 32bits, INTCTL
  38 #define INTR_CONTROL_GLOBAL_ENABLE              (1U << 31)
  39 #define INTR_CONTROL_CONTROLLER_ENABLE  (1 << 30)
  40
  41 #define HDAC_INTR_STATUS                                0x24    // 32bits, INTSTS
  42 #define INTR_STATUS_GLOBAL                              (1U << 31)
  43 #define INTR_STATUS_CONTROLLER                  (1 << 30)
  44 #define INTR_STATUS_STREAM_MASK                 0x3fffffff
  45
  46 #define HDAC_CORB_BASE_LOWER                    0x40    // 32bits, CORBLBASE
  47 #define HDAC_CORB_BASE_UPPER                    0x44    // 32bits, CORBUBASE
  48 #define HDAC_CORB_WRITE_POS                             0x48    // 16bits, CORBWP
  49 #define HDAC_CORB_WRITE_POS_MASK                0xff
  50
  51 #define HDAC_CORB_READ_POS                              0x4a    // 16bits, CORBRP
  52 #define CORB_READ_POS_RESET                             (1 << 15)
  53
  54 #define HDAC_CORB_CONTROL                               0x4c    // 8bits, CORBCTL
  55 #define HDAC_CORB_CONTROL_MASK                  0x3
  56 #define CORB_CONTROL_RUN                                (1 << 1)
  57 #define CORB_CONTROL_MEMORY_ERROR_INTR  (1 << 0)
  58
  59 #define HDAC_CORB_STATUS                                0x4d    // 8bits, CORBSTS
  60 #define CORB_STATUS_MEMORY_ERROR                (1 << 0)
  61
  62 #define HDAC_CORB_SIZE                                  0x4e    // 8bits, CORBSIZE
  63 #define HDAC_CORB_SIZE_MASK                             0x3
  64 #define CORB_SIZE_CAP_2_ENTRIES                 (1 << 4)
  65 #define CORB_SIZE_CAP_16_ENTRIES                (1 << 5)
  66 #define CORB_SIZE_CAP_256_ENTRIES               (1 << 6)
  67 #define CORB_SIZE_2_ENTRIES                             0x00    // 8 byte
  68 #define CORB_SIZE_16_ENTRIES                    0x01    // 64 byte
  69 #define CORB_SIZE_256_ENTRIES                   0x02    // 1024 byte
  70
  71 #define HDAC_RIRB_BASE_LOWER                    0x50    // 32bits, RIRBLBASE
  72 #define HDAC_RIRB_BASE_UPPER                    0x54    // 32bits, RIRBUBASE
  73
  74 #define HDAC_RIRB_WRITE_POS                             0x58    // 16bits, RIRBWP
  75 #define RIRB_WRITE_POS_RESET                    (1 << 15)
  76
  77 #define HDAC_RESPONSE_INTR_COUNT                0x5a    // 16bits, RINTCNT
  78 #define HDAC_RESPONSE_INTR_COUNT_MASK   0xff
  79
  80 #define HDAC_RIRB_CONTROL                               0x5c    // 8bits, RIRBCTL
  81 #define HDAC_RIRB_CONTROL_MASK                  0x7
  82 #define RIRB_CONTROL_OVERRUN_INTR               (1 << 2)
  83 #define RIRB_CONTROL_DMA_ENABLE                 (1 << 1)
  84 #define RIRB_CONTROL_RESPONSE_INTR              (1 << 0)
  85
  86 #define HDAC_RIRB_STATUS                                0x5d    // 8bits, RIRBSTS
  87 #define RIRB_STATUS_OVERRUN                             (1 << 2)
  88 #define RIRB_STATUS_RESPONSE                    (1 << 0)
  89
  90 #define HDAC_RIRB_SIZE                                  0x5e    // 8bits, RIRBSIZE
  91 #define HDAC_RIRB_SIZE_MASK                             0x3
  92 #define RIRB_SIZE_CAP_2_ENTRIES                 (1 << 4)
  93 #define RIRB_SIZE_CAP_16_ENTRIES                (1 << 5)
  94 #define RIRB_SIZE_CAP_256_ENTRIES               (1 << 6)
  95 #define RIRB_SIZE_2_ENTRIES                             0x00
  96 #define RIRB_SIZE_16_ENTRIES                    0x01
  97 #define RIRB_SIZE_256_ENTRIES                   0x02
  98
  99 #define HDAC_DMA_POSITION_BASE_LOWER    0x70    // 32bits, DPLBASE
 100 #define HDAC_DMA_POSITION_BASE_UPPER    0x74    // 32bits, DPUBASE
 101 #define DMA_POSITION_ENABLED                    1
 102
 103 /* Stream Descriptor Registers */
 104 #define HDAC_STREAM_BASE                                0x80
 105 #define HDAC_STREAM_SIZE                                0x20
 106
 107 #define HDAC_STREAM_CONTROL0                    0x00    // 8bits, CTL0
 108 #define CONTROL0_RESET                                  (1 << 0)
 109 #define CONTROL0_RUN                                    (1 << 1)
 110 #define CONTROL0_BUFFER_COMPLETED_INTR  (1 << 2)
 111 #define CONTROL0_FIFO_ERROR_INTR                (1 << 3)
 112 #define CONTROL0_DESCRIPTOR_ERROR_INTR  (1 << 4)
 113 #define HDAC_STREAM_CONTROL1                    0x01    // 8bits, CTL1
 114 #define HDAC_STREAM_CONTROL2                    0x02    // 8bits, CTL2
 115 #define CONTROL2_STREAM_MASK                    0xf0
 116 #define CONTROL2_STREAM_SHIFT                   4
 117 #define CONTROL2_BIDIR                                  (1 << 3)
 118 #define CONTROL2_TRAFFIC_PRIORITY               (1 << 2)
 119 #define CONTROL2_STRIPE_SDO_MASK                0x03
 120 #define HDAC_STREAM_STATUS                              0x03    // 8bits, STS
 121 #define STATUS_BUFFER_COMPLETED                 (1 << 2)
 122 #define STATUS_FIFO_ERROR                               (1 << 3)
 123 #define STATUS_DESCRIPTOR_ERROR                 (1 << 4)
 124 #define STATUS_FIFO_READY                               (1 << 5)
 125 #define HDAC_STREAM_POSITION                    0x04    // 32bits, LPIB
 126 #define HDAC_STREAM_BUFFER_SIZE                 0x08    // 32bits, CBL
 127 #define HDAC_STREAM_LAST_VALID                  0x0c    // 16bits, LVI
 128 #define HDAC_STREAM_FIFO_SIZE                   0x10    // 16bits, FIFOS
 129 #define HDAC_STREAM_FORMAT                              0x12    // 16bits, FMT
 130 #define FORMAT_8BIT                                             (0 << 4)
 131 #define FORMAT_16BIT                                    (1 << 4)
 132 #define FORMAT_20BIT                                    (2 << 4)
 133 #define FORMAT_24BIT                                    (3 << 4)
 134 #define FORMAT_32BIT                                    (4 << 4)
 135 #define FORMAT_44_1_BASE_RATE                   (1 << 14)
 136 #define FORMAT_MULTIPLY_RATE_SHIFT              11
 137 #define FORMAT_DIVIDE_RATE_SHIFT                8
 138 #define HDAC_STREAM_BUFFERS_BASE_LOWER  0x18    // 32bits, BDPL
 139 #define HDAC_STREAM_BUFFERS_BASE_UPPER  0x1c    // 32bits, BDPU
 140
 141 /* PCI space register definitions */
 142 #define PCI_HDA_TCSEL                                   0x44
 143 #define PCI_HDA_TCSEL_MASK                              0xf8
 144
 145 #define ATI_HDA_MISC_CNTR2                              0x42
 146 #define ATI_HDA_MISC_CNTR2_MASK                 0xf8
 147 #define ATI_HDA_ENABLE_SNOOP                    0x02
 148 #define NVIDIA_HDA_OSTRM_COH                    0x4c
 149 #define NVIDIA_HDA_ISTRM_COH                    0x4d
 150 #define NVIDIA_HDA_ENABLE_COHBIT                0x01
 151 #define NVIDIA_HDA_TRANSREG                             0x4e
 152 #define NVIDIA_HDA_TRANSREG_MASK                0xf0
 153 #define NVIDIA_HDA_ENABLE_COHBITS               0x0f
 154 #define INTEL_SCH_HDA_DEVC                              0x78
 155 #define INTEL_SCH_HDA_DEVC_SNOOP                0x800
 156
 157
 158 #ifndef __REACTOS__
 159 typedef uint32 corb_t;
 160 typedef struct {
 161         uint32 response;
 162         uint32 flags;
 163 } rirb_t;
 164 #endif
 165
 166 #define RESPONSE_FLAGS_CODEC_MASK               0x0000000f
 167 #define RESPONSE_FLAGS_UNSOLICITED              (1 << 4)
 168
 169 #ifndef __REACTOS__
 170 typedef struct {
 171         uint32  lower;
 172         uint32  upper;
 173         uint32  length;
 174         uint32  ioc;
 175 } bdl_entry_t;
 176 #endif
 177
 178 #endif /* HDAC_REGS_H */