hal/halarm/generic/cache.S

   1 /*
   2  * PROJECT:         ReactOS HAL
   3  * LICENSE:         GPL - See COPYING in the top level directory
   4  * FILE:            hal/halarm/generic/cache.S
   5  * PURPOSE:         Implements cache clean, invalidate routines for ARM machines
   6  * PROGRAMMERS:     Copyright (C) 2005 ARM Ltd.
   7  */
   8
   9     .title "ARM HAL Cache Routines"
  10     .include "ntoskrnl/include/internal/arm/kxarm.h"
  11     .include "ntoskrnl/include/internal/arm/ksarm.h"
  12
  13     NESTED_ENTRY v7_flush_dcache_all
  14     PROLOG_END v7_flush_dcache_all
  15
  16         mrc     p15, 1, r0, c0, c0, 1           // read clidr
  17         ands    r3, r0, #0x7000000              // extract loc from clidr
  18         mov     r3, r3, lsr #23             // left align loc bit field
  19         beq     finished                    // if loc is 0, then no need to clean
  20         mov     r10, #0                     // start clean at cache level 0
  21 loop1:
  22         add     r2, r10, r10, lsr #1            // work out 3x current cache level
  23         mov     r1, r0, lsr r2              // extract cache type bits from clidr
  24         and     r1, r1, #7                  // mask of the bits for current cache only
  25         cmp     r1, #2                      // see what cache we have at this level
  26         blt     skip                        // skip if no cache, or just i-cache
  27         mcr     p15, 2, r10, c0, c0, 0          // select current cache level in cssr
  28         isb                             // isb to sych the new cssr&csidr
  29         mrc     p15, 1, r1, c0, c0, 0           // read the new csidr
  30         and     r2, r1, #7                  // extract the length of the cache lines
  31         add     r2, r2, #4                  // add 4 (line length offset)
  32         ldr     r4, =0x3ff
  33         ands    r4, r4, r1, lsr #3              // find maximum number on the way size
  34         clz     r5, r4                      // find bit position of way size increment
  35         ldr     r7, =0x7fff
  36         ands    r7, r7, r1, lsr #13             // extract max number of the index size
  37 loop2:
  38         mov     r9, r4                      // create working copy of max way size
  39 loop3:
  40         orr     r11, r10, r9, lsl r5            // factor way and cache number into r11
  41         orr     r11, r11, r7, lsl r2            // factor index number into r11
  42         mcr     p15, 0, r11, c7, c14, 2         // clean & invalidate by set/way
  43         subs    r9, r9, #1              // decrement the way
  44         bge     loop3
  45         subs    r7, r7, #1              // decrement the index
  46         bge     loop2
  47 skip:
  48         add     r10, r10, #2                // increment cache number
  49         cmp     r3, r10
  50         bgt     loop1
  51 finished:
  52         mov     r10, #0                     // swith back to cache level 0
  53         mcr     p15, 2, r10, c0, c0, 0          // select current cache level in cssr
  54         isb
  55         mov     pc, lr
  56
  57     ENTRY_END v7_flush_dcache_all