4 * FIXME: This does not work if we have more than 24 IRQs (ie. more than one
7 #define IRQL2VECTOR(irql) (IRQ2VECTOR(PROFILE_LEVEL - (irql)))
9 #define IRQL2TPR(irql) ((irql) >= IPI_LEVEL ? IPI_VECTOR : ((irql) >= PROFILE_LEVEL ? LOCAL_TIMER_VECTOR : ((irql) > DISPATCH_LEVEL ? IRQL2VECTOR(irql) : 0)))
11 typedef struct _KIRQ_TRAPFRAME
29 } KIRQ_TRAPFRAME
, *PKIRQ_TRAPFRAME
;
32 /* This values are defined in halirql.h */
33 #define FIRST_DEVICE_VECTOR 0x30
34 #define FIRST_SYSTEM_VECTOR 0xEF
37 #define NUMBER_DEVICE_VECTORS (FIRST_SYSTEM_VECTOR - FIRST_DEVICE_VECTOR)
40 /* MP Floating Pointer Structure */
41 #define MPF_SIGNATURE (('_' << 24) | ('P' << 16) | ('M' << 8) | '_')
44 typedef struct _MP_FLOATING_POINTER
46 ULONG Signature
; /* _MP_ */
47 ULONG Address
; /* Physical Address Pointer (0 means no configuration table exist) */
48 UCHAR Length
; /* Structure length in 16-byte paragraphs */
49 UCHAR Specification
; /* Specification revision */
50 UCHAR Checksum
; /* Checksum */
51 UCHAR Feature1
; /* MP System Configuration Type */
52 UCHAR Feature2
; /* Bit 7 set for IMCR|PIC */
53 UCHAR Feature3
; /* Unused (0) */
54 UCHAR Feature4
; /* Unused (0) */
55 UCHAR Feature5
; /* Unused (0) */
56 } MP_FLOATING_POINTER
, *PMP_FLOATING_POINTER
;
59 #define FEATURE2_IMCRP 0x80
61 /* MP Configuration Table Header */
62 #define MPC_SIGNATURE (('P' << 24) | ('M' << 16) | ('C' << 8) | 'P')
64 typedef struct _MP_CONFIGURATION_TABLE
66 ULONG Signature
; /* PCMP */
67 USHORT Length
; /* Size of configuration table */
68 CHAR Specification
; /* Specification Revision */
69 CHAR Checksum
; /* Checksum */
70 CHAR Oem
[8]; /* OEM ID */
71 CHAR ProductId
[12]; /* Product ID */
72 ULONG OemTable
; /* 0 if not present */
73 USHORT OemTableSize
; /* 0 if not present */
74 USHORT EntryCount
; /* Number of entries */
75 ULONG LocalAPICAddress
; /* Local APIC address */
76 USHORT ExtTableLength
; /* Extended Table Length */
77 UCHAR ExtTableChecksum
; /* Extended Table Checksum */
78 UCHAR Reserved
; /* Reserved */
79 } MP_CONFIGURATION_TABLE
, *PMP_CONFIGURATION_TABLE
;
81 /* MP Configuration Table Entries */
82 #define MPCTE_PROCESSOR 0 /* One entry per processor */
83 #define MPCTE_BUS 1 /* One entry per bus */
84 #define MPCTE_IOAPIC 2 /* One entry per I/O APIC */
85 #define MPCTE_INTSRC 3 /* One entry per bus interrupt source */
86 #define MPCTE_LINTSRC 4 /* One entry per system interrupt source */
89 typedef struct _MP_CONFIGURATION_PROCESSOR
92 UCHAR ApicId
; /* Local APIC ID for the processor */
93 UCHAR ApicVersion
; /* Local APIC version */
94 UCHAR CpuFlags
; /* CPU flags */
95 ULONG CpuSignature
; /* CPU signature */
96 ULONG FeatureFlags
; /* CPUID feature value */
97 ULONG Reserved
[2]; /* Reserved (0) */
98 } MP_CONFIGURATION_PROCESSOR
, *PMP_CONFIGURATION_PROCESSOR
;
102 typedef struct _MP_CONFIGURATION_BUS
105 UCHAR BusId
; /* Bus ID */
106 CHAR BusType
[6]; /* Bus type */
107 } MP_CONFIGURATION_BUS
, *PMP_CONFIGURATION_BUS
;
112 #define MP_BUS_EISA 2
116 #define BUSTYPE_EISA "EISA"
117 #define BUSTYPE_ISA "ISA"
118 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
119 #define BUSTYPE_MCA "MCA"
120 #define BUSTYPE_VL "VL" /* Local bus */
121 #define BUSTYPE_PCI "PCI"
122 #define BUSTYPE_PCMCIA "PCMCIA"
123 #define BUSTYPE_CBUS "CBUS"
124 #define BUSTYPE_CBUSII "CBUSII"
125 #define BUSTYPE_FUTURE "FUTURE"
126 #define BUSTYPE_MBI "MBI"
127 #define BUSTYPE_MBII "MBII"
128 #define BUSTYPE_MPI "MPI"
129 #define BUSTYPE_MPSA "MPSA"
130 #define BUSTYPE_NUBUS "NUBUS"
131 #define BUSTYPE_TC "TC"
132 #define BUSTYPE_VME "VME"
133 #define BUSTYPE_XPRESS "XPRESS"
136 typedef struct _MP_CONFIGURATION_IOAPIC
139 UCHAR ApicId
; /* I/O APIC ID */
140 UCHAR ApicVersion
; /* I/O APIC version */
141 UCHAR ApicFlags
; /* I/O APIC flags */
142 ULONG ApicAddress
; /* I/O APIC base address */
143 } MP_CONFIGURATION_IOAPIC
, *PMP_CONFIGURATION_IOAPIC
;
147 #define MP_IOAPIC_USABLE 0x01
150 typedef struct _MP_CONFIGURATION_INTSRC
153 UCHAR IrqType
; /* Interrupt type */
154 USHORT IrqFlag
; /* Interrupt flags */
155 UCHAR SrcBusId
; /* Source bus ID */
156 UCHAR SrcBusIrq
; /* Source bus interrupt */
157 UCHAR DstApicId
; /* Destination APIC ID */
158 UCHAR DstApicInt
; /* Destination interrupt */
159 } MP_CONFIGURATION_INTSRC
, *PMP_CONFIGURATION_INTSRC
;
161 #define MAX_IRQ_SOURCE 128
163 #define INT_VECTORED 0
168 #define IRQDIR_DEFAULT 0
169 #define IRQDIR_HIGH 1
173 typedef struct _MP_CONFIGURATION_INTLOCAL
176 UCHAR IrqType
; /* Interrupt type */
177 USHORT IrqFlag
; /* Interrupt flags */
178 UCHAR SrcBusId
; /* Source bus ID */
179 UCHAR SrcBusIrq
; /* Source bus interrupt */
180 UCHAR DstApicId
; /* Destination local APIC ID */
181 UCHAR DstApicLInt
; /* Destination local APIC interrupt */
182 } MP_CONFIGURATION_INTLOCAL
, *PMP_CONFIGURATION_INTLOCAL
;
185 #define MP_APIC_ALL 0xFF
187 #define CPU_FLAG_ENABLED 1 /* Processor is available */
188 #define CPU_FLAG_BSP 2 /* Processor is the bootstrap processor */
190 #define CPU_STEPPING_MASK 0x0F
191 #define CPU_MODEL_MASK 0xF0
192 #define CPU_FAMILY_MASK 0xF00
198 VOID
HalpInitMPS(VOID
);