3 #define PCI_ADDRESS_MEMORY_SPACE 0x00000000
8 #define PASTE2(x,y) x ## y
9 #define POINTER_TO_(x) PASTE2(P,x)
10 #define READ_FROM(x) PASTE2(READ_PORT_, x)
11 #define WRITE_TO(x) PASTE2(WRITE_PORT_, x)
14 // Declares a PCI Register Read/Write Routine
16 #define TYPE_DEFINE(x, y) \
20 IN PPCIPBUSDATA BusData, \
25 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
26 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
29 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
31 #define TYPE1_START(x, y) \
32 TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS) \
34 ULONG i = Offset % sizeof(ULONG); \
35 PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG); \
36 WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
37 #define TYPE1_END(y) \
39 #define TYPE2_END TYPE1_END
42 // PCI Register Read Type 1 Routine
44 #define TYPE1_READ(x, y) \
46 *((POINTER_TO_(y))Buffer) = \
47 READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i)); \
51 // PCI Register Write Type 1 Routine
53 #define TYPE1_WRITE(x, y) \
55 WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i), \
56 *((POINTER_TO_(y))Buffer)); \
60 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
62 #define TYPE2_START(x, y) \
63 TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS) \
65 PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
68 // PCI Register Read Type 2 Routine
70 #define TYPE2_READ(x, y) \
72 *((POINTER_TO_(y))Buffer) = \
73 READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT); \
77 // PCI Register Write Type 2 Routine
79 #define TYPE2_WRITE(x, y) \
81 WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT, \
82 *((POINTER_TO_(y))Buffer)); \
87 IN PBUS_HANDLER BusHandler
,
88 IN PBUS_HANDLER RootHandler
,
89 IN PCI_SLOT_NUMBER PciSlot
,
90 OUT PSUPPORTED_RANGE
*Interrupt
93 typedef struct _PCIPBUSDATA
95 PCIBUSDATA CommonData
;
111 PciIrqRange GetIrqRange
;
112 BOOLEAN BridgeConfigRead
;
117 RTL_BITMAP DeviceConfigured
;
118 ULONG ConfiguredBits
[PCI_MAX_DEVICES
* PCI_MAX_FUNCTION
/ 32];
119 } PCIPBUSDATA
, *PPCIPBUSDATA
;
122 (NTAPI
*FncConfigIO
)(
123 IN PPCIPBUSDATA BusData
,
131 IN PBUS_HANDLER BusHandler
,
132 IN PCI_SLOT_NUMBER Slot
,
138 (NTAPI
*FncReleaseSync
)(
139 IN PBUS_HANDLER BusHandler
,
143 typedef struct _PCI_CONFIG_HANDLER
146 FncReleaseSync ReleaseSynchronzation
;
147 FncConfigIO ConfigRead
[3];
148 FncConfigIO ConfigWrite
[3];
149 } PCI_CONFIG_HANDLER
, *PPCI_CONFIG_HANDLER
;
151 typedef struct _PCI_REGISTRY_INFO_INTERNAL
155 UCHAR NoBuses
; // Number Of Buses
156 UCHAR HardwareMechanism
;
158 PCI_CARD_DESCRIPTOR CardList
[ANYSIZE_ARRAY
];
159 } PCI_REGISTRY_INFO_INTERNAL
, *PPCI_REGISTRY_INFO_INTERNAL
;
164 #define PCI_TYPE1_ADDRESS_PORT (PULONG)0xCF8
165 #define PCI_TYPE1_DATA_PORT 0xCFC
170 #define PCI_TYPE2_CSE_PORT (PUCHAR)0xCF8
171 #define PCI_TYPE2_FORWARD_PORT (PUCHAR)0xCFA
172 #define PCI_TYPE2_ADDRESS_BASE 0xC
175 // PCI Type 1 Configuration Register
177 typedef struct _PCI_TYPE1_CFG_BITS
184 ULONG RegisterNumber
:6;
185 ULONG FunctionNumber
:3;
186 ULONG DeviceNumber
:5;
194 } PCI_TYPE1_CFG_BITS
, *PPCI_TYPE1_CFG_BITS
;
197 // PCI Type 2 CSE Register
199 typedef struct _PCI_TYPE2_CSE_BITS
206 UCHAR FunctionNumber
:3;
212 } PCI_TYPE2_CSE_BITS
, PPCI_TYPE2_CSE_BITS
;
215 // PCI Type 2 Address Register
217 typedef struct _PCI_TYPE2_ADDRESS_BITS
223 USHORT RegisterNumber
:8;
225 USHORT AddressBase
:4;
230 } PCI_TYPE2_ADDRESS_BITS
, *PPCI_TYPE2_ADDRESS_BITS
;
232 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
239 ULONG RegisterNumber
:6;
240 ULONG FunctionNumber
:3;
245 } PCI_TYPE0_CFG_CYCLE_BITS
, *PPCI_TYPE0_CFG_CYCLE_BITS
;
247 typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
254 ULONG RegisterNumber
:6;
255 ULONG FunctionNumber
:3;
256 ULONG DeviceNumber
:5;
262 } PCI_TYPE1_CFG_CYCLE_BITS
, *PPCI_TYPE1_CFG_CYCLE_BITS
;
264 typedef struct _ARRAY
267 PVOID Element
[ANYSIZE_ARRAY
];
270 typedef struct _HAL_BUS_HANDLER
272 LIST_ENTRY AllHandlers
;
273 ULONG ReferenceCount
;
275 } HAL_BUS_HANDLER
, *PHAL_BUS_HANDLER
;
277 /* FUNCTIONS *****************************************************************/
279 /* SHARED (Fake PCI-BUS HANDLER) */
281 extern PCI_CONFIG_HANDLER PCIConfigHandler
;
282 extern PCI_CONFIG_HANDLER PCIConfigHandlerType1
;
283 extern PCI_CONFIG_HANDLER PCIConfigHandlerType2
;
285 PPCI_REGISTRY_INFO_INTERNAL
287 HalpQueryPciRegistryInfo(
293 HalpPCISynchronizeType1(
294 IN PBUS_HANDLER BusHandler
,
295 IN PCI_SLOT_NUMBER Slot
,
297 IN PPCI_TYPE1_CFG_BITS PciCfg
302 HalpPCIReleaseSynchronzationType1(
303 IN PBUS_HANDLER BusHandler
,
309 HalpPCISynchronizeType2(
310 IN PBUS_HANDLER BusHandler
,
311 IN PCI_SLOT_NUMBER Slot
,
313 IN PPCI_TYPE2_ADDRESS_BITS PciCfg
318 HalpPCIReleaseSynchronizationType2(
319 IN PBUS_HANDLER BusHandler
,
323 TYPE1_DEFINE(HalpPCIReadUcharType1
);
324 TYPE1_DEFINE(HalpPCIReadUshortType1
);
325 TYPE1_DEFINE(HalpPCIReadUlongType1
);
326 TYPE2_DEFINE(HalpPCIReadUcharType2
);
327 TYPE2_DEFINE(HalpPCIReadUshortType2
);
328 TYPE2_DEFINE(HalpPCIReadUlongType2
);
329 TYPE1_DEFINE(HalpPCIWriteUcharType1
);
330 TYPE1_DEFINE(HalpPCIWriteUshortType1
);
331 TYPE1_DEFINE(HalpPCIWriteUlongType1
);
332 TYPE2_DEFINE(HalpPCIWriteUcharType2
);
333 TYPE2_DEFINE(HalpPCIWriteUshortType2
);
334 TYPE2_DEFINE(HalpPCIWriteUlongType2
);
339 IN PBUS_HANDLER BusHandler
,
340 IN PCI_SLOT_NUMBER Slot
346 IN PBUS_HANDLER BusHandler
,
347 IN PCI_SLOT_NUMBER Slot
,
356 IN PBUS_HANDLER BusHandler
,
357 IN PCI_SLOT_NUMBER Slot
,
366 IN PBUS_HANDLER BusHandler
,
367 IN PBUS_HANDLER RootBusHandler
,
368 IN PCI_SLOT_NUMBER SlotNumber
,
377 IN PBUS_HANDLER BusHandler
,
378 IN PBUS_HANDLER RootBusHandler
,
379 IN PCI_SLOT_NUMBER SlotNumber
,
387 HalpAssignPCISlotResources(
388 IN PBUS_HANDLER BusHandler
,
389 IN PBUS_HANDLER RootHandler
,
390 IN PUNICODE_STRING RegistryPath
,
391 IN PUNICODE_STRING DriverClassName OPTIONAL
,
392 IN PDRIVER_OBJECT DriverObject
,
393 IN PDEVICE_OBJECT DeviceObject OPTIONAL
,
395 IN OUT PCM_RESOURCE_LIST
*pAllocatedResources
402 HalpGetSystemInterruptVector_Acpi(
404 ULONG BusInterruptLevel
,
405 ULONG BusInterruptVector
,
430 HalpInitializePciBus(
436 HalpInitializePciStubs(
442 HalpTranslateBusAddress(
443 IN INTERFACE_TYPE InterfaceType
,
445 IN PHYSICAL_ADDRESS BusAddress
,
446 IN OUT PULONG AddressSpace
,
447 OUT PPHYSICAL_ADDRESS TranslatedAddress
452 HalpAssignSlotResources(
453 IN PUNICODE_STRING RegistryPath
,
454 IN PUNICODE_STRING DriverClassName
,
455 IN PDRIVER_OBJECT DriverObject
,
456 IN PDEVICE_OBJECT DeviceObject
,
457 IN INTERFACE_TYPE BusType
,
460 IN OUT PCM_RESOURCE_LIST
*AllocatedResources
465 HalpFindBusAddressTranslation(
466 IN PHYSICAL_ADDRESS BusAddress
,
467 IN OUT PULONG AddressSpace
,
468 OUT PPHYSICAL_ADDRESS TranslatedAddress
,
469 IN OUT PULONG_PTR Context
,
475 HalpRegisterPciDebuggingDeviceInfo(
483 HaliTranslateBusAddress(
484 IN INTERFACE_TYPE InterfaceType
,
486 IN PHYSICAL_ADDRESS BusAddress
,
487 IN OUT PULONG AddressSpace
,
488 OUT PPHYSICAL_ADDRESS TranslatedAddress
493 HaliFindBusAddressTranslation(
494 IN PHYSICAL_ADDRESS BusAddress
,
495 IN OUT PULONG AddressSpace
,
496 OUT PPHYSICAL_ADDRESS TranslatedAddress
,
497 IN OUT PULONG_PTR Context
,
503 HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler
,
504 IN PBUS_HANDLER RootHandler
,
505 IN OUT PIO_RESOURCE_REQUIREMENTS_LIST
*pResourceList
);
509 HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler
,
510 IN PBUS_HANDLER RootHandler
,
511 IN ULONG BusInterruptLevel
,
512 IN ULONG BusInterruptVector
,
514 OUT PKAFFINITY Affinity
);
517 HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler
,
518 IN PBUS_HANDLER RootHandler
,
519 IN PCI_SLOT_NUMBER SlotNumber
,
520 IN PPCI_COMMON_CONFIG PciData
);
524 HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler
,
525 IN PBUS_HANDLER RootHandler
,
526 IN PCI_SLOT_NUMBER SlotNumber
,
527 IN PPCI_COMMON_CONFIG PciNewData
,
528 IN PPCI_COMMON_CONFIG PciOldData
);
532 HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler
,
533 IN PBUS_HANDLER RootHandler
,
534 IN PCI_SLOT_NUMBER PciSlot
,
535 OUT PSUPPORTED_RANGE
*Range
);
545 HalpContextToBusHandler(
546 IN ULONG_PTR ContextValue
551 HaliReferenceHandlerForConfigSpace(
552 IN BUS_DATA_TYPE ConfigType
,
559 IN PBUS_HANDLER BusHandler
,
560 IN PBUS_HANDLER RootHandler
,
570 IN PBUS_HANDLER BusHandler
,
571 IN PBUS_HANDLER RootHandler
,
581 IN PBUS_HANDLER BusHandler
,
582 IN PBUS_HANDLER RootHandler
,
591 HalpTranslateSystemBusAddress(
592 IN PBUS_HANDLER BusHandler
,
593 IN PBUS_HANDLER RootHandler
,
594 IN PHYSICAL_ADDRESS BusAddress
,
595 IN OUT PULONG AddressSpace
,
596 OUT PPHYSICAL_ADDRESS TranslatedAddress
601 HalpTranslateIsaBusAddress(
602 IN PBUS_HANDLER BusHandler
,
603 IN PBUS_HANDLER RootHandler
,
604 IN PHYSICAL_ADDRESS BusAddress
,
605 IN OUT PULONG AddressSpace
,
606 OUT PPHYSICAL_ADDRESS TranslatedAddress
611 HalpGetSystemInterruptVector(
612 IN PBUS_HANDLER BusHandler
,
613 IN PBUS_HANDLER RootHandler
,
614 IN ULONG BusInterruptLevel
,
615 IN ULONG BusInterruptVector
,
617 OUT PKAFFINITY Affinity
620 extern ULONG HalpBusType
;
621 extern BOOLEAN HalpPCIConfigInitialized
;
622 extern BUS_HANDLER HalpFakePciBusHandler
;
623 extern ULONG HalpMinPciBus
, HalpMaxPciBus
;
624 extern LIST_ENTRY HalpAllBusHandlers
;