hal/halx86/include/bus.h

   1 #pragma once
   2
   3 #define PCI_ADDRESS_MEMORY_SPACE            0x00000000
   4
   5 //
   6 // Helper Macros
   7 //
   8 #define PASTE2(x,y)                                                     x ## y
   9 #define POINTER_TO_(x)                                                  PASTE2(P,x)
  10 #define READ_FROM(x)                                                    PASTE2(READ_PORT_, x)
  11 #define WRITE_TO(x)                                                     PASTE2(WRITE_PORT_, x)
  12
  13 //
  14 // Declares a PCI Register Read/Write Routine
  15 //
  16 #define TYPE_DEFINE(x, y)                                               \
  17     ULONG                                                               \
  18     NTAPI                                                               \
  19     x(                                                                  \
  20         IN PPCIPBUSDATA BusData,                                        \
  21         IN y PciCfg,                                                    \
  22         IN PUCHAR Buffer,                                               \
  23         IN ULONG Offset                                                 \
  24     )
  25 #define TYPE1_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS);
  26 #define TYPE2_DEFINE(x) TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS);
  27
  28 //
  29 // Defines a PCI Register Read/Write Type 1 Routine Prologue and Epilogue
  30 //
  31 #define TYPE1_START(x, y)                                               \
  32     TYPE_DEFINE(x, PPCI_TYPE1_CFG_BITS)                                 \
  33 {                                                                       \
  34     ULONG i = Offset % sizeof(ULONG);                                   \
  35     PciCfg->u.bits.RegisterNumber = Offset / sizeof(ULONG);             \
  36     WRITE_PORT_ULONG(BusData->Config.Type1.Address, PciCfg->u.AsULONG);
  37 #define TYPE1_END(y)                                                    \
  38     return sizeof(y); }
  39 #define TYPE2_END       TYPE1_END
  40
  41 //
  42 // PCI Register Read Type 1 Routine
  43 //
  44 #define TYPE1_READ(x, y)                                                \
  45     TYPE1_START(x, y)                                                   \
  46     *((POINTER_TO_(y))Buffer) =                                         \
  47     READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i));     \
  48     TYPE1_END(y)
  49
  50 //
  51 // PCI Register Write Type 1 Routine
  52 //
  53 #define TYPE1_WRITE(x, y)                                               \
  54     TYPE1_START(x, y)                                                   \
  55     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)(BusData->Config.Type1.Data + i),       \
  56                 *((POINTER_TO_(y))Buffer));                             \
  57     TYPE1_END(y)
  58
  59 //
  60 // Defines a PCI Register Read/Write Type 2 Routine Prologue and Epilogue
  61 //
  62 #define TYPE2_START(x, y)                                               \
  63     TYPE_DEFINE(x, PPCI_TYPE2_ADDRESS_BITS)                             \
  64 {                                                                       \
  65     PciCfg->u.bits.RegisterNumber = (USHORT)Offset;
  66
  67 //
  68 // PCI Register Read Type 2 Routine
  69 //
  70 #define TYPE2_READ(x, y)                                                \
  71     TYPE2_START(x, y)                                                   \
  72     *((POINTER_TO_(y))Buffer) =                                         \
  73         READ_FROM(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT);        \
  74     TYPE2_END(y)
  75
  76 //
  77 // PCI Register Write Type 2 Routine
  78 //
  79 #define TYPE2_WRITE(x, y)                                               \
  80     TYPE2_START(x, y)                                                   \
  81     WRITE_TO(y)((POINTER_TO_(y))(ULONG_PTR)PciCfg->u.AsUSHORT,              \
  82                 *((POINTER_TO_(y))Buffer));                             \
  83     TYPE2_END(y)
  84
  85 typedef NTSTATUS
  86 (NTAPI *PciIrqRange)(
  87     IN PBUS_HANDLER BusHandler,
  88     IN PBUS_HANDLER RootHandler,
  89     IN PCI_SLOT_NUMBER PciSlot,
  90     OUT PSUPPORTED_RANGE *Interrupt
  91 );
  92
  93 typedef struct _PCIPBUSDATA
  94 {
  95     PCIBUSDATA CommonData;
  96     union
  97     {
  98         struct
  99         {
 100             PULONG Address;
 101             ULONG Data;
 102         } Type1;
 103         struct
 104         {
 105             PUCHAR CSE;
 106             PUCHAR Forward;
 107             ULONG Base;
 108         } Type2;
 109     } Config;
 110     ULONG MaxDevice;
 111     PciIrqRange GetIrqRange;
 112     BOOLEAN BridgeConfigRead;
 113     UCHAR ParentBus;
 114     UCHAR Subtractive;
 115     UCHAR reserved[1];
 116     UCHAR SwizzleIn[4];
 117     RTL_BITMAP DeviceConfigured;
 118     ULONG ConfiguredBits[PCI_MAX_DEVICES * PCI_MAX_FUNCTION / 32];
 119 } PCIPBUSDATA, *PPCIPBUSDATA;
 120
 121 typedef ULONG
 122 (NTAPI *FncConfigIO)(
 123     IN PPCIPBUSDATA BusData,
 124     IN PVOID State,
 125     IN PUCHAR Buffer,
 126     IN ULONG Offset
 127 );
 128
 129 typedef VOID
 130 (NTAPI *FncSync)(
 131     IN PBUS_HANDLER BusHandler,
 132     IN PCI_SLOT_NUMBER Slot,
 133     IN PKIRQL Irql,
 134     IN PVOID State
 135 );
 136
 137 typedef VOID
 138 (NTAPI *FncReleaseSync)(
 139     IN PBUS_HANDLER BusHandler,
 140     IN KIRQL Irql
 141 );
 142
 143 typedef struct _PCI_CONFIG_HANDLER
 144 {
 145     FncSync Synchronize;
 146     FncReleaseSync ReleaseSynchronzation;
 147     FncConfigIO ConfigRead[3];
 148     FncConfigIO ConfigWrite[3];
 149 } PCI_CONFIG_HANDLER, *PPCI_CONFIG_HANDLER;
 150
 151 typedef struct _PCI_REGISTRY_INFO_INTERNAL
 152 {
 153     UCHAR MajorRevision;
 154     UCHAR MinorRevision;
 155     UCHAR NoBuses; // Number Of Buses
 156     UCHAR HardwareMechanism;
 157     ULONG ElementCount;
 158     PCI_CARD_DESCRIPTOR CardList[ANYSIZE_ARRAY];
 159 } PCI_REGISTRY_INFO_INTERNAL, *PPCI_REGISTRY_INFO_INTERNAL;
 160
 161 //
 162 // PCI Type 1 Ports
 163 //
 164 #define PCI_TYPE1_ADDRESS_PORT      (PULONG)0xCF8
 165 #define PCI_TYPE1_DATA_PORT         0xCFC
 166
 167 //
 168 // PCI Type 2 Ports
 169 //
 170 #define PCI_TYPE2_CSE_PORT          (PUCHAR)0xCF8
 171 #define PCI_TYPE2_FORWARD_PORT      (PUCHAR)0xCFA
 172 #define PCI_TYPE2_ADDRESS_BASE      0xC
 173
 174 //
 175 // PCI Type 1 Configuration Register
 176 //
 177 typedef struct _PCI_TYPE1_CFG_BITS
 178 {
 179     union
 180     {
 181         struct
 182         {
 183             ULONG Reserved1:2;
 184             ULONG RegisterNumber:6;
 185             ULONG FunctionNumber:3;
 186             ULONG DeviceNumber:5;
 187             ULONG BusNumber:8;
 188             ULONG Reserved2:7;
 189             ULONG Enable:1;
 190         } bits;
 191
 192         ULONG AsULONG;
 193     } u;
 194 } PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
 195
 196 //
 197 // PCI Type 2 CSE Register
 198 //
 199 typedef struct _PCI_TYPE2_CSE_BITS
 200 {
 201     union
 202     {
 203         struct
 204         {
 205             UCHAR Enable:1;
 206             UCHAR FunctionNumber:3;
 207             UCHAR Key:4;
 208         } bits;
 209
 210         UCHAR AsUCHAR;
 211     } u;
 212 } PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
 213
 214 //
 215 // PCI Type 2 Address Register
 216 //
 217 typedef struct _PCI_TYPE2_ADDRESS_BITS
 218 {
 219     union
 220     {
 221         struct
 222         {
 223             USHORT RegisterNumber:8;
 224             USHORT Agent:4;
 225             USHORT AddressBase:4;
 226         } bits;
 227
 228         USHORT AsUSHORT;
 229     } u;
 230 } PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
 231
 232 typedef struct _PCI_TYPE0_CFG_CYCLE_BITS
 233 {
 234     union
 235     {
 236         struct
 237         {
 238             ULONG Reserved1:2;
 239             ULONG RegisterNumber:6;
 240             ULONG FunctionNumber:3;
 241             ULONG Reserved2:21;
 242         } bits;
 243         ULONG AsULONG;
 244     } u;
 245 } PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
 246
 247 typedef struct _PCI_TYPE1_CFG_CYCLE_BITS
 248 {
 249     union
 250     {
 251         struct
 252         {
 253             ULONG Reserved1:2;
 254             ULONG RegisterNumber:6;
 255             ULONG FunctionNumber:3;
 256             ULONG DeviceNumber:5;
 257             ULONG BusNumber:8;
 258             ULONG Reserved2:8;
 259         } bits;
 260         ULONG AsULONG;
 261     } u;
 262 } PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
 263
 264 typedef struct _ARRAY
 265 {
 266     ULONG ArraySize;
 267     PVOID Element[ANYSIZE_ARRAY];
 268 } ARRAY, *PARRAY;
 269
 270 typedef struct _HAL_BUS_HANDLER
 271 {
 272     LIST_ENTRY AllHandlers;
 273     ULONG ReferenceCount;
 274     BUS_HANDLER Handler;
 275 } HAL_BUS_HANDLER, *PHAL_BUS_HANDLER;
 276
 277 /* FUNCTIONS *****************************************************************/
 278
 279 /* SHARED (Fake PCI-BUS HANDLER) */
 280
 281 extern PCI_CONFIG_HANDLER PCIConfigHandler;
 282 extern PCI_CONFIG_HANDLER PCIConfigHandlerType1;
 283 extern PCI_CONFIG_HANDLER PCIConfigHandlerType2;
 284
 285 PPCI_REGISTRY_INFO_INTERNAL
 286 NTAPI
 287 HalpQueryPciRegistryInfo(
 288     VOID
 289 );
 290
 291 VOID
 292 NTAPI
 293 HalpPCISynchronizeType1(
 294     IN PBUS_HANDLER BusHandler,
 295     IN PCI_SLOT_NUMBER Slot,
 296     IN PKIRQL Irql,
 297     IN PPCI_TYPE1_CFG_BITS PciCfg
 298 );
 299
 300 VOID
 301 NTAPI
 302 HalpPCIReleaseSynchronzationType1(
 303     IN PBUS_HANDLER BusHandler,
 304     IN KIRQL Irql
 305 );
 306
 307 VOID
 308 NTAPI
 309 HalpPCISynchronizeType2(
 310     IN PBUS_HANDLER BusHandler,
 311     IN PCI_SLOT_NUMBER Slot,
 312     IN PKIRQL Irql,
 313     IN PPCI_TYPE2_ADDRESS_BITS PciCfg
 314 );
 315
 316 VOID
 317 NTAPI
 318 HalpPCIReleaseSynchronizationType2(
 319     IN PBUS_HANDLER BusHandler,
 320     IN KIRQL Irql
 321 );
 322
 323 TYPE1_DEFINE(HalpPCIReadUcharType1);
 324 TYPE1_DEFINE(HalpPCIReadUshortType1);
 325 TYPE1_DEFINE(HalpPCIReadUlongType1);
 326 TYPE2_DEFINE(HalpPCIReadUcharType2);
 327 TYPE2_DEFINE(HalpPCIReadUshortType2);
 328 TYPE2_DEFINE(HalpPCIReadUlongType2);
 329 TYPE1_DEFINE(HalpPCIWriteUcharType1);
 330 TYPE1_DEFINE(HalpPCIWriteUshortType1);
 331 TYPE1_DEFINE(HalpPCIWriteUlongType1);
 332 TYPE2_DEFINE(HalpPCIWriteUcharType2);
 333 TYPE2_DEFINE(HalpPCIWriteUshortType2);
 334 TYPE2_DEFINE(HalpPCIWriteUlongType2);
 335
 336 BOOLEAN
 337 NTAPI
 338 HalpValidPCISlot(
 339     IN PBUS_HANDLER BusHandler,
 340     IN PCI_SLOT_NUMBER Slot
 341 );
 342
 343 VOID
 344 NTAPI
 345 HalpReadPCIConfig(
 346     IN PBUS_HANDLER BusHandler,
 347     IN PCI_SLOT_NUMBER Slot,
 348     IN PVOID Buffer,
 349     IN ULONG Offset,
 350     IN ULONG Length
 351 );
 352
 353 VOID
 354 NTAPI
 355 HalpWritePCIConfig(
 356     IN PBUS_HANDLER BusHandler,
 357     IN PCI_SLOT_NUMBER Slot,
 358     IN PVOID Buffer,
 359     IN ULONG Offset,
 360     IN ULONG Length
 361 );
 362
 363 ULONG
 364 NTAPI
 365 HalpGetPCIData(
 366     IN PBUS_HANDLER BusHandler,
 367     IN PBUS_HANDLER RootBusHandler,
 368     IN ULONG SlotNumber,
 369     IN PVOID Buffer,
 370     IN ULONG Offset,
 371     IN ULONG Length
 372 );
 373
 374 ULONG
 375 NTAPI
 376 HalpSetPCIData(
 377     IN PBUS_HANDLER BusHandler,
 378     IN PBUS_HANDLER RootBusHandler,
 379     IN ULONG SlotNumber,
 380     IN PVOID Buffer,
 381     IN ULONG Offset,
 382     IN ULONG Length
 383 );
 384
 385 NTSTATUS
 386 NTAPI
 387 HalpAssignPCISlotResources(
 388     IN PBUS_HANDLER BusHandler,
 389     IN PBUS_HANDLER RootHandler,
 390     IN PUNICODE_STRING RegistryPath,
 391     IN PUNICODE_STRING DriverClassName OPTIONAL,
 392     IN PDRIVER_OBJECT DriverObject,
 393     IN PDEVICE_OBJECT DeviceObject OPTIONAL,
 394     IN ULONG Slot,
 395     IN OUT PCM_RESOURCE_LIST *pAllocatedResources
 396 );
 397
 398 /* NON-LEGACY */
 399
 400 ULONG
 401 NTAPI
 402 HalpGetSystemInterruptVector_Acpi(
 403     ULONG BusNumber,
 404     ULONG BusInterruptLevel,
 405     ULONG BusInterruptVector,
 406     PKIRQL Irql,
 407     PKAFFINITY Affinity
 408 );
 409
 410 ULONG
 411 NTAPI
 412 HalpGetCmosData(
 413     IN ULONG BusNumber,
 414     IN ULONG SlotNumber,
 415     IN PVOID Buffer,
 416     IN ULONG Length
 417 );
 418
 419 ULONG
 420 NTAPI
 421 HalpSetCmosData(
 422     IN ULONG BusNumber,
 423     IN ULONG SlotNumber,
 424     IN PVOID Buffer,
 425     IN ULONG Length
 426 );
 427
 428 VOID
 429 NTAPI
 430 HalpInitializePciBus(
 431     VOID
 432 );
 433
 434 VOID
 435 NTAPI
 436 HalpInitializePciStubs(
 437     VOID
 438 );
 439
 440 BOOLEAN
 441 NTAPI
 442 HalpTranslateBusAddress(
 443     IN INTERFACE_TYPE InterfaceType,
 444     IN ULONG BusNumber,
 445     IN PHYSICAL_ADDRESS BusAddress,
 446     IN OUT PULONG AddressSpace,
 447     OUT PPHYSICAL_ADDRESS TranslatedAddress
 448 );
 449
 450 NTSTATUS
 451 NTAPI
 452 HalpAssignSlotResources(
 453     IN PUNICODE_STRING RegistryPath,
 454     IN PUNICODE_STRING DriverClassName,
 455     IN PDRIVER_OBJECT DriverObject,
 456     IN PDEVICE_OBJECT DeviceObject,
 457     IN INTERFACE_TYPE BusType,
 458     IN ULONG BusNumber,
 459     IN ULONG SlotNumber,
 460     IN OUT PCM_RESOURCE_LIST *AllocatedResources
 461 );
 462
 463 BOOLEAN
 464 NTAPI
 465 HalpFindBusAddressTranslation(
 466     IN PHYSICAL_ADDRESS BusAddress,
 467     IN OUT PULONG AddressSpace,
 468     OUT PPHYSICAL_ADDRESS TranslatedAddress,
 469     IN OUT PULONG_PTR Context,
 470     IN BOOLEAN NextBus
 471 );
 472
 473 VOID
 474 NTAPI
 475 HalpRegisterPciDebuggingDeviceInfo(
 476     VOID
 477 );
 478
 479 /* LEGACY */
 480
 481 BOOLEAN
 482 NTAPI
 483 HaliTranslateBusAddress(
 484     IN INTERFACE_TYPE InterfaceType,
 485     IN ULONG BusNumber,
 486     IN PHYSICAL_ADDRESS BusAddress,
 487     IN OUT PULONG AddressSpace,
 488     OUT PPHYSICAL_ADDRESS TranslatedAddress
 489 );
 490
 491 BOOLEAN
 492 NTAPI
 493 HaliFindBusAddressTranslation(
 494     IN PHYSICAL_ADDRESS BusAddress,
 495     IN OUT PULONG AddressSpace,
 496     OUT PPHYSICAL_ADDRESS TranslatedAddress,
 497     IN OUT PULONG_PTR Context,
 498     IN BOOLEAN NextBus
 499 );
 500
 501 NTSTATUS
 502 NTAPI
 503 HalpAdjustPCIResourceList(IN PBUS_HANDLER BusHandler,
 504                           IN PBUS_HANDLER RootHandler,
 505                           IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList);
 506
 507 ULONG
 508 NTAPI
 509 HalpGetPCIIntOnISABus(IN PBUS_HANDLER BusHandler,
 510                       IN PBUS_HANDLER RootHandler,
 511                       IN ULONG BusInterruptLevel,
 512                       IN ULONG BusInterruptVector,
 513                       OUT PKIRQL Irql,
 514                       OUT PKAFFINITY Affinity);
 515 VOID
 516 NTAPI
 517 HalpPCIPin2ISALine(IN PBUS_HANDLER BusHandler,
 518                    IN PBUS_HANDLER RootHandler,
 519                    IN PCI_SLOT_NUMBER SlotNumber,
 520                    IN PPCI_COMMON_CONFIG PciData);
 521
 522 VOID
 523 NTAPI
 524 HalpPCIISALine2Pin(IN PBUS_HANDLER BusHandler,
 525                    IN PBUS_HANDLER RootHandler,
 526                    IN PCI_SLOT_NUMBER SlotNumber,
 527                    IN PPCI_COMMON_CONFIG PciNewData,
 528                    IN PPCI_COMMON_CONFIG PciOldData);
 529
 530 NTSTATUS
 531 NTAPI
 532 HalpGetISAFixedPCIIrq(IN PBUS_HANDLER BusHandler,
 533                       IN PBUS_HANDLER RootHandler,
 534                       IN PCI_SLOT_NUMBER PciSlot,
 535                       OUT PSUPPORTED_RANGE *Range);
 536
 537 VOID
 538 NTAPI
 539 HalpInitBusHandler(
 540     VOID
 541 );
 542
 543 PBUS_HANDLER
 544 NTAPI
 545 HalpContextToBusHandler(
 546     IN ULONG_PTR ContextValue
 547 );
 548
 549 PBUS_HANDLER
 550 FASTCALL
 551 HaliReferenceHandlerForConfigSpace(
 552     IN BUS_DATA_TYPE ConfigType,
 553     IN ULONG BusNumber
 554 );
 555
 556 ULONG
 557 NTAPI
 558 HalpNoBusData(
 559     IN PBUS_HANDLER BusHandler,
 560     IN PBUS_HANDLER RootHandler,
 561     IN ULONG SlotNumber,
 562     IN PVOID Buffer,
 563     IN ULONG Offset,
 564     IN ULONG Length
 565 );
 566
 567 ULONG
 568 NTAPI
 569 HalpcGetCmosData(
 570     IN PBUS_HANDLER BusHandler,
 571     IN PBUS_HANDLER RootHandler,
 572     IN ULONG SlotNumber,
 573     IN PVOID Buffer,
 574     IN ULONG Offset,
 575     IN ULONG Length
 576 );
 577
 578 ULONG
 579 NTAPI
 580 HalpcSetCmosData(
 581     IN PBUS_HANDLER BusHandler,
 582     IN PBUS_HANDLER RootHandler,
 583     IN ULONG SlotNumber,
 584     IN PVOID Buffer,
 585     IN ULONG Offset,
 586     IN ULONG Length
 587 );
 588
 589 BOOLEAN
 590 NTAPI
 591 HalpTranslateSystemBusAddress(
 592     IN PBUS_HANDLER BusHandler,
 593     IN PBUS_HANDLER RootHandler,
 594     IN PHYSICAL_ADDRESS BusAddress,
 595     IN OUT PULONG AddressSpace,
 596     OUT PPHYSICAL_ADDRESS TranslatedAddress
 597 );
 598
 599 BOOLEAN
 600 NTAPI
 601 HalpTranslateIsaBusAddress(
 602     IN PBUS_HANDLER BusHandler,
 603     IN PBUS_HANDLER RootHandler,
 604     IN PHYSICAL_ADDRESS BusAddress,
 605     IN OUT PULONG AddressSpace,
 606     OUT PPHYSICAL_ADDRESS TranslatedAddress
 607 );
 608
 609 ULONG
 610 NTAPI
 611 HalpGetSystemInterruptVector(
 612     IN PBUS_HANDLER BusHandler,
 613     IN PBUS_HANDLER RootHandler,
 614     IN ULONG BusInterruptLevel,
 615     IN ULONG BusInterruptVector,
 616     OUT PKIRQL Irql,
 617     OUT PKAFFINITY Affinity
 618 );
 619
 620 extern ULONG HalpBusType;
 621 extern BOOLEAN HalpPCIConfigInitialized;
 622 extern BUS_HANDLER HalpFakePciBusHandler;
 623 extern ULONG HalpMinPciBus, HalpMaxPciBus;
 624 extern LIST_ENTRY HalpAllBusHandlers;
 625
 626 /* EOF */