[HAL][FREELDR] Fix system timer oscillator frequency on a Xbox (#2245)
[reactos.git] / hal / halx86 / include / halp.h
1 /*
2 *
3 */
4
5 #pragma once
6
7 #ifdef CONFIG_SMP
8 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
9 #else
10 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
11 #endif
12
13 typedef struct _HAL_BIOS_FRAME
14 {
15 ULONG SegSs;
16 ULONG Esp;
17 ULONG EFlags;
18 ULONG SegCs;
19 ULONG Eip;
20 PKTRAP_FRAME TrapFrame;
21 ULONG CsLimit;
22 ULONG CsBase;
23 ULONG CsFlags;
24 ULONG SsLimit;
25 ULONG SsBase;
26 ULONG SsFlags;
27 ULONG Prefix;
28 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
29
30 typedef
31 VOID
32 (__cdecl *PHAL_SW_INTERRUPT_HANDLER)(
33 VOID
34 );
35
36 typedef
37 VOID
38 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
39 IN PKTRAP_FRAME TrapFrame
40 );
41
42 #define HAL_APC_REQUEST 0
43 #define HAL_DPC_REQUEST 1
44
45 /* HAL profiling offsets in KeGetPcr()->HalReserved[] */
46 #define HAL_PROFILING_INTERVAL 0
47 #define HAL_PROFILING_MULTIPLIER 1
48
49 /* CMOS Registers and Ports */
50 #define CMOS_CONTROL_PORT (PUCHAR)0x70
51 #define CMOS_DATA_PORT (PUCHAR)0x71
52 #define RTC_REGISTER_A 0x0A
53 #define RTC_REG_A_UIP 0x80
54 #define RTC_REGISTER_B 0x0B
55 #define RTC_REG_B_PI 0x40
56 #define RTC_REGISTER_C 0x0C
57 #define RTC_REG_C_IRQ 0x80
58 #define RTC_REGISTER_D 0x0D
59 #define RTC_REGISTER_CENTURY 0x32
60
61 /* Usage flags */
62 #define IDT_REGISTERED 0x01
63 #define IDT_LATCHED 0x02
64 #define IDT_READ_ONLY 0x04
65 #define IDT_INTERNAL 0x11
66 #define IDT_DEVICE 0x21
67
68 /* Conversion functions */
69 #define BCD_INT(bcd) \
70 (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
71 #define INT_BCD(int) \
72 (UCHAR)(((int / 10) << 4) + (int % 10))
73
74 //
75 // BIOS Interrupts
76 //
77 #define VIDEO_SERVICES 0x10
78
79 //
80 // Operations for INT 10h (in AH)
81 //
82 #define SET_VIDEO_MODE 0x00
83
84 //
85 // Video Modes for INT10h AH=00 (in AL)
86 //
87 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
88
89 #if defined(SARCH_XBOX)
90 //
91 // For some unknown reason the PIT of the Xbox is fixed at 1.125000 MHz,
92 // which is ~5.7% lower than on the PC.
93 //
94 #define PIT_FREQUENCY 1125000
95 #else
96 //
97 // Commonly stated as being 1.19318MHz
98 //
99 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
100 // p. 471
101 //
102 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
103 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
104 //
105 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
106 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
107 // infinite series) and divides it by three, one obtains 1.19318167.
108 //
109 // It may be that the original NT HAL source code introduced a typo and turned
110 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
111 // number is quite long.
112 //
113 #define PIT_FREQUENCY 1193182
114 #endif
115
116 //
117 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
118 //
119 #define TIMER_CHANNEL0_DATA_PORT 0x40
120 #define TIMER_CHANNEL1_DATA_PORT 0x41
121 #define TIMER_CHANNEL2_DATA_PORT 0x42
122 #define TIMER_CONTROL_PORT 0x43
123
124 //
125 // Mode 0 - Interrupt On Terminal Count
126 // Mode 1 - Hardware Re-triggerable One-Shot
127 // Mode 2 - Rate Generator
128 // Mode 3 - Square Wave Generator
129 // Mode 4 - Software Triggered Strobe
130 // Mode 5 - Hardware Triggered Strobe
131 //
132 typedef enum _TIMER_OPERATING_MODES
133 {
134 PitOperatingMode0,
135 PitOperatingMode1,
136 PitOperatingMode2,
137 PitOperatingMode3,
138 PitOperatingMode4,
139 PitOperatingMode5,
140 PitOperatingMode2Reserved,
141 PitOperatingMode5Reserved
142 } TIMER_OPERATING_MODES;
143
144 typedef enum _TIMER_ACCESS_MODES
145 {
146 PitAccessModeCounterLatch,
147 PitAccessModeLow,
148 PitAccessModeHigh,
149 PitAccessModeLowHigh
150 } TIMER_ACCESS_MODES;
151
152 typedef enum _TIMER_CHANNELS
153 {
154 PitChannel0,
155 PitChannel1,
156 PitChannel2,
157 PitReadBack
158 } TIMER_CHANNELS;
159
160 typedef union _TIMER_CONTROL_PORT_REGISTER
161 {
162 struct
163 {
164 UCHAR BcdMode:1;
165 UCHAR OperatingMode:3;
166 UCHAR AccessMode:2;
167 UCHAR Channel:2;
168 };
169 UCHAR Bits;
170 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
171
172 //
173 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
174 // P. 400
175 //
176 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
177 //
178 #define SYSTEM_CONTROL_PORT_A 0x92
179 #define SYSTEM_CONTROL_PORT_B 0x61
180 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
181 {
182 struct
183 {
184 UCHAR Timer2GateToSpeaker:1;
185 UCHAR SpeakerDataEnable:1;
186 UCHAR ParityCheckEnable:1;
187 UCHAR ChannelCheckEnable:1;
188 UCHAR RefreshRequest:1;
189 UCHAR Timer2Output:1;
190 UCHAR ChannelCheck:1;
191 UCHAR ParityCheck:1;
192 };
193 UCHAR Bits;
194 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
195
196 //
197 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
198 // P. 396, 397
199 //
200 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
201 //
202 #define PIC1_CONTROL_PORT 0x20
203 #define PIC1_DATA_PORT 0x21
204 #define PIC2_CONTROL_PORT 0xA0
205 #define PIC2_DATA_PORT 0xA1
206
207 //
208 // Definitions for ICW/OCW Bits
209 //
210 typedef enum _I8259_ICW1_OPERATING_MODE
211 {
212 Cascade,
213 Single
214 } I8259_ICW1_OPERATING_MODE;
215
216 typedef enum _I8259_ICW1_INTERRUPT_MODE
217 {
218 EdgeTriggered,
219 LevelTriggered
220 } I8259_ICW1_INTERRUPT_MODE;
221
222 typedef enum _I8259_ICW1_INTERVAL
223 {
224 Interval8,
225 Interval4
226 } I8259_ICW1_INTERVAL;
227
228 typedef enum _I8259_ICW4_SYSTEM_MODE
229 {
230 Mcs8085Mode,
231 New8086Mode
232 } I8259_ICW4_SYSTEM_MODE;
233
234 typedef enum _I8259_ICW4_EOI_MODE
235 {
236 NormalEoi,
237 AutomaticEoi
238 } I8259_ICW4_EOI_MODE;
239
240 typedef enum _I8259_ICW4_BUFFERED_MODE
241 {
242 NonBuffered,
243 NonBuffered2,
244 BufferedSlave,
245 BufferedMaster
246 } I8259_ICW4_BUFFERED_MODE;
247
248 typedef enum _I8259_READ_REQUEST
249 {
250 InvalidRequest,
251 InvalidRequest2,
252 ReadIdr,
253 ReadIsr
254 } I8259_READ_REQUEST;
255
256 typedef enum _I8259_EOI_MODE
257 {
258 RotateAutoEoiClear,
259 NonSpecificEoi,
260 InvalidEoiMode,
261 SpecificEoi,
262 RotateAutoEoiSet,
263 RotateNonSpecific,
264 SetPriority,
265 RotateSpecific
266 } I8259_EOI_MODE;
267
268 //
269 // Definitions for ICW Registers
270 //
271 typedef union _I8259_ICW1
272 {
273 struct
274 {
275 UCHAR NeedIcw4:1;
276 UCHAR OperatingMode:1;
277 UCHAR Interval:1;
278 UCHAR InterruptMode:1;
279 UCHAR Init:1;
280 UCHAR InterruptVectorAddress:3;
281 };
282 UCHAR Bits;
283 } I8259_ICW1, *PI8259_ICW1;
284
285 typedef union _I8259_ICW2
286 {
287 struct
288 {
289 UCHAR Sbz:3;
290 UCHAR InterruptVector:5;
291 };
292 UCHAR Bits;
293 } I8259_ICW2, *PI8259_ICW2;
294
295 typedef union _I8259_ICW3
296 {
297 union
298 {
299 struct
300 {
301 UCHAR SlaveIrq0:1;
302 UCHAR SlaveIrq1:1;
303 UCHAR SlaveIrq2:1;
304 UCHAR SlaveIrq3:1;
305 UCHAR SlaveIrq4:1;
306 UCHAR SlaveIrq5:1;
307 UCHAR SlaveIrq6:1;
308 UCHAR SlaveIrq7:1;
309 };
310 struct
311 {
312 UCHAR SlaveId:3;
313 UCHAR Reserved:5;
314 };
315 };
316 UCHAR Bits;
317 } I8259_ICW3, *PI8259_ICW3;
318
319 typedef union _I8259_ICW4
320 {
321 struct
322 {
323 UCHAR SystemMode:1;
324 UCHAR EoiMode:1;
325 UCHAR BufferedMode:2;
326 UCHAR SpecialFullyNestedMode:1;
327 UCHAR Reserved:3;
328 };
329 UCHAR Bits;
330 } I8259_ICW4, *PI8259_ICW4;
331
332 typedef union _I8259_OCW2
333 {
334 struct
335 {
336 UCHAR IrqNumber:3;
337 UCHAR Sbz:2;
338 UCHAR EoiMode:3;
339 };
340 UCHAR Bits;
341 } I8259_OCW2, *PI8259_OCW2;
342
343 typedef union _I8259_OCW3
344 {
345 struct
346 {
347 UCHAR ReadRequest:2;
348 UCHAR PollCommand:1;
349 UCHAR Sbo:1;
350 UCHAR Sbz:1;
351 UCHAR SpecialMaskMode:2;
352 UCHAR Reserved:1;
353 };
354 UCHAR Bits;
355 } I8259_OCW3, *PI8259_OCW3;
356
357 typedef union _I8259_ISR
358 {
359 union
360 {
361 struct
362 {
363 UCHAR Irq0:1;
364 UCHAR Irq1:1;
365 UCHAR Irq2:1;
366 UCHAR Irq3:1;
367 UCHAR Irq4:1;
368 UCHAR Irq5:1;
369 UCHAR Irq6:1;
370 UCHAR Irq7:1;
371 };
372 };
373 UCHAR Bits;
374 } I8259_ISR, *PI8259_ISR;
375
376 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
377
378 //
379 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
380 // P. 34, 35
381 //
382 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
383 //
384 #define EISA_ELCR_MASTER 0x4D0
385 #define EISA_ELCR_SLAVE 0x4D1
386
387 typedef union _EISA_ELCR
388 {
389 struct
390 {
391 struct
392 {
393 UCHAR Irq0Level:1;
394 UCHAR Irq1Level:1;
395 UCHAR Irq2Level:1;
396 UCHAR Irq3Level:1;
397 UCHAR Irq4Level:1;
398 UCHAR Irq5Level:1;
399 UCHAR Irq6Level:1;
400 UCHAR Irq7Level:1;
401 } Master;
402 struct
403 {
404 UCHAR Irq8Level:1;
405 UCHAR Irq9Level:1;
406 UCHAR Irq10Level:1;
407 UCHAR Irq11Level:1;
408 UCHAR Irq12Level:1;
409 UCHAR Irq13Level:1;
410 UCHAR Irq14Level:1;
411 UCHAR Irq15Level:1;
412 } Slave;
413 };
414 USHORT Bits;
415 } EISA_ELCR, *PEISA_ELCR;
416
417 typedef struct _PIC_MASK
418 {
419 union
420 {
421 struct
422 {
423 UCHAR Master;
424 UCHAR Slave;
425 };
426 USHORT Both;
427 };
428 } PIC_MASK, *PPIC_MASK;
429
430 typedef
431 BOOLEAN
432 (NTAPI *PHAL_DISMISS_INTERRUPT)(
433 IN KIRQL Irql,
434 IN ULONG Irq,
435 OUT PKIRQL OldIrql
436 );
437
438 BOOLEAN
439 NTAPI
440 HalpDismissIrqGeneric(
441 IN KIRQL Irql,
442 IN ULONG Irq,
443 OUT PKIRQL OldIrql
444 );
445
446 BOOLEAN
447 NTAPI
448 HalpDismissIrq15(
449 IN KIRQL Irql,
450 IN ULONG Irq,
451 OUT PKIRQL OldIrql
452 );
453
454 BOOLEAN
455 NTAPI
456 HalpDismissIrq13(
457 IN KIRQL Irql,
458 IN ULONG Irq,
459 OUT PKIRQL OldIrql
460 );
461
462 BOOLEAN
463 NTAPI
464 HalpDismissIrq07(
465 IN KIRQL Irql,
466 IN ULONG Irq,
467 OUT PKIRQL OldIrql
468 );
469
470 BOOLEAN
471 NTAPI
472 HalpDismissIrqLevel(
473 IN KIRQL Irql,
474 IN ULONG Irq,
475 OUT PKIRQL OldIrql
476 );
477
478 BOOLEAN
479 NTAPI
480 HalpDismissIrq15Level(
481 IN KIRQL Irql,
482 IN ULONG Irq,
483 OUT PKIRQL OldIrql
484 );
485
486 BOOLEAN
487 NTAPI
488 HalpDismissIrq13Level(
489 IN KIRQL Irql,
490 IN ULONG Irq,
491 OUT PKIRQL OldIrql
492 );
493
494 BOOLEAN
495 NTAPI
496 HalpDismissIrq07Level(
497 IN KIRQL Irql,
498 IN ULONG Irq,
499 OUT PKIRQL OldIrql
500 );
501
502 VOID
503 __cdecl
504 HalpHardwareInterruptLevel(
505 VOID
506 );
507
508 //
509 // Hack Flags
510 //
511 #define HALP_REVISION_FROM_HACK_FLAGS(x) ((x) >> 24)
512 #define HALP_REVISION_HACK_FLAGS(x) ((x) >> 12)
513 #define HALP_HACK_FLAGS(x) ((x) & 0xFFF)
514
515 //
516 // Feature flags
517 //
518 #define HALP_CARD_FEATURE_FULL_DECODE 0x0001
519
520 //
521 // Match Flags
522 //
523 #define HALP_CHECK_CARD_REVISION_ID 0x10000
524 #define HALP_CHECK_CARD_SUBVENDOR_ID 0x20000
525 #define HALP_CHECK_CARD_SUBSYSTEM_ID 0x40000
526
527 //
528 // Mm PTE/PDE to Hal PTE/PDE
529 //
530 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
531 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
532
533 typedef struct _IDTUsageFlags
534 {
535 UCHAR Flags;
536 } IDTUsageFlags;
537
538 typedef struct
539 {
540 KIRQL Irql;
541 UCHAR BusReleativeVector;
542 } IDTUsage;
543
544 typedef struct _HalAddressUsage
545 {
546 struct _HalAddressUsage *Next;
547 CM_RESOURCE_TYPE Type;
548 UCHAR Flags;
549 struct
550 {
551 ULONG Start;
552 ULONG Length;
553 } Element[];
554 } ADDRESS_USAGE, *PADDRESS_USAGE;
555
556 /* adapter.c */
557 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
558
559 /* sysinfo.c */
560 INIT_FUNCTION
561 VOID
562 NTAPI
563 HalpRegisterVector(IN UCHAR Flags,
564 IN ULONG BusVector,
565 IN ULONG SystemVector,
566 IN KIRQL Irql);
567
568 INIT_FUNCTION
569 VOID
570 NTAPI
571 HalpEnableInterruptHandler(IN UCHAR Flags,
572 IN ULONG BusVector,
573 IN ULONG SystemVector,
574 IN KIRQL Irql,
575 IN PVOID Handler,
576 IN KINTERRUPT_MODE Mode);
577
578 /* pic.c */
579 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
580 VOID __cdecl HalpApcInterrupt(VOID);
581 VOID __cdecl HalpDispatchInterrupt(VOID);
582 PHAL_SW_INTERRUPT_HANDLER __cdecl HalpDispatchInterrupt2(VOID);
583 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
584 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
585
586 /* profil.c */
587 extern BOOLEAN HalpProfilingStopped;
588
589 /* timer.c */
590 INIT_FUNCTION VOID NTAPI HalpInitializeClock(VOID);
591 VOID __cdecl HalpClockInterrupt(VOID);
592 VOID __cdecl HalpProfileInterrupt(VOID);
593
594 VOID
595 NTAPI
596 HalpCalibrateStallExecution(VOID);
597
598 /* pci.c */
599 VOID HalpInitPciBus (VOID);
600
601 /* dma.c */
602 INIT_FUNCTION VOID HalpInitDma (VOID);
603
604 /* Non-generic initialization */
605 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
606 VOID HalpInitPhase1(VOID);
607
608 VOID
609 NTAPI
610 HalpFlushTLB(VOID);
611
612 //
613 // KD Support
614 //
615 VOID
616 NTAPI
617 HalpCheckPowerButton(
618 VOID
619 );
620
621 INIT_FUNCTION
622 VOID
623 NTAPI
624 HalpRegisterKdSupportFunctions(
625 VOID
626 );
627
628 INIT_FUNCTION
629 NTSTATUS
630 NTAPI
631 HalpSetupPciDeviceForDebugging(
632 IN PVOID LoaderBlock,
633 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
634 );
635
636 INIT_FUNCTION
637 NTSTATUS
638 NTAPI
639 HalpReleasePciDeviceForDebugging(
640 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
641 );
642
643 //
644 // Memory routines
645 //
646 ULONG64
647 NTAPI
648 HalpAllocPhysicalMemory(
649 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
650 IN ULONG64 MaxAddress,
651 IN PFN_NUMBER PageCount,
652 IN BOOLEAN Aligned
653 );
654
655 PVOID
656 NTAPI
657 HalpMapPhysicalMemory64Vista(
658 IN PHYSICAL_ADDRESS PhysicalAddress,
659 IN PFN_COUNT PageCount,
660 IN BOOLEAN FlushCurrentTLB
661 );
662
663 VOID
664 NTAPI
665 HalpUnmapVirtualAddressVista(
666 IN PVOID VirtualAddress,
667 IN PFN_COUNT NumberPages,
668 IN BOOLEAN FlushCurrentTLB
669 );
670
671 PVOID
672 NTAPI
673 HalpMapPhysicalMemory64(
674 IN PHYSICAL_ADDRESS PhysicalAddress,
675 IN PFN_COUNT PageCount
676 );
677
678 VOID
679 NTAPI
680 HalpUnmapVirtualAddress(
681 IN PVOID VirtualAddress,
682 IN PFN_COUNT NumberPages
683 );
684
685 /* sysinfo.c */
686 NTSTATUS
687 NTAPI
688 HaliQuerySystemInformation(
689 IN HAL_QUERY_INFORMATION_CLASS InformationClass,
690 IN ULONG BufferSize,
691 IN OUT PVOID Buffer,
692 OUT PULONG ReturnedLength
693 );
694
695 NTSTATUS
696 NTAPI
697 HaliSetSystemInformation(
698 IN HAL_SET_INFORMATION_CLASS InformationClass,
699 IN ULONG BufferSize,
700 IN OUT PVOID Buffer
701 );
702
703 //
704 // BIOS Routines
705 //
706 BOOLEAN
707 NTAPI
708 HalpBiosDisplayReset(
709 VOID
710 );
711
712 VOID
713 FASTCALL
714 HalpExitToV86(
715 PKTRAP_FRAME TrapFrame
716 );
717
718 VOID
719 __cdecl
720 HalpRealModeStart(
721 VOID
722 );
723
724 //
725 // Processor Halt Routine
726 //
727 VOID
728 NTAPI
729 HaliHaltSystem(
730 VOID
731 );
732
733 //
734 // CMOS Routines
735 //
736 INIT_FUNCTION
737 VOID
738 NTAPI
739 HalpInitializeCmos(
740 VOID
741 );
742
743 UCHAR
744 NTAPI
745 HalpReadCmos(
746 IN UCHAR Reg
747 );
748
749 VOID
750 NTAPI
751 HalpWriteCmos(
752 IN UCHAR Reg,
753 IN UCHAR Value
754 );
755
756 //
757 // Spinlock for protecting CMOS access
758 //
759 VOID
760 NTAPI
761 HalpAcquireCmosSpinLock(
762 VOID
763 );
764
765 VOID
766 NTAPI
767 HalpReleaseCmosSpinLock(
768 VOID
769 );
770
771 VOID
772 NTAPI
773 HalpInitializeLegacyPICs(
774 VOID
775 );
776
777 NTSTATUS
778 NTAPI
779 HalpOpenRegistryKey(
780 IN PHANDLE KeyHandle,
781 IN HANDLE RootKey,
782 IN PUNICODE_STRING KeyName,
783 IN ACCESS_MASK DesiredAccess,
784 IN BOOLEAN Create
785 );
786
787 INIT_FUNCTION
788 VOID
789 NTAPI
790 HalpGetNMICrashFlag(
791 VOID
792 );
793
794 INIT_FUNCTION
795 BOOLEAN
796 NTAPI
797 HalpGetDebugPortTable(
798 VOID
799 );
800
801 INIT_FUNCTION
802 VOID
803 NTAPI
804 HalpReportSerialNumber(
805 VOID
806 );
807
808 INIT_FUNCTION
809 NTSTATUS
810 NTAPI
811 HalpMarkAcpiHal(
812 VOID
813 );
814
815 INIT_FUNCTION
816 VOID
817 NTAPI
818 HalpBuildAddressMap(
819 VOID
820 );
821
822 INIT_FUNCTION
823 VOID
824 NTAPI
825 HalpReportResourceUsage(
826 IN PUNICODE_STRING HalName,
827 IN INTERFACE_TYPE InterfaceType
828 );
829
830 INIT_FUNCTION
831 ULONG
832 NTAPI
833 HalpIs16BitPortDecodeSupported(
834 VOID
835 );
836
837 NTSTATUS
838 NTAPI
839 HalpQueryAcpiResourceRequirements(
840 OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
841 );
842
843 VOID
844 FASTCALL
845 KeUpdateSystemTime(
846 IN PKTRAP_FRAME TrapFrame,
847 IN ULONG Increment,
848 IN KIRQL OldIrql
849 );
850
851 INIT_FUNCTION
852 VOID
853 NTAPI
854 HalpInitBusHandlers(
855 VOID
856 );
857
858 NTSTATUS
859 NTAPI
860 HaliInitPnpDriver(
861 VOID
862 );
863
864 INIT_FUNCTION
865 VOID
866 NTAPI
867 HalpDebugPciDumpBus(
868 IN ULONG i,
869 IN ULONG j,
870 IN ULONG k,
871 IN PPCI_COMMON_CONFIG PciData
872 );
873
874 VOID
875 NTAPI
876 HalpInitProcessor(
877 IN ULONG ProcessorNumber,
878 IN PLOADER_PARAMETER_BLOCK LoaderBlock
879 );
880
881 #ifdef _M_AMD64
882
883 VOID
884 NTAPI
885 HalInitializeBios(
886 _In_ ULONG Unknown,
887 _In_ PLOADER_PARAMETER_BLOCK LoaderBlock
888 );
889
890 #define KfLowerIrql KeLowerIrql
891 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
892 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
893 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
894 #ifndef CONFIG_SMP
895 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
896 #define KiAcquireSpinLock(SpinLock)
897 #define KiReleaseSpinLock(SpinLock)
898 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
899 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
900 #endif // !CONFIG_SMP
901 #endif // _M_AMD64
902
903 extern BOOLEAN HalpNMIInProgress;
904
905 extern ADDRESS_USAGE HalpDefaultIoSpace;
906
907 extern KSPIN_LOCK HalpSystemHardwareLock;
908
909 extern PADDRESS_USAGE HalpAddressUsageList;
910
911 extern LARGE_INTEGER HalpPerfCounter;
912
913 extern KAFFINITY HalpActiveProcessors;
914
915 extern BOOLEAN HalDisableFirmwareMapper;
916 extern PWCHAR HalHardwareIdString;
917 extern PWCHAR HalName;
918
919 extern KAFFINITY HalpDefaultInterruptAffinity;
920
921 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
922
923 extern const USHORT HalpBuildType;