hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7
   8 #ifdef _MSC_VER
   9 #define REGISTERCALL FASTCALL
  10 #else
  11 #define REGISTERCALL __attribute__((regparm(3)))
  12 #endif
  13
  14 typedef struct _HAL_BIOS_FRAME
  15 {
  16     ULONG SegSs;
  17     ULONG Esp;
  18     ULONG EFlags;
  19     ULONG SegCs;
  20     ULONG Eip;
  21     PKTRAP_FRAME TrapFrame;
  22     ULONG CsLimit;
  23     ULONG CsBase;
  24     ULONG CsFlags;
  25     ULONG SsLimit;
  26     ULONG SsBase;
  27     ULONG SsFlags;
  28     ULONG Prefix;
  29 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  30
  31 typedef
  32 VOID
  33 (*PHAL_SW_INTERRUPT_HANDLER)(
  34     VOID
  35 );
  36
  37 typedef
  38 VOID
  39 ATTRIB_NORETURN
  40 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  41     IN PKTRAP_FRAME TrapFrame
  42 );
  43
  44 #define HAL_APC_REQUEST         0
  45 #define HAL_DPC_REQUEST         1
  46
  47 /* CMOS Registers and Ports */
  48 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  49 #define CMOS_DATA_PORT          (PUCHAR)0x71
  50 #define RTC_REGISTER_A          0x0A
  51 #define   RTC_REG_A_UIP         0x80
  52 #define RTC_REGISTER_B          0x0B
  53 #define   RTC_REG_B_PI          0x40
  54 #define RTC_REGISTER_C          0x0C
  55 #define RTC_REGISTER_D          0x0D
  56 #define RTC_REGISTER_CENTURY    0x32
  57
  58 /* Usage flags */
  59 #define IDT_REGISTERED          0x01
  60 #define IDT_LATCHED             0x02
  61 #define IDT_READ_ONLY           0x04
  62 #define IDT_INTERNAL            0x11
  63 #define IDT_DEVICE              0x21
  64
  65 /* Conversion functions */
  66 #define BCD_INT(bcd)            \
  67     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  68 #define INT_BCD(int)            \
  69     (UCHAR)(((int / 10) << 4) + (int % 10))
  70
  71 //
  72 // BIOS Interrupts
  73 //
  74 #define VIDEO_SERVICES   0x10
  75
  76 //
  77 // Operations for INT 10h (in AH)
  78 //
  79 #define SET_VIDEO_MODE   0x00
  80
  81 //
  82 // Video Modes for INT10h AH=00 (in AL)
  83 //
  84 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  85
  86 //
  87 // Commonly stated as being 1.19318MHz
  88 //
  89 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
  90 // P. 471
  91 //
  92 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
  93 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
  94 //
  95 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
  96 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
  97 // infinite series) and divides it by three, one obtains 1.19318167.
  98 //
  99 // It may be that the original NT HAL source code introduced a typo and turned
 100 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 101 // number is quite long.
 102 //
 103 #define PIT_FREQUENCY 1193182
 104
 105 //
 106 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 107 //
 108 #define TIMER_CHANNEL0_DATA_PORT 0x40
 109 #define TIMER_CHANNEL1_DATA_PORT 0x41
 110 #define TIMER_CHANNEL2_DATA_PORT 0x42
 111 #define TIMER_CONTROL_PORT       0x43
 112
 113 //
 114 // Mode 0 - Interrupt On Terminal Count
 115 // Mode 1 - Hardware Re-triggerable One-Shot
 116 // Mode 2 - Rate Generator
 117 // Mode 3 - Square Wave Generator
 118 // Mode 4 - Software Triggered Strobe
 119 // Mode 5 - Hardware Triggered Strobe
 120 //
 121 typedef enum _TIMER_OPERATING_MODES
 122 {
 123     PitOperatingMode0,
 124     PitOperatingMode1,
 125     PitOperatingMode2,
 126     PitOperatingMode3,
 127     PitOperatingMode4,
 128     PitOperatingMode5,
 129     PitOperatingMode2Reserved,
 130     PitOperatingMode5Reserved
 131 } TIMER_OPERATING_MODES;
 132
 133 typedef enum _TIMER_ACCESS_MODES
 134 {
 135     PitAccessModeCounterLatch,
 136     PitAccessModeLow,
 137     PitAccessModeHigh,
 138     PitAccessModeLowHigh
 139 } TIMER_ACCESS_MODES;
 140
 141 typedef enum _TIMER_CHANNELS
 142 {
 143     PitChannel0,
 144     PitChannel1,
 145     PitChannel2,
 146     PitReadBack
 147 } TIMER_CHANNELS;
 148
 149 typedef union _TIMER_CONTROL_PORT_REGISTER
 150 {
 151     struct
 152     {
 153         UCHAR BcdMode:1;
 154         TIMER_OPERATING_MODES OperatingMode:3;
 155         TIMER_ACCESS_MODES AccessMode:2;
 156         TIMER_CHANNELS Channel:2;
 157     };
 158     UCHAR Bits;
 159 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 160
 161 //
 162 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 163 // P. 400
 164 //
 165 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 166 //
 167 #define SYSTEM_CONTROL_PORT_A   0x92
 168 #define SYSTEM_CONTROL_PORT_B   0x61
 169 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 170 {
 171     struct
 172     {
 173         UCHAR Timer2GateToSpeaker:1;
 174         UCHAR SpeakerDataEnable:1;
 175         UCHAR ParityCheckEnable:1;
 176         UCHAR ChannelCheckEnable:1;
 177         UCHAR RefreshRequest:1;
 178         UCHAR Timer2Output:1;
 179         UCHAR ChannelCheck:1;
 180         UCHAR ParityCheck:1;
 181     };
 182     UCHAR Bits;
 183 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 184
 185 //
 186 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 187 // P. 396, 397
 188 //
 189 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 190 //
 191 #define PIC1_CONTROL_PORT      0x20
 192 #define PIC1_DATA_PORT         0x21
 193 #define PIC2_CONTROL_PORT      0xA0
 194 #define PIC2_DATA_PORT         0xA1
 195
 196 //
 197 // Definitions for ICW/OCW Bits
 198 //
 199 typedef enum _I8259_ICW1_OPERATING_MODE
 200 {
 201     Cascade,
 202     Single
 203 } I8259_ICW1_OPERATING_MODE;
 204
 205 typedef enum _I8259_ICW1_INTERRUPT_MODE
 206 {
 207     EdgeTriggered,
 208     LevelTriggered
 209 } I8259_ICW1_INTERRUPT_MODE;
 210
 211 typedef enum _I8259_ICW1_INTERVAL
 212 {
 213     Interval8,
 214     Interval4
 215 } I8259_ICW1_INTERVAL;
 216
 217 typedef enum _I8259_ICW4_SYSTEM_MODE
 218 {
 219     Mcs8085Mode,
 220     New8086Mode
 221 } I8259_ICW4_SYSTEM_MODE;
 222
 223 typedef enum _I8259_ICW4_EOI_MODE
 224 {
 225     NormalEoi,
 226     AutomaticEoi
 227 } I8259_ICW4_EOI_MODE;
 228
 229 typedef enum _I8259_ICW4_BUFFERED_MODE
 230 {
 231     NonBuffered,
 232     NonBuffered2,
 233     BufferedSlave,
 234     BufferedMaster
 235 } I8259_ICW4_BUFFERED_MODE;
 236
 237 typedef enum _I8259_READ_REQUEST
 238 {
 239     InvalidRequest,
 240     InvalidRequest2,
 241     ReadIdr,
 242     ReadIsr
 243 } I8259_READ_REQUEST;
 244
 245 typedef enum _I8259_EOI_MODE
 246 {
 247     RotateAutoEoiClear,
 248     NonSpecificEoi,
 249     InvalidEoiMode,
 250     SpecificEoi,
 251     RotateAutoEoiSet,
 252     RotateNonSpecific,
 253     SetPriority,
 254     RotateSpecific
 255 } I8259_EOI_MODE;
 256
 257 //
 258 // Definitions for ICW Registers
 259 //
 260 typedef union _I8259_ICW1
 261 {
 262     struct
 263     {
 264         UCHAR NeedIcw4:1;
 265         I8259_ICW1_OPERATING_MODE OperatingMode:1;
 266         I8259_ICW1_INTERVAL Interval:1;
 267         I8259_ICW1_INTERRUPT_MODE InterruptMode:1;
 268         UCHAR Init:1;
 269         UCHAR InterruptVectorAddress:3;
 270     };
 271     UCHAR Bits;
 272 } I8259_ICW1, *PI8259_ICW1;
 273
 274 typedef union _I8259_ICW2
 275 {
 276     struct
 277     {
 278         UCHAR Sbz:3;
 279         UCHAR InterruptVector:5;
 280     };
 281     UCHAR Bits;
 282 } I8259_ICW2, *PI8259_ICW2;
 283
 284 typedef union _I8259_ICW3
 285 {
 286     union
 287     {
 288         struct
 289         {
 290             UCHAR SlaveIrq0:1;
 291             UCHAR SlaveIrq1:1;
 292             UCHAR SlaveIrq2:1;
 293             UCHAR SlaveIrq3:1;
 294             UCHAR SlaveIrq4:1;
 295             UCHAR SlaveIrq5:1;
 296             UCHAR SlaveIrq6:1;
 297             UCHAR SlaveIrq7:1;
 298         };
 299         struct
 300         {
 301             UCHAR SlaveId:3;
 302             UCHAR Reserved:5;
 303         };
 304     };
 305     UCHAR Bits;
 306 } I8259_ICW3, *PI8259_ICW3;
 307
 308 typedef union _I8259_ICW4
 309 {
 310     struct
 311     {
 312         I8259_ICW4_SYSTEM_MODE SystemMode:1;
 313         I8259_ICW4_EOI_MODE EoiMode:1;
 314         I8259_ICW4_BUFFERED_MODE BufferedMode:2;
 315         UCHAR SpecialFullyNestedMode:1;
 316         UCHAR Reserved:3;
 317     };
 318     UCHAR Bits;
 319 } I8259_ICW4, *PI8259_ICW4;
 320
 321 typedef union _I8259_OCW2
 322 {
 323     struct
 324     {
 325         UCHAR IrqNumber:3;
 326         UCHAR Sbz:2;
 327         I8259_EOI_MODE EoiMode:3;
 328     };
 329     UCHAR Bits;
 330 } I8259_OCW2, *PI8259_OCW2;
 331
 332 typedef union _I8259_OCW3
 333 {
 334     struct
 335     {
 336         I8259_READ_REQUEST ReadRequest:2;
 337         UCHAR PollCommand:1;
 338         UCHAR Sbo:1;
 339         UCHAR Sbz:1;
 340         UCHAR SpecialMaskMode:2;
 341         UCHAR Reserved:1;
 342     };
 343     UCHAR Bits;
 344 } I8259_OCW3, *PI8259_OCW3;
 345
 346 typedef union _I8259_ISR
 347 {
 348     union
 349     {
 350         struct
 351         {
 352             UCHAR Irq0:1;
 353             UCHAR Irq1:1;
 354             UCHAR Irq2:1;
 355             UCHAR Irq3:1;
 356             UCHAR Irq4:1;
 357             UCHAR Irq5:1;
 358             UCHAR Irq6:1;
 359             UCHAR Irq7:1;
 360         };
 361     };
 362     UCHAR Bits;
 363 } I8259_ISR, *PI8259_ISR;
 364
 365 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 366
 367 //
 368 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 369 // P. 34, 35
 370 //
 371 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 372 //
 373 #define EISA_ELCR_MASTER       0x4D0
 374 #define EISA_ELCR_SLAVE        0x4D1
 375
 376 typedef union _EISA_ELCR
 377 {
 378     struct
 379     {
 380         struct
 381         {
 382             UCHAR Irq0Level:1;
 383             UCHAR Irq1Level:1;
 384             UCHAR Irq2Level:1;
 385             UCHAR Irq3Level:1;
 386             UCHAR Irq4Level:1;
 387             UCHAR Irq5Level:1;
 388             UCHAR Irq6Level:1;
 389             UCHAR Irq7Level:1;
 390         } Master;
 391         struct
 392         {
 393             UCHAR Irq8Level:1;
 394             UCHAR Irq9Level:1;
 395             UCHAR Irq10Level:1;
 396             UCHAR Irq11Level:1;
 397             UCHAR Irq12Level:1;
 398             UCHAR Irq13Level:1;
 399             UCHAR Irq14Level:1;
 400             UCHAR Irq15Level:1;
 401         } Slave;
 402     };
 403     USHORT Bits;
 404 } EISA_ELCR, *PEISA_ELCR;
 405
 406 typedef struct _PIC_MASK
 407 {
 408     union
 409     {
 410         struct
 411         {
 412             UCHAR Master;
 413             UCHAR Slave;
 414         };
 415         USHORT Both;
 416     };
 417 } PIC_MASK, *PPIC_MASK;
 418
 419 typedef
 420 BOOLEAN
 421 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
 422     IN KIRQL Irql,
 423     IN ULONG Irq,
 424     OUT PKIRQL OldIrql
 425 );
 426
 427 BOOLEAN
 428 REGISTERCALL
 429 HalpDismissIrqGeneric(
 430     IN KIRQL Irql,
 431     IN ULONG Irq,
 432     OUT PKIRQL OldIrql
 433 );
 434
 435 BOOLEAN
 436 REGISTERCALL
 437 HalpDismissIrq15(
 438     IN KIRQL Irql,
 439     IN ULONG Irq,
 440     OUT PKIRQL OldIrql
 441 );
 442
 443 BOOLEAN
 444 REGISTERCALL
 445 HalpDismissIrq13(
 446     IN KIRQL Irql,
 447     IN ULONG Irq,
 448     OUT PKIRQL OldIrql
 449 );
 450
 451 BOOLEAN
 452 REGISTERCALL
 453 HalpDismissIrq07(
 454     IN KIRQL Irql,
 455     IN ULONG Irq,
 456     OUT PKIRQL OldIrql
 457 );
 458
 459 BOOLEAN
 460 REGISTERCALL
 461 HalpDismissIrqLevel(
 462     IN KIRQL Irql,
 463     IN ULONG Irq,
 464     OUT PKIRQL OldIrql
 465 );
 466
 467 BOOLEAN
 468 REGISTERCALL
 469 HalpDismissIrq15Level(
 470     IN KIRQL Irql,
 471     IN ULONG Irq,
 472     OUT PKIRQL OldIrql
 473 );
 474
 475 BOOLEAN
 476 REGISTERCALL
 477 HalpDismissIrq13Level(
 478     IN KIRQL Irql,
 479     IN ULONG Irq,
 480     OUT PKIRQL OldIrql
 481 );
 482
 483 BOOLEAN
 484 REGISTERCALL
 485 HalpDismissIrq07Level(
 486     IN KIRQL Irql,
 487     IN ULONG Irq,
 488     OUT PKIRQL OldIrql
 489 );
 490
 491 VOID
 492 HalpHardwareInterruptLevel(
 493     VOID
 494 );
 495
 496 //
 497 // Hack Flags
 498 //
 499 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 500 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 501 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 502
 503 //
 504 // Feature flags
 505 //
 506 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 507
 508 //
 509 // Match Flags
 510 //
 511 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 512 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 513 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 514
 515 //
 516 // Mm PTE/PDE to Hal PTE/PDE
 517 //
 518 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 519 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 520
 521 typedef struct _IDTUsageFlags
 522 {
 523     UCHAR Flags;
 524 } IDTUsageFlags;
 525
 526 typedef struct
 527 {
 528     KIRQL Irql;
 529     UCHAR BusReleativeVector;
 530 } IDTUsage;
 531
 532 typedef struct _HalAddressUsage
 533 {
 534     struct _HalAddressUsage *Next;
 535     CM_RESOURCE_TYPE Type;
 536     UCHAR Flags;
 537     struct
 538     {
 539         ULONG Start;
 540         ULONG Length;
 541     } Element[];
 542 } ADDRESS_USAGE, *PADDRESS_USAGE;
 543
 544 /* adapter.c */
 545 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 546
 547 /* sysinfo.c */
 548 VOID
 549 NTAPI
 550 HalpRegisterVector(IN UCHAR Flags,
 551                    IN ULONG BusVector,
 552                    IN ULONG SystemVector,
 553                    IN KIRQL Irql);
 554
 555 VOID
 556 NTAPI
 557 HalpEnableInterruptHandler(IN UCHAR Flags,
 558                            IN ULONG BusVector,
 559                            IN ULONG SystemVector,
 560                            IN KIRQL Irql,
 561                            IN PVOID Handler,
 562                            IN KINTERRUPT_MODE Mode);
 563
 564 /* pic.c */
 565 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 566 VOID HalpApcInterrupt(VOID);
 567 VOID HalpDispatchInterrupt(VOID);
 568 VOID HalpDispatchInterrupt2(VOID);
 569 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 570 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 571
 572 /* timer.c */
 573 VOID NTAPI HalpInitializeClock(VOID);
 574 VOID HalpClockInterrupt(VOID);
 575 VOID HalpProfileInterrupt(VOID);
 576
 577 VOID
 578 NTAPI
 579 HalpCalibrateStallExecution(VOID);
 580
 581 /* pci.c */
 582 VOID HalpInitPciBus (VOID);
 583
 584 /* dma.c */
 585 VOID HalpInitDma (VOID);
 586
 587 /* Non-generic initialization */
 588 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 589 VOID HalpInitPhase1(VOID);
 590
 591 VOID
 592 NTAPI
 593 HalpFlushTLB(VOID);
 594
 595 //
 596 // KD Support
 597 //
 598 VOID
 599 NTAPI
 600 HalpCheckPowerButton(
 601     VOID
 602 );
 603
 604 VOID
 605 NTAPI
 606 HalpRegisterKdSupportFunctions(
 607     VOID
 608 );
 609
 610 NTSTATUS
 611 NTAPI
 612 HalpSetupPciDeviceForDebugging(
 613     IN PVOID LoaderBlock,
 614     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 615 );
 616
 617 NTSTATUS
 618 NTAPI
 619 HalpReleasePciDeviceForDebugging(
 620     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 621 );
 622
 623 //
 624 // Memory routines
 625 //
 626 PVOID
 627 NTAPI
 628 HalpMapPhysicalMemory64(
 629     IN PHYSICAL_ADDRESS PhysicalAddress,
 630     IN ULONG NumberPage
 631 );
 632
 633 VOID
 634 NTAPI
 635 HalpUnmapVirtualAddress(
 636     IN PVOID VirtualAddress,
 637     IN ULONG NumberPages
 638 );
 639
 640 /* sysinfo.c */
 641 NTSTATUS
 642 NTAPI
 643 HaliQuerySystemInformation(
 644     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 645     IN ULONG BufferSize,
 646     IN OUT PVOID Buffer,
 647     OUT PULONG ReturnedLength
 648 );
 649
 650 NTSTATUS
 651 NTAPI
 652 HaliSetSystemInformation(
 653     IN HAL_SET_INFORMATION_CLASS InformationClass,
 654     IN ULONG BufferSize,
 655     IN OUT PVOID Buffer
 656 );
 657
 658 //
 659 // BIOS Routines
 660 //
 661 BOOLEAN
 662 NTAPI
 663 HalpBiosDisplayReset(
 664     VOID
 665 );
 666
 667 VOID
 668 FASTCALL
 669 HalpExitToV86(
 670     PKTRAP_FRAME TrapFrame
 671 );
 672
 673 VOID
 674 DECLSPEC_NORETURN
 675 HalpRealModeStart(
 676     VOID
 677 );
 678
 679 //
 680 // Processor Halt Routine
 681 //
 682 VOID
 683 NTAPI
 684 HaliHaltSystem(
 685     VOID
 686 );
 687
 688 //
 689 // CMOS Routines
 690 //
 691 VOID
 692 NTAPI
 693 HalpInitializeCmos(
 694     VOID
 695 );
 696
 697 UCHAR
 698 NTAPI
 699 HalpReadCmos(
 700     IN UCHAR Reg
 701 );
 702
 703 VOID
 704 NTAPI
 705 HalpWriteCmos(
 706     IN UCHAR Reg,
 707     IN UCHAR Value
 708 );
 709
 710 //
 711 // Spinlock for protecting CMOS access
 712 //
 713 VOID
 714 NTAPI
 715 HalpAcquireSystemHardwareSpinLock(
 716     VOID
 717 );
 718
 719 VOID
 720 NTAPI
 721 HalpReleaseCmosSpinLock(
 722     VOID
 723 );
 724
 725 ULONG
 726 NTAPI
 727 HalpAllocPhysicalMemory(
 728     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 729     IN ULONG MaxAddress,
 730     IN ULONG PageCount,
 731     IN BOOLEAN Aligned
 732 );
 733
 734 PVOID
 735 NTAPI
 736 HalpMapPhysicalMemory64(
 737     IN PHYSICAL_ADDRESS PhysicalAddress,
 738     IN ULONG PageCount
 739 );
 740
 741 NTSTATUS
 742 NTAPI
 743 HalpOpenRegistryKey(
 744     IN PHANDLE KeyHandle,
 745     IN HANDLE RootKey,
 746     IN PUNICODE_STRING KeyName,
 747     IN ACCESS_MASK DesiredAccess,
 748     IN BOOLEAN Create
 749 );
 750
 751 VOID
 752 NTAPI
 753 HalpGetNMICrashFlag(
 754     VOID
 755 );
 756
 757 BOOLEAN
 758 NTAPI
 759 HalpGetDebugPortTable(
 760     VOID
 761 );
 762
 763 VOID
 764 NTAPI
 765 HalpReportSerialNumber(
 766     VOID
 767 );
 768
 769 NTSTATUS
 770 NTAPI
 771 HalpMarkAcpiHal(
 772     VOID
 773 );
 774
 775 VOID
 776 NTAPI
 777 HalpBuildAddressMap(
 778     VOID
 779 );
 780
 781 VOID
 782 NTAPI
 783 HalpReportResourceUsage(
 784     IN PUNICODE_STRING HalName,
 785     IN INTERFACE_TYPE InterfaceType
 786 );
 787
 788 ULONG
 789 NTAPI
 790 HalpIs16BitPortDecodeSupported(
 791     VOID
 792 );
 793
 794 NTSTATUS
 795 NTAPI
 796 HalpQueryAcpiResourceRequirements(
 797     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 798 );
 799
 800 VOID
 801 FASTCALL
 802 KeUpdateSystemTime(
 803     IN PKTRAP_FRAME TrapFrame,
 804     IN ULONG Increment,
 805     IN KIRQL OldIrql
 806 );
 807
 808 VOID
 809 NTAPI
 810 HalpInitBusHandlers(
 811     VOID
 812 );
 813
 814 NTSTATUS
 815 NTAPI
 816 HaliInitPnpDriver(
 817     VOID
 818 );
 819
 820 VOID
 821 NTAPI
 822 HalpDebugPciDumpBus(
 823     IN ULONG i,
 824     IN ULONG j,
 825     IN ULONG k,
 826     IN PPCI_COMMON_CONFIG PciData
 827 );
 828
 829 #ifdef _M_AMD64
 830 #define KfLowerIrql KeLowerIrql
 831 #ifndef CONFIG_SMP
 832 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 833 #define KiAcquireSpinLock(SpinLock)
 834 #define KiReleaseSpinLock(SpinLock)
 835 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 836 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 837 #endif // !CONFIG_SMP
 838 #endif // _M_AMD64
 839
 840 extern BOOLEAN HalpNMIInProgress;
 841
 842 extern ADDRESS_USAGE HalpDefaultIoSpace;
 843
 844 extern KSPIN_LOCK HalpSystemHardwareLock;
 845
 846 extern PADDRESS_USAGE HalpAddressUsageList;
 847
 848 extern LARGE_INTEGER HalpPerfCounter;
 849
 850 extern KAFFINITY HalpActiveProcessors;
 851
 852 extern BOOLEAN HalDisableFirmwareMapper;
 853 extern PWCHAR HalHardwareIdString;
 854 extern PWCHAR HalName;
 855
 856 extern KAFFINITY HalpDefaultInterruptAffinity;
 857
 858 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR];
 859