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[reactos.git] / hal / halx86 / include / halp.h
1 /*
2 *
3 */
4
5 #pragma once
6
7 #define PLACE_IN_SECTION(s) __attribute__((section (s)))
8 #ifdef __GNUC__
9 #define INIT_FUNCTION PLACE_IN_SECTION("init")
10 #define PAGE_LOCKED_FUNCTION PLACE_IN_SECTION("pagelk")
11 #define PAGE_UNLOCKED_FUNCTION PLACE_IN_SECTION("pagepo")
12 #else
13 #define INIT_FUNCTION
14 #define PAGE_LOCKED_FUNCTION
15 #define PAGE_UNLOCKED_FUNCTION
16 #endif
17
18 #ifdef _MSC_VER
19 #define REGISTERCALL FASTCALL
20 #else
21 #define REGISTERCALL __attribute__((regparm(3)))
22 #endif
23
24 typedef struct _HAL_BIOS_FRAME
25 {
26 ULONG SegSs;
27 ULONG Esp;
28 ULONG EFlags;
29 ULONG SegCs;
30 ULONG Eip;
31 PKTRAP_FRAME TrapFrame;
32 ULONG CsLimit;
33 ULONG CsBase;
34 ULONG CsFlags;
35 ULONG SsLimit;
36 ULONG SsBase;
37 ULONG SsFlags;
38 ULONG Prefix;
39 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
40
41 typedef
42 VOID
43 (*PHAL_SW_INTERRUPT_HANDLER)(
44 VOID
45 );
46
47 typedef
48 VOID
49 ATTRIB_NORETURN
50 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
51 IN PKTRAP_FRAME TrapFrame
52 );
53
54 #define HAL_APC_REQUEST 0
55 #define HAL_DPC_REQUEST 1
56
57 /* CMOS Registers and Ports */
58 #define CMOS_CONTROL_PORT (PUCHAR)0x70
59 #define CMOS_DATA_PORT (PUCHAR)0x71
60 #define RTC_REGISTER_A 0x0A
61 #define RTC_REG_A_UIP 0x80
62 #define RTC_REGISTER_B 0x0B
63 #define RTC_REG_B_PI 0x40
64 #define RTC_REGISTER_C 0x0C
65 #define RTC_REGISTER_D 0x0D
66 #define RTC_REGISTER_CENTURY 0x32
67
68 /* Usage flags */
69 #define IDT_REGISTERED 0x01
70 #define IDT_LATCHED 0x02
71 #define IDT_READ_ONLY 0x04
72 #define IDT_INTERNAL 0x11
73 #define IDT_DEVICE 0x21
74
75 /* Conversion functions */
76 #define BCD_INT(bcd) \
77 (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
78 #define INT_BCD(int) \
79 (UCHAR)(((int / 10) << 4) + (int % 10))
80
81 //
82 // BIOS Interrupts
83 //
84 #define VIDEO_SERVICES 0x10
85
86 //
87 // Operations for INT 10h (in AH)
88 //
89 #define SET_VIDEO_MODE 0x00
90
91 //
92 // Video Modes for INT10h AH=00 (in AL)
93 //
94 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
95
96 //
97 // Commonly stated as being 1.19318MHz
98 //
99 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
100 // P. 471
101 //
102 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
103 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
104 //
105 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
106 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
107 // infinite series) and divides it by three, one obtains 1.19318167.
108 //
109 // It may be that the original NT HAL source code introduced a typo and turned
110 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
111 // number is quite long.
112 //
113 #define PIT_FREQUENCY 1193182
114
115 //
116 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
117 //
118 #define TIMER_CHANNEL0_DATA_PORT 0x40
119 #define TIMER_CHANNEL1_DATA_PORT 0x41
120 #define TIMER_CHANNEL2_DATA_PORT 0x42
121 #define TIMER_CONTROL_PORT 0x43
122
123 //
124 // Mode 0 - Interrupt On Terminal Count
125 // Mode 1 - Hardware Re-triggerable One-Shot
126 // Mode 2 - Rate Generator
127 // Mode 3 - Square Wave Generator
128 // Mode 4 - Software Triggered Strobe
129 // Mode 5 - Hardware Triggered Strobe
130 //
131 typedef enum _TIMER_OPERATING_MODES
132 {
133 PitOperatingMode0,
134 PitOperatingMode1,
135 PitOperatingMode2,
136 PitOperatingMode3,
137 PitOperatingMode4,
138 PitOperatingMode5,
139 PitOperatingMode2Reserved,
140 PitOperatingMode5Reserved
141 } TIMER_OPERATING_MODES;
142
143 typedef enum _TIMER_ACCESS_MODES
144 {
145 PitAccessModeCounterLatch,
146 PitAccessModeLow,
147 PitAccessModeHigh,
148 PitAccessModeLowHigh
149 } TIMER_ACCESS_MODES;
150
151 typedef enum _TIMER_CHANNELS
152 {
153 PitChannel0,
154 PitChannel1,
155 PitChannel2,
156 PitReadBack
157 } TIMER_CHANNELS;
158
159 typedef union _TIMER_CONTROL_PORT_REGISTER
160 {
161 struct
162 {
163 UCHAR BcdMode:1;
164 TIMER_OPERATING_MODES OperatingMode:3;
165 TIMER_ACCESS_MODES AccessMode:2;
166 TIMER_CHANNELS Channel:2;
167 };
168 UCHAR Bits;
169 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
170
171 //
172 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
173 // P. 400
174 //
175 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
176 //
177 #define SYSTEM_CONTROL_PORT_A 0x92
178 #define SYSTEM_CONTROL_PORT_B 0x61
179 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
180 {
181 struct
182 {
183 UCHAR Timer2GateToSpeaker:1;
184 UCHAR SpeakerDataEnable:1;
185 UCHAR ParityCheckEnable:1;
186 UCHAR ChannelCheckEnable:1;
187 UCHAR RefreshRequest:1;
188 UCHAR Timer2Output:1;
189 UCHAR ChannelCheck:1;
190 UCHAR ParityCheck:1;
191 };
192 UCHAR Bits;
193 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
194
195 //
196 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
197 // P. 396, 397
198 //
199 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
200 //
201 #define PIC1_CONTROL_PORT 0x20
202 #define PIC1_DATA_PORT 0x21
203 #define PIC2_CONTROL_PORT 0xA0
204 #define PIC2_DATA_PORT 0xA1
205
206 //
207 // Definitions for ICW/OCW Bits
208 //
209 typedef enum _I8259_ICW1_OPERATING_MODE
210 {
211 Cascade,
212 Single
213 } I8259_ICW1_OPERATING_MODE;
214
215 typedef enum _I8259_ICW1_INTERRUPT_MODE
216 {
217 EdgeTriggered,
218 LevelTriggered
219 } I8259_ICW1_INTERRUPT_MODE;
220
221 typedef enum _I8259_ICW1_INTERVAL
222 {
223 Interval8,
224 Interval4
225 } I8259_ICW1_INTERVAL;
226
227 typedef enum _I8259_ICW4_SYSTEM_MODE
228 {
229 Mcs8085Mode,
230 New8086Mode
231 } I8259_ICW4_SYSTEM_MODE;
232
233 typedef enum _I8259_ICW4_EOI_MODE
234 {
235 NormalEoi,
236 AutomaticEoi
237 } I8259_ICW4_EOI_MODE;
238
239 typedef enum _I8259_ICW4_BUFFERED_MODE
240 {
241 NonBuffered,
242 NonBuffered2,
243 BufferedSlave,
244 BufferedMaster
245 } I8259_ICW4_BUFFERED_MODE;
246
247 typedef enum _I8259_READ_REQUEST
248 {
249 InvalidRequest,
250 InvalidRequest2,
251 ReadIdr,
252 ReadIsr
253 } I8259_READ_REQUEST;
254
255 typedef enum _I8259_EOI_MODE
256 {
257 RotateAutoEoiClear,
258 NonSpecificEoi,
259 InvalidEoiMode,
260 SpecificEoi,
261 RotateAutoEoiSet,
262 RotateNonSpecific,
263 SetPriority,
264 RotateSpecific
265 } I8259_EOI_MODE;
266
267 //
268 // Definitions for ICW Registers
269 //
270 typedef union _I8259_ICW1
271 {
272 struct
273 {
274 UCHAR NeedIcw4:1;
275 I8259_ICW1_OPERATING_MODE OperatingMode:1;
276 I8259_ICW1_INTERVAL Interval:1;
277 I8259_ICW1_INTERRUPT_MODE InterruptMode:1;
278 UCHAR Init:1;
279 UCHAR InterruptVectorAddress:3;
280 };
281 UCHAR Bits;
282 } I8259_ICW1, *PI8259_ICW1;
283
284 typedef union _I8259_ICW2
285 {
286 struct
287 {
288 UCHAR Sbz:3;
289 UCHAR InterruptVector:5;
290 };
291 UCHAR Bits;
292 } I8259_ICW2, *PI8259_ICW2;
293
294 typedef union _I8259_ICW3
295 {
296 union
297 {
298 struct
299 {
300 UCHAR SlaveIrq0:1;
301 UCHAR SlaveIrq1:1;
302 UCHAR SlaveIrq2:1;
303 UCHAR SlaveIrq3:1;
304 UCHAR SlaveIrq4:1;
305 UCHAR SlaveIrq5:1;
306 UCHAR SlaveIrq6:1;
307 UCHAR SlaveIrq7:1;
308 };
309 struct
310 {
311 UCHAR SlaveId:3;
312 UCHAR Reserved:5;
313 };
314 };
315 UCHAR Bits;
316 } I8259_ICW3, *PI8259_ICW3;
317
318 typedef union _I8259_ICW4
319 {
320 struct
321 {
322 I8259_ICW4_SYSTEM_MODE SystemMode:1;
323 I8259_ICW4_EOI_MODE EoiMode:1;
324 I8259_ICW4_BUFFERED_MODE BufferedMode:2;
325 UCHAR SpecialFullyNestedMode:1;
326 UCHAR Reserved:3;
327 };
328 UCHAR Bits;
329 } I8259_ICW4, *PI8259_ICW4;
330
331 typedef union _I8259_OCW2
332 {
333 struct
334 {
335 UCHAR IrqNumber:3;
336 UCHAR Sbz:2;
337 I8259_EOI_MODE EoiMode:3;
338 };
339 UCHAR Bits;
340 } I8259_OCW2, *PI8259_OCW2;
341
342 typedef union _I8259_OCW3
343 {
344 struct
345 {
346 I8259_READ_REQUEST ReadRequest:2;
347 UCHAR PollCommand:1;
348 UCHAR Sbo:1;
349 UCHAR Sbz:1;
350 UCHAR SpecialMaskMode:2;
351 UCHAR Reserved:1;
352 };
353 UCHAR Bits;
354 } I8259_OCW3, *PI8259_OCW3;
355
356 typedef union _I8259_ISR
357 {
358 union
359 {
360 struct
361 {
362 UCHAR Irq0:1;
363 UCHAR Irq1:1;
364 UCHAR Irq2:1;
365 UCHAR Irq3:1;
366 UCHAR Irq4:1;
367 UCHAR Irq5:1;
368 UCHAR Irq6:1;
369 UCHAR Irq7:1;
370 };
371 };
372 UCHAR Bits;
373 } I8259_ISR, *PI8259_ISR;
374
375 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
376
377 //
378 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
379 // P. 34, 35
380 //
381 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
382 //
383 #define EISA_ELCR_MASTER 0x4D0
384 #define EISA_ELCR_SLAVE 0x4D1
385
386 typedef union _EISA_ELCR
387 {
388 struct
389 {
390 struct
391 {
392 UCHAR Irq0Level:1;
393 UCHAR Irq1Level:1;
394 UCHAR Irq2Level:1;
395 UCHAR Irq3Level:1;
396 UCHAR Irq4Level:1;
397 UCHAR Irq5Level:1;
398 UCHAR Irq6Level:1;
399 UCHAR Irq7Level:1;
400 } Master;
401 struct
402 {
403 UCHAR Irq8Level:1;
404 UCHAR Irq9Level:1;
405 UCHAR Irq10Level:1;
406 UCHAR Irq11Level:1;
407 UCHAR Irq12Level:1;
408 UCHAR Irq13Level:1;
409 UCHAR Irq14Level:1;
410 UCHAR Irq15Level:1;
411 } Slave;
412 };
413 USHORT Bits;
414 } EISA_ELCR, *PEISA_ELCR;
415
416 typedef struct _PIC_MASK
417 {
418 union
419 {
420 struct
421 {
422 UCHAR Master;
423 UCHAR Slave;
424 };
425 USHORT Both;
426 };
427 } PIC_MASK, *PPIC_MASK;
428
429 typedef
430 BOOLEAN
431 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
432 IN KIRQL Irql,
433 IN ULONG Irq,
434 OUT PKIRQL OldIrql
435 );
436
437 BOOLEAN
438 REGISTERCALL
439 HalpDismissIrqGeneric(
440 IN KIRQL Irql,
441 IN ULONG Irq,
442 OUT PKIRQL OldIrql
443 );
444
445 BOOLEAN
446 REGISTERCALL
447 HalpDismissIrq15(
448 IN KIRQL Irql,
449 IN ULONG Irq,
450 OUT PKIRQL OldIrql
451 );
452
453 BOOLEAN
454 REGISTERCALL
455 HalpDismissIrq13(
456 IN KIRQL Irql,
457 IN ULONG Irq,
458 OUT PKIRQL OldIrql
459 );
460
461 BOOLEAN
462 REGISTERCALL
463 HalpDismissIrq07(
464 IN KIRQL Irql,
465 IN ULONG Irq,
466 OUT PKIRQL OldIrql
467 );
468
469 BOOLEAN
470 REGISTERCALL
471 HalpDismissIrqLevel(
472 IN KIRQL Irql,
473 IN ULONG Irq,
474 OUT PKIRQL OldIrql
475 );
476
477 BOOLEAN
478 REGISTERCALL
479 HalpDismissIrq15Level(
480 IN KIRQL Irql,
481 IN ULONG Irq,
482 OUT PKIRQL OldIrql
483 );
484
485 BOOLEAN
486 REGISTERCALL
487 HalpDismissIrq13Level(
488 IN KIRQL Irql,
489 IN ULONG Irq,
490 OUT PKIRQL OldIrql
491 );
492
493 BOOLEAN
494 REGISTERCALL
495 HalpDismissIrq07Level(
496 IN KIRQL Irql,
497 IN ULONG Irq,
498 OUT PKIRQL OldIrql
499 );
500
501 VOID
502 HalpHardwareInterruptLevel(
503 VOID
504 );
505
506 //
507 // Hack Flags
508 //
509 #define HALP_REVISION_FROM_HACK_FLAGS(x) ((x) >> 24)
510 #define HALP_REVISION_HACK_FLAGS(x) ((x) >> 12)
511 #define HALP_HACK_FLAGS(x) ((x) & 0xFFF)
512
513 //
514 // Feature flags
515 //
516 #define HALP_CARD_FEATURE_FULL_DECODE 0x0001
517
518 //
519 // Match Flags
520 //
521 #define HALP_CHECK_CARD_REVISION_ID 0x10000
522 #define HALP_CHECK_CARD_SUBVENDOR_ID 0x20000
523 #define HALP_CHECK_CARD_SUBSYSTEM_ID 0x40000
524
525 //
526 // Mm PTE/PDE to Hal PTE/PDE
527 //
528 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
529 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
530
531 typedef struct _IDTUsageFlags
532 {
533 UCHAR Flags;
534 } IDTUsageFlags;
535
536 typedef struct
537 {
538 KIRQL Irql;
539 UCHAR BusReleativeVector;
540 } IDTUsage;
541
542 typedef struct _HalAddressUsage
543 {
544 struct _HalAddressUsage *Next;
545 CM_RESOURCE_TYPE Type;
546 UCHAR Flags;
547 struct
548 {
549 ULONG Start;
550 ULONG Length;
551 } Element[];
552 } ADDRESS_USAGE, *PADDRESS_USAGE;
553
554 /* adapter.c */
555 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
556
557 /* sysinfo.c */
558 VOID
559 NTAPI
560 HalpRegisterVector(IN UCHAR Flags,
561 IN ULONG BusVector,
562 IN ULONG SystemVector,
563 IN KIRQL Irql);
564
565 VOID
566 NTAPI
567 HalpEnableInterruptHandler(IN UCHAR Flags,
568 IN ULONG BusVector,
569 IN ULONG SystemVector,
570 IN KIRQL Irql,
571 IN PVOID Handler,
572 IN KINTERRUPT_MODE Mode);
573
574 /* pic.c */
575 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
576 VOID HalpApcInterrupt(VOID);
577 VOID HalpDispatchInterrupt(VOID);
578 VOID HalpDispatchInterrupt2(VOID);
579 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
580 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
581
582 /* timer.c */
583 VOID NTAPI HalpInitializeClock(VOID);
584 VOID HalpClockInterrupt(VOID);
585 VOID HalpProfileInterrupt(VOID);
586
587 VOID
588 NTAPI
589 HalpCalibrateStallExecution(VOID);
590
591 /* pci.c */
592 VOID HalpInitPciBus (VOID);
593
594 /* dma.c */
595 VOID HalpInitDma (VOID);
596
597 /* Non-generic initialization */
598 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
599 VOID HalpInitPhase1(VOID);
600
601 VOID
602 NTAPI
603 HalpFlushTLB(VOID);
604
605 //
606 // KD Support
607 //
608 VOID
609 NTAPI
610 HalpCheckPowerButton(
611 VOID
612 );
613
614 VOID
615 NTAPI
616 HalpRegisterKdSupportFunctions(
617 VOID
618 );
619
620 NTSTATUS
621 NTAPI
622 HalpSetupPciDeviceForDebugging(
623 IN PVOID LoaderBlock,
624 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
625 );
626
627 NTSTATUS
628 NTAPI
629 HalpReleasePciDeviceForDebugging(
630 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
631 );
632
633 //
634 // Memory routines
635 //
636 PVOID
637 NTAPI
638 HalpMapPhysicalMemory64(
639 IN PHYSICAL_ADDRESS PhysicalAddress,
640 IN ULONG NumberPage
641 );
642
643 VOID
644 NTAPI
645 HalpUnmapVirtualAddress(
646 IN PVOID VirtualAddress,
647 IN ULONG NumberPages
648 );
649
650 /* sysinfo.c */
651 NTSTATUS
652 NTAPI
653 HaliQuerySystemInformation(
654 IN HAL_QUERY_INFORMATION_CLASS InformationClass,
655 IN ULONG BufferSize,
656 IN OUT PVOID Buffer,
657 OUT PULONG ReturnedLength
658 );
659
660 NTSTATUS
661 NTAPI
662 HaliSetSystemInformation(
663 IN HAL_SET_INFORMATION_CLASS InformationClass,
664 IN ULONG BufferSize,
665 IN OUT PVOID Buffer
666 );
667
668 //
669 // BIOS Routines
670 //
671 BOOLEAN
672 NTAPI
673 HalpBiosDisplayReset(
674 VOID
675 );
676
677 VOID
678 FASTCALL
679 HalpExitToV86(
680 PKTRAP_FRAME TrapFrame
681 );
682
683 VOID
684 DECLSPEC_NORETURN
685 HalpRealModeStart(
686 VOID
687 );
688
689 //
690 // Processor Halt Routine
691 //
692 VOID
693 NTAPI
694 HaliHaltSystem(
695 VOID
696 );
697
698 //
699 // CMOS Routines
700 //
701 VOID
702 NTAPI
703 HalpInitializeCmos(
704 VOID
705 );
706
707 UCHAR
708 NTAPI
709 HalpReadCmos(
710 IN UCHAR Reg
711 );
712
713 VOID
714 NTAPI
715 HalpWriteCmos(
716 IN UCHAR Reg,
717 IN UCHAR Value
718 );
719
720 //
721 // Spinlock for protecting CMOS access
722 //
723 VOID
724 NTAPI
725 HalpAcquireSystemHardwareSpinLock(
726 VOID
727 );
728
729 VOID
730 NTAPI
731 HalpReleaseCmosSpinLock(
732 VOID
733 );
734
735 ULONG
736 NTAPI
737 HalpAllocPhysicalMemory(
738 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
739 IN ULONG MaxAddress,
740 IN ULONG PageCount,
741 IN BOOLEAN Aligned
742 );
743
744 PVOID
745 NTAPI
746 HalpMapPhysicalMemory64(
747 IN PHYSICAL_ADDRESS PhysicalAddress,
748 IN ULONG PageCount
749 );
750
751 NTSTATUS
752 NTAPI
753 HalpOpenRegistryKey(
754 IN PHANDLE KeyHandle,
755 IN HANDLE RootKey,
756 IN PUNICODE_STRING KeyName,
757 IN ACCESS_MASK DesiredAccess,
758 IN BOOLEAN Create
759 );
760
761 VOID
762 NTAPI
763 HalpGetNMICrashFlag(
764 VOID
765 );
766
767 BOOLEAN
768 NTAPI
769 HalpGetDebugPortTable(
770 VOID
771 );
772
773 VOID
774 NTAPI
775 HalpReportSerialNumber(
776 VOID
777 );
778
779 NTSTATUS
780 NTAPI
781 HalpMarkAcpiHal(
782 VOID
783 );
784
785 VOID
786 NTAPI
787 HalpBuildAddressMap(
788 VOID
789 );
790
791 VOID
792 NTAPI
793 HalpReportResourceUsage(
794 IN PUNICODE_STRING HalName,
795 IN INTERFACE_TYPE InterfaceType
796 );
797
798 ULONG
799 NTAPI
800 HalpIs16BitPortDecodeSupported(
801 VOID
802 );
803
804 NTSTATUS
805 NTAPI
806 HalpQueryAcpiResourceRequirements(
807 OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
808 );
809
810 VOID
811 FASTCALL
812 KeUpdateSystemTime(
813 IN PKTRAP_FRAME TrapFrame,
814 IN ULONG Increment,
815 IN KIRQL OldIrql
816 );
817
818 VOID
819 NTAPI
820 HalpInitBusHandlers(
821 VOID
822 );
823
824 NTSTATUS
825 NTAPI
826 HaliInitPnpDriver(
827 VOID
828 );
829
830 VOID
831 NTAPI
832 HalpDebugPciDumpBus(
833 IN ULONG i,
834 IN ULONG j,
835 IN ULONG k,
836 IN PPCI_COMMON_CONFIG PciData
837 );
838
839 #ifdef _M_AMD64
840 #define KfLowerIrql KeLowerIrql
841 #ifndef CONFIG_SMP
842 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
843 #define KiAcquireSpinLock(SpinLock)
844 #define KiReleaseSpinLock(SpinLock)
845 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
846 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
847 #endif // !CONFIG_SMP
848 #endif // _M_AMD64
849
850 extern BOOLEAN HalpNMIInProgress;
851
852 extern ADDRESS_USAGE HalpDefaultIoSpace;
853
854 extern KSPIN_LOCK HalpSystemHardwareLock;
855
856 extern PADDRESS_USAGE HalpAddressUsageList;
857
858 extern LARGE_INTEGER HalpPerfCounter;
859
860 extern KAFFINITY HalpActiveProcessors;
861
862 extern BOOLEAN HalDisableFirmwareMapper;
863 extern PWCHAR HalHardwareIdString;
864 extern PWCHAR HalName;
865
866 extern KAFFINITY HalpDefaultInterruptAffinity;
867
868 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR];
869