hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 #define PLACE_IN_SECTION(s)     __attribute__((section (s)))
   8 #ifdef __GNUC__
   9 #define INIT_FUNCTION
  10 #define PAGE_LOCKED_FUNCTION    PLACE_IN_SECTION("pagelk")
  11 #define PAGE_UNLOCKED_FUNCTION  PLACE_IN_SECTION("pagepo")
  12 #else
  13 #define INIT_FUNCTION
  14 #define PAGE_LOCKED_FUNCTION
  15 #define PAGE_UNLOCKED_FUNCTION
  16 #endif
  17
  18 #ifdef _MSC_VER
  19 #define REGISTERCALL FASTCALL
  20 #else
  21 #define REGISTERCALL __attribute__((regparm(3)))
  22 #endif
  23
  24 #ifdef CONFIG_SMP
  25 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
  26 #else
  27 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
  28 #endif
  29
  30 typedef struct _HAL_BIOS_FRAME
  31 {
  32     ULONG SegSs;
  33     ULONG Esp;
  34     ULONG EFlags;
  35     ULONG SegCs;
  36     ULONG Eip;
  37     PKTRAP_FRAME TrapFrame;
  38     ULONG CsLimit;
  39     ULONG CsBase;
  40     ULONG CsFlags;
  41     ULONG SsLimit;
  42     ULONG SsBase;
  43     ULONG SsFlags;
  44     ULONG Prefix;
  45 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  46
  47 typedef
  48 VOID
  49 (*PHAL_SW_INTERRUPT_HANDLER)(
  50     VOID
  51 );
  52
  53 typedef
  54 VOID
  55 ATTRIB_NORETURN
  56 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  57     IN PKTRAP_FRAME TrapFrame
  58 );
  59
  60 #define HAL_APC_REQUEST         0
  61 #define HAL_DPC_REQUEST         1
  62
  63 /* CMOS Registers and Ports */
  64 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  65 #define CMOS_DATA_PORT          (PUCHAR)0x71
  66 #define RTC_REGISTER_A          0x0A
  67 #define   RTC_REG_A_UIP         0x80
  68 #define RTC_REGISTER_B          0x0B
  69 #define   RTC_REG_B_PI          0x40
  70 #define RTC_REGISTER_C          0x0C
  71 #define RTC_REGISTER_D          0x0D
  72 #define RTC_REGISTER_CENTURY    0x32
  73
  74 /* Usage flags */
  75 #define IDT_REGISTERED          0x01
  76 #define IDT_LATCHED             0x02
  77 #define IDT_READ_ONLY           0x04
  78 #define IDT_INTERNAL            0x11
  79 #define IDT_DEVICE              0x21
  80
  81 /* Conversion functions */
  82 #define BCD_INT(bcd)            \
  83     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  84 #define INT_BCD(int)            \
  85     (UCHAR)(((int / 10) << 4) + (int % 10))
  86
  87 //
  88 // BIOS Interrupts
  89 //
  90 #define VIDEO_SERVICES   0x10
  91
  92 //
  93 // Operations for INT 10h (in AH)
  94 //
  95 #define SET_VIDEO_MODE   0x00
  96
  97 //
  98 // Video Modes for INT10h AH=00 (in AL)
  99 //
 100 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
 101
 102 //
 103 // Commonly stated as being 1.19318MHz
 104 //
 105 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 106 // P. 471
 107 //
 108 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
 109 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 110 //
 111 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 112 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 113 // infinite series) and divides it by three, one obtains 1.19318167.
 114 //
 115 // It may be that the original NT HAL source code introduced a typo and turned
 116 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 117 // number is quite long.
 118 //
 119 #define PIT_FREQUENCY 1193182
 120
 121 //
 122 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 123 //
 124 #define TIMER_CHANNEL0_DATA_PORT 0x40
 125 #define TIMER_CHANNEL1_DATA_PORT 0x41
 126 #define TIMER_CHANNEL2_DATA_PORT 0x42
 127 #define TIMER_CONTROL_PORT       0x43
 128
 129 //
 130 // Mode 0 - Interrupt On Terminal Count
 131 // Mode 1 - Hardware Re-triggerable One-Shot
 132 // Mode 2 - Rate Generator
 133 // Mode 3 - Square Wave Generator
 134 // Mode 4 - Software Triggered Strobe
 135 // Mode 5 - Hardware Triggered Strobe
 136 //
 137 typedef enum _TIMER_OPERATING_MODES
 138 {
 139     PitOperatingMode0,
 140     PitOperatingMode1,
 141     PitOperatingMode2,
 142     PitOperatingMode3,
 143     PitOperatingMode4,
 144     PitOperatingMode5,
 145     PitOperatingMode2Reserved,
 146     PitOperatingMode5Reserved
 147 } TIMER_OPERATING_MODES;
 148
 149 typedef enum _TIMER_ACCESS_MODES
 150 {
 151     PitAccessModeCounterLatch,
 152     PitAccessModeLow,
 153     PitAccessModeHigh,
 154     PitAccessModeLowHigh
 155 } TIMER_ACCESS_MODES;
 156
 157 typedef enum _TIMER_CHANNELS
 158 {
 159     PitChannel0,
 160     PitChannel1,
 161     PitChannel2,
 162     PitReadBack
 163 } TIMER_CHANNELS;
 164
 165 typedef union _TIMER_CONTROL_PORT_REGISTER
 166 {
 167     struct
 168     {
 169         UCHAR BcdMode:1;
 170         UCHAR OperatingMode:3;
 171         UCHAR AccessMode:2;
 172         UCHAR Channel:2;
 173     };
 174     UCHAR Bits;
 175 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 176
 177 //
 178 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 179 // P. 400
 180 //
 181 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 182 //
 183 #define SYSTEM_CONTROL_PORT_A   0x92
 184 #define SYSTEM_CONTROL_PORT_B   0x61
 185 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 186 {
 187     struct
 188     {
 189         UCHAR Timer2GateToSpeaker:1;
 190         UCHAR SpeakerDataEnable:1;
 191         UCHAR ParityCheckEnable:1;
 192         UCHAR ChannelCheckEnable:1;
 193         UCHAR RefreshRequest:1;
 194         UCHAR Timer2Output:1;
 195         UCHAR ChannelCheck:1;
 196         UCHAR ParityCheck:1;
 197     };
 198     UCHAR Bits;
 199 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 200
 201 //
 202 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 203 // P. 396, 397
 204 //
 205 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 206 //
 207 #define PIC1_CONTROL_PORT      0x20
 208 #define PIC1_DATA_PORT         0x21
 209 #define PIC2_CONTROL_PORT      0xA0
 210 #define PIC2_DATA_PORT         0xA1
 211
 212 //
 213 // Definitions for ICW/OCW Bits
 214 //
 215 typedef enum _I8259_ICW1_OPERATING_MODE
 216 {
 217     Cascade,
 218     Single
 219 } I8259_ICW1_OPERATING_MODE;
 220
 221 typedef enum _I8259_ICW1_INTERRUPT_MODE
 222 {
 223     EdgeTriggered,
 224     LevelTriggered
 225 } I8259_ICW1_INTERRUPT_MODE;
 226
 227 typedef enum _I8259_ICW1_INTERVAL
 228 {
 229     Interval8,
 230     Interval4
 231 } I8259_ICW1_INTERVAL;
 232
 233 typedef enum _I8259_ICW4_SYSTEM_MODE
 234 {
 235     Mcs8085Mode,
 236     New8086Mode
 237 } I8259_ICW4_SYSTEM_MODE;
 238
 239 typedef enum _I8259_ICW4_EOI_MODE
 240 {
 241     NormalEoi,
 242     AutomaticEoi
 243 } I8259_ICW4_EOI_MODE;
 244
 245 typedef enum _I8259_ICW4_BUFFERED_MODE
 246 {
 247     NonBuffered,
 248     NonBuffered2,
 249     BufferedSlave,
 250     BufferedMaster
 251 } I8259_ICW4_BUFFERED_MODE;
 252
 253 typedef enum _I8259_READ_REQUEST
 254 {
 255     InvalidRequest,
 256     InvalidRequest2,
 257     ReadIdr,
 258     ReadIsr
 259 } I8259_READ_REQUEST;
 260
 261 typedef enum _I8259_EOI_MODE
 262 {
 263     RotateAutoEoiClear,
 264     NonSpecificEoi,
 265     InvalidEoiMode,
 266     SpecificEoi,
 267     RotateAutoEoiSet,
 268     RotateNonSpecific,
 269     SetPriority,
 270     RotateSpecific
 271 } I8259_EOI_MODE;
 272
 273 //
 274 // Definitions for ICW Registers
 275 //
 276 typedef union _I8259_ICW1
 277 {
 278     struct
 279     {
 280         UCHAR NeedIcw4:1;
 281         UCHAR OperatingMode:1;
 282         UCHAR Interval:1;
 283         UCHAR InterruptMode:1;
 284         UCHAR Init:1;
 285         UCHAR InterruptVectorAddress:3;
 286     };
 287     UCHAR Bits;
 288 } I8259_ICW1, *PI8259_ICW1;
 289
 290 typedef union _I8259_ICW2
 291 {
 292     struct
 293     {
 294         UCHAR Sbz:3;
 295         UCHAR InterruptVector:5;
 296     };
 297     UCHAR Bits;
 298 } I8259_ICW2, *PI8259_ICW2;
 299
 300 typedef union _I8259_ICW3
 301 {
 302     union
 303     {
 304         struct
 305         {
 306             UCHAR SlaveIrq0:1;
 307             UCHAR SlaveIrq1:1;
 308             UCHAR SlaveIrq2:1;
 309             UCHAR SlaveIrq3:1;
 310             UCHAR SlaveIrq4:1;
 311             UCHAR SlaveIrq5:1;
 312             UCHAR SlaveIrq6:1;
 313             UCHAR SlaveIrq7:1;
 314         };
 315         struct
 316         {
 317             UCHAR SlaveId:3;
 318             UCHAR Reserved:5;
 319         };
 320     };
 321     UCHAR Bits;
 322 } I8259_ICW3, *PI8259_ICW3;
 323
 324 typedef union _I8259_ICW4
 325 {
 326     struct
 327     {
 328         UCHAR SystemMode:1;
 329         UCHAR EoiMode:1;
 330         UCHAR BufferedMode:2;
 331         UCHAR SpecialFullyNestedMode:1;
 332         UCHAR Reserved:3;
 333     };
 334     UCHAR Bits;
 335 } I8259_ICW4, *PI8259_ICW4;
 336
 337 typedef union _I8259_OCW2
 338 {
 339     struct
 340     {
 341         UCHAR IrqNumber:3;
 342         UCHAR Sbz:2;
 343         UCHAR EoiMode:3;
 344     };
 345     UCHAR Bits;
 346 } I8259_OCW2, *PI8259_OCW2;
 347
 348 typedef union _I8259_OCW3
 349 {
 350     struct
 351     {
 352         UCHAR ReadRequest:2;
 353         UCHAR PollCommand:1;
 354         UCHAR Sbo:1;
 355         UCHAR Sbz:1;
 356         UCHAR SpecialMaskMode:2;
 357         UCHAR Reserved:1;
 358     };
 359     UCHAR Bits;
 360 } I8259_OCW3, *PI8259_OCW3;
 361
 362 typedef union _I8259_ISR
 363 {
 364     union
 365     {
 366         struct
 367         {
 368             UCHAR Irq0:1;
 369             UCHAR Irq1:1;
 370             UCHAR Irq2:1;
 371             UCHAR Irq3:1;
 372             UCHAR Irq4:1;
 373             UCHAR Irq5:1;
 374             UCHAR Irq6:1;
 375             UCHAR Irq7:1;
 376         };
 377     };
 378     UCHAR Bits;
 379 } I8259_ISR, *PI8259_ISR;
 380
 381 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 382
 383 //
 384 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 385 // P. 34, 35
 386 //
 387 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 388 //
 389 #define EISA_ELCR_MASTER       0x4D0
 390 #define EISA_ELCR_SLAVE        0x4D1
 391
 392 typedef union _EISA_ELCR
 393 {
 394     struct
 395     {
 396         struct
 397         {
 398             UCHAR Irq0Level:1;
 399             UCHAR Irq1Level:1;
 400             UCHAR Irq2Level:1;
 401             UCHAR Irq3Level:1;
 402             UCHAR Irq4Level:1;
 403             UCHAR Irq5Level:1;
 404             UCHAR Irq6Level:1;
 405             UCHAR Irq7Level:1;
 406         } Master;
 407         struct
 408         {
 409             UCHAR Irq8Level:1;
 410             UCHAR Irq9Level:1;
 411             UCHAR Irq10Level:1;
 412             UCHAR Irq11Level:1;
 413             UCHAR Irq12Level:1;
 414             UCHAR Irq13Level:1;
 415             UCHAR Irq14Level:1;
 416             UCHAR Irq15Level:1;
 417         } Slave;
 418     };
 419     USHORT Bits;
 420 } EISA_ELCR, *PEISA_ELCR;
 421
 422 typedef struct _PIC_MASK
 423 {
 424     union
 425     {
 426         struct
 427         {
 428             UCHAR Master;
 429             UCHAR Slave;
 430         };
 431         USHORT Both;
 432     };
 433 } PIC_MASK, *PPIC_MASK;
 434
 435 typedef
 436 BOOLEAN
 437 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
 438     IN KIRQL Irql,
 439     IN ULONG Irq,
 440     OUT PKIRQL OldIrql
 441 );
 442
 443 BOOLEAN
 444 REGISTERCALL
 445 HalpDismissIrqGeneric(
 446     IN KIRQL Irql,
 447     IN ULONG Irq,
 448     OUT PKIRQL OldIrql
 449 );
 450
 451 BOOLEAN
 452 REGISTERCALL
 453 HalpDismissIrq15(
 454     IN KIRQL Irql,
 455     IN ULONG Irq,
 456     OUT PKIRQL OldIrql
 457 );
 458
 459 BOOLEAN
 460 REGISTERCALL
 461 HalpDismissIrq13(
 462     IN KIRQL Irql,
 463     IN ULONG Irq,
 464     OUT PKIRQL OldIrql
 465 );
 466
 467 BOOLEAN
 468 REGISTERCALL
 469 HalpDismissIrq07(
 470     IN KIRQL Irql,
 471     IN ULONG Irq,
 472     OUT PKIRQL OldIrql
 473 );
 474
 475 BOOLEAN
 476 REGISTERCALL
 477 HalpDismissIrqLevel(
 478     IN KIRQL Irql,
 479     IN ULONG Irq,
 480     OUT PKIRQL OldIrql
 481 );
 482
 483 BOOLEAN
 484 REGISTERCALL
 485 HalpDismissIrq15Level(
 486     IN KIRQL Irql,
 487     IN ULONG Irq,
 488     OUT PKIRQL OldIrql
 489 );
 490
 491 BOOLEAN
 492 REGISTERCALL
 493 HalpDismissIrq13Level(
 494     IN KIRQL Irql,
 495     IN ULONG Irq,
 496     OUT PKIRQL OldIrql
 497 );
 498
 499 BOOLEAN
 500 REGISTERCALL
 501 HalpDismissIrq07Level(
 502     IN KIRQL Irql,
 503     IN ULONG Irq,
 504     OUT PKIRQL OldIrql
 505 );
 506
 507 VOID
 508 HalpHardwareInterruptLevel(
 509     VOID
 510 );
 511
 512 //
 513 // Hack Flags
 514 //
 515 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 516 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 517 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 518
 519 //
 520 // Feature flags
 521 //
 522 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 523
 524 //
 525 // Match Flags
 526 //
 527 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 528 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 529 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 530
 531 //
 532 // Mm PTE/PDE to Hal PTE/PDE
 533 //
 534 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 535 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 536
 537 typedef struct _IDTUsageFlags
 538 {
 539     UCHAR Flags;
 540 } IDTUsageFlags;
 541
 542 typedef struct
 543 {
 544     KIRQL Irql;
 545     UCHAR BusReleativeVector;
 546 } IDTUsage;
 547
 548 typedef struct _HalAddressUsage
 549 {
 550     struct _HalAddressUsage *Next;
 551     CM_RESOURCE_TYPE Type;
 552     UCHAR Flags;
 553     struct
 554     {
 555         ULONG Start;
 556         ULONG Length;
 557     } Element[];
 558 } ADDRESS_USAGE, *PADDRESS_USAGE;
 559
 560 /* adapter.c */
 561 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 562
 563 /* sysinfo.c */
 564 VOID
 565 NTAPI
 566 HalpRegisterVector(IN UCHAR Flags,
 567                    IN ULONG BusVector,
 568                    IN ULONG SystemVector,
 569                    IN KIRQL Irql);
 570
 571 VOID
 572 NTAPI
 573 HalpEnableInterruptHandler(IN UCHAR Flags,
 574                            IN ULONG BusVector,
 575                            IN ULONG SystemVector,
 576                            IN KIRQL Irql,
 577                            IN PVOID Handler,
 578                            IN KINTERRUPT_MODE Mode);
 579
 580 /* pic.c */
 581 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 582 VOID HalpApcInterrupt(VOID);
 583 VOID HalpDispatchInterrupt(VOID);
 584 VOID HalpDispatchInterrupt2(VOID);
 585 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 586 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 587
 588 /* timer.c */
 589 VOID NTAPI HalpInitializeClock(VOID);
 590 VOID HalpClockInterrupt(VOID);
 591 VOID HalpProfileInterrupt(VOID);
 592
 593 VOID
 594 NTAPI
 595 HalpCalibrateStallExecution(VOID);
 596
 597 /* pci.c */
 598 VOID HalpInitPciBus (VOID);
 599
 600 /* dma.c */
 601 VOID HalpInitDma (VOID);
 602
 603 /* Non-generic initialization */
 604 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 605 VOID HalpInitPhase1(VOID);
 606
 607 VOID
 608 NTAPI
 609 HalpFlushTLB(VOID);
 610
 611 //
 612 // KD Support
 613 //
 614 VOID
 615 NTAPI
 616 HalpCheckPowerButton(
 617     VOID
 618 );
 619
 620 VOID
 621 NTAPI
 622 HalpRegisterKdSupportFunctions(
 623     VOID
 624 );
 625
 626 NTSTATUS
 627 NTAPI
 628 HalpSetupPciDeviceForDebugging(
 629     IN PVOID LoaderBlock,
 630     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 631 );
 632
 633 NTSTATUS
 634 NTAPI
 635 HalpReleasePciDeviceForDebugging(
 636     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 637 );
 638
 639 //
 640 // Memory routines
 641 //
 642 ULONG_PTR
 643 NTAPI
 644 HalpAllocPhysicalMemory(
 645     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 646     IN ULONG_PTR MaxAddress,
 647     IN PFN_NUMBER PageCount,
 648     IN BOOLEAN Aligned
 649 );
 650
 651 PVOID
 652 NTAPI
 653 HalpMapPhysicalMemory64(
 654     IN PHYSICAL_ADDRESS PhysicalAddress,
 655     IN PFN_COUNT PageCount
 656 );
 657
 658 VOID
 659 NTAPI
 660 HalpUnmapVirtualAddress(
 661     IN PVOID VirtualAddress,
 662     IN PFN_COUNT NumberPages
 663 );
 664
 665 /* sysinfo.c */
 666 NTSTATUS
 667 NTAPI
 668 HaliQuerySystemInformation(
 669     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 670     IN ULONG BufferSize,
 671     IN OUT PVOID Buffer,
 672     OUT PULONG ReturnedLength
 673 );
 674
 675 NTSTATUS
 676 NTAPI
 677 HaliSetSystemInformation(
 678     IN HAL_SET_INFORMATION_CLASS InformationClass,
 679     IN ULONG BufferSize,
 680     IN OUT PVOID Buffer
 681 );
 682
 683 //
 684 // BIOS Routines
 685 //
 686 BOOLEAN
 687 NTAPI
 688 HalpBiosDisplayReset(
 689     VOID
 690 );
 691
 692 VOID
 693 FASTCALL
 694 HalpExitToV86(
 695     PKTRAP_FRAME TrapFrame
 696 );
 697
 698 VOID
 699 DECLSPEC_NORETURN
 700 HalpRealModeStart(
 701     VOID
 702 );
 703
 704 //
 705 // Processor Halt Routine
 706 //
 707 VOID
 708 NTAPI
 709 HaliHaltSystem(
 710     VOID
 711 );
 712
 713 //
 714 // CMOS Routines
 715 //
 716 VOID
 717 NTAPI
 718 HalpInitializeCmos(
 719     VOID
 720 );
 721
 722 UCHAR
 723 NTAPI
 724 HalpReadCmos(
 725     IN UCHAR Reg
 726 );
 727
 728 VOID
 729 NTAPI
 730 HalpWriteCmos(
 731     IN UCHAR Reg,
 732     IN UCHAR Value
 733 );
 734
 735 //
 736 // Spinlock for protecting CMOS access
 737 //
 738 VOID
 739 NTAPI
 740 HalpAcquireCmosSpinLock(
 741     VOID
 742 );
 743
 744 VOID
 745 NTAPI
 746 HalpReleaseCmosSpinLock(
 747     VOID
 748 );
 749
 750 NTSTATUS
 751 NTAPI
 752 HalpOpenRegistryKey(
 753     IN PHANDLE KeyHandle,
 754     IN HANDLE RootKey,
 755     IN PUNICODE_STRING KeyName,
 756     IN ACCESS_MASK DesiredAccess,
 757     IN BOOLEAN Create
 758 );
 759
 760 VOID
 761 NTAPI
 762 HalpGetNMICrashFlag(
 763     VOID
 764 );
 765
 766 BOOLEAN
 767 NTAPI
 768 HalpGetDebugPortTable(
 769     VOID
 770 );
 771
 772 VOID
 773 NTAPI
 774 HalpReportSerialNumber(
 775     VOID
 776 );
 777
 778 NTSTATUS
 779 NTAPI
 780 HalpMarkAcpiHal(
 781     VOID
 782 );
 783
 784 VOID
 785 NTAPI
 786 HalpBuildAddressMap(
 787     VOID
 788 );
 789
 790 VOID
 791 NTAPI
 792 HalpReportResourceUsage(
 793     IN PUNICODE_STRING HalName,
 794     IN INTERFACE_TYPE InterfaceType
 795 );
 796
 797 ULONG
 798 NTAPI
 799 HalpIs16BitPortDecodeSupported(
 800     VOID
 801 );
 802
 803 NTSTATUS
 804 NTAPI
 805 HalpQueryAcpiResourceRequirements(
 806     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 807 );
 808
 809 VOID
 810 FASTCALL
 811 KeUpdateSystemTime(
 812     IN PKTRAP_FRAME TrapFrame,
 813     IN ULONG Increment,
 814     IN KIRQL OldIrql
 815 );
 816
 817 VOID
 818 NTAPI
 819 HalpInitBusHandlers(
 820     VOID
 821 );
 822
 823 NTSTATUS
 824 NTAPI
 825 HaliInitPnpDriver(
 826     VOID
 827 );
 828
 829 VOID
 830 NTAPI
 831 HalpDebugPciDumpBus(
 832     IN ULONG i,
 833     IN ULONG j,
 834     IN ULONG k,
 835     IN PPCI_COMMON_CONFIG PciData
 836 );
 837
 838 VOID
 839 NTAPI
 840 HalpInitProcessor(
 841     IN ULONG ProcessorNumber,
 842     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 843 );
 844
 845 #ifdef _M_AMD64
 846 #define KfLowerIrql KeLowerIrql
 847 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
 848 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
 849 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
 850 #ifndef CONFIG_SMP
 851 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 852 #define KiAcquireSpinLock(SpinLock)
 853 #define KiReleaseSpinLock(SpinLock)
 854 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 855 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 856 #endif // !CONFIG_SMP
 857 #endif // _M_AMD64
 858
 859 extern BOOLEAN HalpNMIInProgress;
 860
 861 extern ADDRESS_USAGE HalpDefaultIoSpace;
 862
 863 extern KSPIN_LOCK HalpSystemHardwareLock;
 864
 865 extern PADDRESS_USAGE HalpAddressUsageList;
 866
 867 extern LARGE_INTEGER HalpPerfCounter;
 868
 869 extern KAFFINITY HalpActiveProcessors;
 870
 871 extern BOOLEAN HalDisableFirmwareMapper;
 872 extern PWCHAR HalHardwareIdString;
 873 extern PWCHAR HalName;
 874
 875 extern KAFFINITY HalpDefaultInterruptAffinity;
 876
 877 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
 878
 879 extern const USHORT HalpBuildType;