hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7 #if defined(__GNUC__) && !defined(_MINIHAL_)
   8 #define INIT_SECTION __attribute__((section ("INIT")))
   9 #else
  10 #define INIT_SECTION /* Done via alloc_text for MSC */
  11 #endif
  12
  13
  14 #ifdef CONFIG_SMP
  15 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
  16 #else
  17 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
  18 #endif
  19
  20 typedef struct _HAL_BIOS_FRAME
  21 {
  22     ULONG SegSs;
  23     ULONG Esp;
  24     ULONG EFlags;
  25     ULONG SegCs;
  26     ULONG Eip;
  27     PKTRAP_FRAME TrapFrame;
  28     ULONG CsLimit;
  29     ULONG CsBase;
  30     ULONG CsFlags;
  31     ULONG SsLimit;
  32     ULONG SsBase;
  33     ULONG SsFlags;
  34     ULONG Prefix;
  35 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  36
  37 typedef
  38 VOID
  39 (__cdecl *PHAL_SW_INTERRUPT_HANDLER)(
  40     VOID
  41 );
  42
  43 typedef
  44 VOID
  45 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  46     IN PKTRAP_FRAME TrapFrame
  47 );
  48
  49 #define HAL_APC_REQUEST         0
  50 #define HAL_DPC_REQUEST         1
  51
  52 /* CMOS Registers and Ports */
  53 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  54 #define CMOS_DATA_PORT          (PUCHAR)0x71
  55 #define RTC_REGISTER_A          0x0A
  56 #define   RTC_REG_A_UIP         0x80
  57 #define RTC_REGISTER_B          0x0B
  58 #define   RTC_REG_B_PI          0x40
  59 #define RTC_REGISTER_C          0x0C
  60 #define   RTC_REG_C_IRQ         0x80
  61 #define RTC_REGISTER_D          0x0D
  62 #define RTC_REGISTER_CENTURY    0x32
  63
  64 /* Usage flags */
  65 #define IDT_REGISTERED          0x01
  66 #define IDT_LATCHED             0x02
  67 #define IDT_READ_ONLY           0x04
  68 #define IDT_INTERNAL            0x11
  69 #define IDT_DEVICE              0x21
  70
  71 /* Conversion functions */
  72 #define BCD_INT(bcd)            \
  73     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  74 #define INT_BCD(int)            \
  75     (UCHAR)(((int / 10) << 4) + (int % 10))
  76
  77 //
  78 // BIOS Interrupts
  79 //
  80 #define VIDEO_SERVICES   0x10
  81
  82 //
  83 // Operations for INT 10h (in AH)
  84 //
  85 #define SET_VIDEO_MODE   0x00
  86
  87 //
  88 // Video Modes for INT10h AH=00 (in AL)
  89 //
  90 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  91
  92 //
  93 // Commonly stated as being 1.19318MHz
  94 //
  95 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
  96 // P. 471
  97 //
  98 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
  99 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
 100 //
 101 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
 102 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
 103 // infinite series) and divides it by three, one obtains 1.19318167.
 104 //
 105 // It may be that the original NT HAL source code introduced a typo and turned
 106 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
 107 // number is quite long.
 108 //
 109 #define PIT_FREQUENCY 1193182
 110
 111 //
 112 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 113 //
 114 #define TIMER_CHANNEL0_DATA_PORT 0x40
 115 #define TIMER_CHANNEL1_DATA_PORT 0x41
 116 #define TIMER_CHANNEL2_DATA_PORT 0x42
 117 #define TIMER_CONTROL_PORT       0x43
 118
 119 //
 120 // Mode 0 - Interrupt On Terminal Count
 121 // Mode 1 - Hardware Re-triggerable One-Shot
 122 // Mode 2 - Rate Generator
 123 // Mode 3 - Square Wave Generator
 124 // Mode 4 - Software Triggered Strobe
 125 // Mode 5 - Hardware Triggered Strobe
 126 //
 127 typedef enum _TIMER_OPERATING_MODES
 128 {
 129     PitOperatingMode0,
 130     PitOperatingMode1,
 131     PitOperatingMode2,
 132     PitOperatingMode3,
 133     PitOperatingMode4,
 134     PitOperatingMode5,
 135     PitOperatingMode2Reserved,
 136     PitOperatingMode5Reserved
 137 } TIMER_OPERATING_MODES;
 138
 139 typedef enum _TIMER_ACCESS_MODES
 140 {
 141     PitAccessModeCounterLatch,
 142     PitAccessModeLow,
 143     PitAccessModeHigh,
 144     PitAccessModeLowHigh
 145 } TIMER_ACCESS_MODES;
 146
 147 typedef enum _TIMER_CHANNELS
 148 {
 149     PitChannel0,
 150     PitChannel1,
 151     PitChannel2,
 152     PitReadBack
 153 } TIMER_CHANNELS;
 154
 155 typedef union _TIMER_CONTROL_PORT_REGISTER
 156 {
 157     struct
 158     {
 159         UCHAR BcdMode:1;
 160         UCHAR OperatingMode:3;
 161         UCHAR AccessMode:2;
 162         UCHAR Channel:2;
 163     };
 164     UCHAR Bits;
 165 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 166
 167 //
 168 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 169 // P. 400
 170 //
 171 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 172 //
 173 #define SYSTEM_CONTROL_PORT_A   0x92
 174 #define SYSTEM_CONTROL_PORT_B   0x61
 175 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 176 {
 177     struct
 178     {
 179         UCHAR Timer2GateToSpeaker:1;
 180         UCHAR SpeakerDataEnable:1;
 181         UCHAR ParityCheckEnable:1;
 182         UCHAR ChannelCheckEnable:1;
 183         UCHAR RefreshRequest:1;
 184         UCHAR Timer2Output:1;
 185         UCHAR ChannelCheck:1;
 186         UCHAR ParityCheck:1;
 187     };
 188     UCHAR Bits;
 189 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 190
 191 //
 192 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 193 // P. 396, 397
 194 //
 195 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 196 //
 197 #define PIC1_CONTROL_PORT      0x20
 198 #define PIC1_DATA_PORT         0x21
 199 #define PIC2_CONTROL_PORT      0xA0
 200 #define PIC2_DATA_PORT         0xA1
 201
 202 //
 203 // Definitions for ICW/OCW Bits
 204 //
 205 typedef enum _I8259_ICW1_OPERATING_MODE
 206 {
 207     Cascade,
 208     Single
 209 } I8259_ICW1_OPERATING_MODE;
 210
 211 typedef enum _I8259_ICW1_INTERRUPT_MODE
 212 {
 213     EdgeTriggered,
 214     LevelTriggered
 215 } I8259_ICW1_INTERRUPT_MODE;
 216
 217 typedef enum _I8259_ICW1_INTERVAL
 218 {
 219     Interval8,
 220     Interval4
 221 } I8259_ICW1_INTERVAL;
 222
 223 typedef enum _I8259_ICW4_SYSTEM_MODE
 224 {
 225     Mcs8085Mode,
 226     New8086Mode
 227 } I8259_ICW4_SYSTEM_MODE;
 228
 229 typedef enum _I8259_ICW4_EOI_MODE
 230 {
 231     NormalEoi,
 232     AutomaticEoi
 233 } I8259_ICW4_EOI_MODE;
 234
 235 typedef enum _I8259_ICW4_BUFFERED_MODE
 236 {
 237     NonBuffered,
 238     NonBuffered2,
 239     BufferedSlave,
 240     BufferedMaster
 241 } I8259_ICW4_BUFFERED_MODE;
 242
 243 typedef enum _I8259_READ_REQUEST
 244 {
 245     InvalidRequest,
 246     InvalidRequest2,
 247     ReadIdr,
 248     ReadIsr
 249 } I8259_READ_REQUEST;
 250
 251 typedef enum _I8259_EOI_MODE
 252 {
 253     RotateAutoEoiClear,
 254     NonSpecificEoi,
 255     InvalidEoiMode,
 256     SpecificEoi,
 257     RotateAutoEoiSet,
 258     RotateNonSpecific,
 259     SetPriority,
 260     RotateSpecific
 261 } I8259_EOI_MODE;
 262
 263 //
 264 // Definitions for ICW Registers
 265 //
 266 typedef union _I8259_ICW1
 267 {
 268     struct
 269     {
 270         UCHAR NeedIcw4:1;
 271         UCHAR OperatingMode:1;
 272         UCHAR Interval:1;
 273         UCHAR InterruptMode:1;
 274         UCHAR Init:1;
 275         UCHAR InterruptVectorAddress:3;
 276     };
 277     UCHAR Bits;
 278 } I8259_ICW1, *PI8259_ICW1;
 279
 280 typedef union _I8259_ICW2
 281 {
 282     struct
 283     {
 284         UCHAR Sbz:3;
 285         UCHAR InterruptVector:5;
 286     };
 287     UCHAR Bits;
 288 } I8259_ICW2, *PI8259_ICW2;
 289
 290 typedef union _I8259_ICW3
 291 {
 292     union
 293     {
 294         struct
 295         {
 296             UCHAR SlaveIrq0:1;
 297             UCHAR SlaveIrq1:1;
 298             UCHAR SlaveIrq2:1;
 299             UCHAR SlaveIrq3:1;
 300             UCHAR SlaveIrq4:1;
 301             UCHAR SlaveIrq5:1;
 302             UCHAR SlaveIrq6:1;
 303             UCHAR SlaveIrq7:1;
 304         };
 305         struct
 306         {
 307             UCHAR SlaveId:3;
 308             UCHAR Reserved:5;
 309         };
 310     };
 311     UCHAR Bits;
 312 } I8259_ICW3, *PI8259_ICW3;
 313
 314 typedef union _I8259_ICW4
 315 {
 316     struct
 317     {
 318         UCHAR SystemMode:1;
 319         UCHAR EoiMode:1;
 320         UCHAR BufferedMode:2;
 321         UCHAR SpecialFullyNestedMode:1;
 322         UCHAR Reserved:3;
 323     };
 324     UCHAR Bits;
 325 } I8259_ICW4, *PI8259_ICW4;
 326
 327 typedef union _I8259_OCW2
 328 {
 329     struct
 330     {
 331         UCHAR IrqNumber:3;
 332         UCHAR Sbz:2;
 333         UCHAR EoiMode:3;
 334     };
 335     UCHAR Bits;
 336 } I8259_OCW2, *PI8259_OCW2;
 337
 338 typedef union _I8259_OCW3
 339 {
 340     struct
 341     {
 342         UCHAR ReadRequest:2;
 343         UCHAR PollCommand:1;
 344         UCHAR Sbo:1;
 345         UCHAR Sbz:1;
 346         UCHAR SpecialMaskMode:2;
 347         UCHAR Reserved:1;
 348     };
 349     UCHAR Bits;
 350 } I8259_OCW3, *PI8259_OCW3;
 351
 352 typedef union _I8259_ISR
 353 {
 354     union
 355     {
 356         struct
 357         {
 358             UCHAR Irq0:1;
 359             UCHAR Irq1:1;
 360             UCHAR Irq2:1;
 361             UCHAR Irq3:1;
 362             UCHAR Irq4:1;
 363             UCHAR Irq5:1;
 364             UCHAR Irq6:1;
 365             UCHAR Irq7:1;
 366         };
 367     };
 368     UCHAR Bits;
 369 } I8259_ISR, *PI8259_ISR;
 370
 371 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 372
 373 //
 374 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 375 // P. 34, 35
 376 //
 377 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 378 //
 379 #define EISA_ELCR_MASTER       0x4D0
 380 #define EISA_ELCR_SLAVE        0x4D1
 381
 382 typedef union _EISA_ELCR
 383 {
 384     struct
 385     {
 386         struct
 387         {
 388             UCHAR Irq0Level:1;
 389             UCHAR Irq1Level:1;
 390             UCHAR Irq2Level:1;
 391             UCHAR Irq3Level:1;
 392             UCHAR Irq4Level:1;
 393             UCHAR Irq5Level:1;
 394             UCHAR Irq6Level:1;
 395             UCHAR Irq7Level:1;
 396         } Master;
 397         struct
 398         {
 399             UCHAR Irq8Level:1;
 400             UCHAR Irq9Level:1;
 401             UCHAR Irq10Level:1;
 402             UCHAR Irq11Level:1;
 403             UCHAR Irq12Level:1;
 404             UCHAR Irq13Level:1;
 405             UCHAR Irq14Level:1;
 406             UCHAR Irq15Level:1;
 407         } Slave;
 408     };
 409     USHORT Bits;
 410 } EISA_ELCR, *PEISA_ELCR;
 411
 412 typedef struct _PIC_MASK
 413 {
 414     union
 415     {
 416         struct
 417         {
 418             UCHAR Master;
 419             UCHAR Slave;
 420         };
 421         USHORT Both;
 422     };
 423 } PIC_MASK, *PPIC_MASK;
 424
 425 typedef
 426 BOOLEAN
 427 (NTAPI *PHAL_DISMISS_INTERRUPT)(
 428     IN KIRQL Irql,
 429     IN ULONG Irq,
 430     OUT PKIRQL OldIrql
 431 );
 432
 433 BOOLEAN
 434 NTAPI
 435 HalpDismissIrqGeneric(
 436     IN KIRQL Irql,
 437     IN ULONG Irq,
 438     OUT PKIRQL OldIrql
 439 );
 440
 441 BOOLEAN
 442 NTAPI
 443 HalpDismissIrq15(
 444     IN KIRQL Irql,
 445     IN ULONG Irq,
 446     OUT PKIRQL OldIrql
 447 );
 448
 449 BOOLEAN
 450 NTAPI
 451 HalpDismissIrq13(
 452     IN KIRQL Irql,
 453     IN ULONG Irq,
 454     OUT PKIRQL OldIrql
 455 );
 456
 457 BOOLEAN
 458 NTAPI
 459 HalpDismissIrq07(
 460     IN KIRQL Irql,
 461     IN ULONG Irq,
 462     OUT PKIRQL OldIrql
 463 );
 464
 465 BOOLEAN
 466 NTAPI
 467 HalpDismissIrqLevel(
 468     IN KIRQL Irql,
 469     IN ULONG Irq,
 470     OUT PKIRQL OldIrql
 471 );
 472
 473 BOOLEAN
 474 NTAPI
 475 HalpDismissIrq15Level(
 476     IN KIRQL Irql,
 477     IN ULONG Irq,
 478     OUT PKIRQL OldIrql
 479 );
 480
 481 BOOLEAN
 482 NTAPI
 483 HalpDismissIrq13Level(
 484     IN KIRQL Irql,
 485     IN ULONG Irq,
 486     OUT PKIRQL OldIrql
 487 );
 488
 489 BOOLEAN
 490 NTAPI
 491 HalpDismissIrq07Level(
 492     IN KIRQL Irql,
 493     IN ULONG Irq,
 494     OUT PKIRQL OldIrql
 495 );
 496
 497 VOID
 498 __cdecl
 499 HalpHardwareInterruptLevel(
 500     VOID
 501 );
 502
 503 //
 504 // Hack Flags
 505 //
 506 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 507 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 508 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 509
 510 //
 511 // Feature flags
 512 //
 513 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 514
 515 //
 516 // Match Flags
 517 //
 518 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 519 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 520 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 521
 522 //
 523 // Mm PTE/PDE to Hal PTE/PDE
 524 //
 525 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 526 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 527
 528 typedef struct _IDTUsageFlags
 529 {
 530     UCHAR Flags;
 531 } IDTUsageFlags;
 532
 533 typedef struct
 534 {
 535     KIRQL Irql;
 536     UCHAR BusReleativeVector;
 537 } IDTUsage;
 538
 539 typedef struct _HalAddressUsage
 540 {
 541     struct _HalAddressUsage *Next;
 542     CM_RESOURCE_TYPE Type;
 543     UCHAR Flags;
 544     struct
 545     {
 546         ULONG Start;
 547         ULONG Length;
 548     } Element[];
 549 } ADDRESS_USAGE, *PADDRESS_USAGE;
 550
 551 /* adapter.c */
 552 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 553
 554 /* sysinfo.c */
 555 VOID
 556 NTAPI
 557 HalpRegisterVector(IN UCHAR Flags,
 558                    IN ULONG BusVector,
 559                    IN ULONG SystemVector,
 560                    IN KIRQL Irql);
 561
 562 VOID
 563 NTAPI
 564 HalpEnableInterruptHandler(IN UCHAR Flags,
 565                            IN ULONG BusVector,
 566                            IN ULONG SystemVector,
 567                            IN KIRQL Irql,
 568                            IN PVOID Handler,
 569                            IN KINTERRUPT_MODE Mode);
 570
 571 /* pic.c */
 572 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 573 VOID __cdecl HalpApcInterrupt(VOID);
 574 VOID __cdecl HalpDispatchInterrupt(VOID);
 575 VOID __cdecl HalpDispatchInterrupt2(VOID);
 576 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 577 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 578
 579 /* profil.c */
 580 extern BOOLEAN HalpProfilingStopped;
 581
 582 /* timer.c */
 583 VOID NTAPI HalpInitializeClock(VOID);
 584 VOID __cdecl HalpClockInterrupt(VOID);
 585 VOID __cdecl HalpProfileInterrupt(VOID);
 586
 587 VOID
 588 NTAPI
 589 HalpCalibrateStallExecution(VOID);
 590
 591 /* pci.c */
 592 VOID HalpInitPciBus (VOID);
 593
 594 /* dma.c */
 595 VOID HalpInitDma (VOID);
 596
 597 /* Non-generic initialization */
 598 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 599 VOID HalpInitPhase1(VOID);
 600
 601 VOID
 602 NTAPI
 603 HalpFlushTLB(VOID);
 604
 605 //
 606 // KD Support
 607 //
 608 VOID
 609 NTAPI
 610 HalpCheckPowerButton(
 611     VOID
 612 );
 613
 614 VOID
 615 NTAPI
 616 HalpRegisterKdSupportFunctions(
 617     VOID
 618 );
 619
 620 NTSTATUS
 621 NTAPI
 622 HalpSetupPciDeviceForDebugging(
 623     IN PVOID LoaderBlock,
 624     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 625 );
 626
 627 NTSTATUS
 628 NTAPI
 629 HalpReleasePciDeviceForDebugging(
 630     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 631 );
 632
 633 //
 634 // Memory routines
 635 //
 636 ULONG_PTR
 637 NTAPI
 638 HalpAllocPhysicalMemory(
 639     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 640     IN ULONG_PTR MaxAddress,
 641     IN PFN_NUMBER PageCount,
 642     IN BOOLEAN Aligned
 643 );
 644
 645 PVOID
 646 NTAPI
 647 HalpMapPhysicalMemory64(
 648     IN PHYSICAL_ADDRESS PhysicalAddress,
 649     IN PFN_COUNT PageCount
 650 );
 651
 652 VOID
 653 NTAPI
 654 HalpUnmapVirtualAddress(
 655     IN PVOID VirtualAddress,
 656     IN PFN_COUNT NumberPages
 657 );
 658
 659 /* sysinfo.c */
 660 NTSTATUS
 661 NTAPI
 662 HaliQuerySystemInformation(
 663     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 664     IN ULONG BufferSize,
 665     IN OUT PVOID Buffer,
 666     OUT PULONG ReturnedLength
 667 );
 668
 669 NTSTATUS
 670 NTAPI
 671 HaliSetSystemInformation(
 672     IN HAL_SET_INFORMATION_CLASS InformationClass,
 673     IN ULONG BufferSize,
 674     IN OUT PVOID Buffer
 675 );
 676
 677 //
 678 // BIOS Routines
 679 //
 680 BOOLEAN
 681 NTAPI
 682 HalpBiosDisplayReset(
 683     VOID
 684 );
 685
 686 VOID
 687 FASTCALL
 688 HalpExitToV86(
 689     PKTRAP_FRAME TrapFrame
 690 );
 691
 692 VOID
 693 __cdecl
 694 HalpRealModeStart(
 695     VOID
 696 );
 697
 698 //
 699 // Processor Halt Routine
 700 //
 701 VOID
 702 NTAPI
 703 HaliHaltSystem(
 704     VOID
 705 );
 706
 707 //
 708 // CMOS Routines
 709 //
 710 VOID
 711 NTAPI
 712 HalpInitializeCmos(
 713     VOID
 714 );
 715
 716 UCHAR
 717 NTAPI
 718 HalpReadCmos(
 719     IN UCHAR Reg
 720 );
 721
 722 VOID
 723 NTAPI
 724 HalpWriteCmos(
 725     IN UCHAR Reg,
 726     IN UCHAR Value
 727 );
 728
 729 //
 730 // Spinlock for protecting CMOS access
 731 //
 732 VOID
 733 NTAPI
 734 HalpAcquireCmosSpinLock(
 735     VOID
 736 );
 737
 738 VOID
 739 NTAPI
 740 HalpReleaseCmosSpinLock(
 741     VOID
 742 );
 743
 744 NTSTATUS
 745 NTAPI
 746 HalpOpenRegistryKey(
 747     IN PHANDLE KeyHandle,
 748     IN HANDLE RootKey,
 749     IN PUNICODE_STRING KeyName,
 750     IN ACCESS_MASK DesiredAccess,
 751     IN BOOLEAN Create
 752 );
 753
 754 VOID
 755 NTAPI
 756 HalpGetNMICrashFlag(
 757     VOID
 758 );
 759
 760 BOOLEAN
 761 NTAPI
 762 HalpGetDebugPortTable(
 763     VOID
 764 );
 765
 766 VOID
 767 NTAPI
 768 HalpReportSerialNumber(
 769     VOID
 770 );
 771
 772 NTSTATUS
 773 NTAPI
 774 HalpMarkAcpiHal(
 775     VOID
 776 );
 777
 778 VOID
 779 NTAPI
 780 HalpBuildAddressMap(
 781     VOID
 782 );
 783
 784 VOID
 785 NTAPI
 786 HalpReportResourceUsage(
 787     IN PUNICODE_STRING HalName,
 788     IN INTERFACE_TYPE InterfaceType
 789 );
 790
 791 ULONG
 792 NTAPI
 793 HalpIs16BitPortDecodeSupported(
 794     VOID
 795 );
 796
 797 NTSTATUS
 798 NTAPI
 799 HalpQueryAcpiResourceRequirements(
 800     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 801 );
 802
 803 VOID
 804 FASTCALL
 805 KeUpdateSystemTime(
 806     IN PKTRAP_FRAME TrapFrame,
 807     IN ULONG Increment,
 808     IN KIRQL OldIrql
 809 );
 810
 811 VOID
 812 NTAPI
 813 HalpInitBusHandlers(
 814     VOID
 815 );
 816
 817 NTSTATUS
 818 NTAPI
 819 HaliInitPnpDriver(
 820     VOID
 821 );
 822
 823 VOID
 824 NTAPI
 825 HalpDebugPciDumpBus(
 826     IN ULONG i,
 827     IN ULONG j,
 828     IN ULONG k,
 829     IN PPCI_COMMON_CONFIG PciData
 830 );
 831
 832 VOID
 833 NTAPI
 834 HalpInitProcessor(
 835     IN ULONG ProcessorNumber,
 836     IN PLOADER_PARAMETER_BLOCK LoaderBlock
 837 );
 838
 839 #ifdef _M_AMD64
 840 #define KfLowerIrql KeLowerIrql
 841 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
 842 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
 843 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
 844 #ifndef CONFIG_SMP
 845 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 846 #define KiAcquireSpinLock(SpinLock)
 847 #define KiReleaseSpinLock(SpinLock)
 848 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 849 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 850 #endif // !CONFIG_SMP
 851 #endif // _M_AMD64
 852
 853 extern BOOLEAN HalpNMIInProgress;
 854
 855 extern ADDRESS_USAGE HalpDefaultIoSpace;
 856
 857 extern KSPIN_LOCK HalpSystemHardwareLock;
 858
 859 extern PADDRESS_USAGE HalpAddressUsageList;
 860
 861 extern LARGE_INTEGER HalpPerfCounter;
 862
 863 extern KAFFINITY HalpActiveProcessors;
 864
 865 extern BOOLEAN HalDisableFirmwareMapper;
 866 extern PWCHAR HalHardwareIdString;
 867 extern PWCHAR HalName;
 868
 869 extern KAFFINITY HalpDefaultInterruptAffinity;
 870
 871 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
 872
 873 extern const USHORT HalpBuildType;