7 typedef struct _HAL_BIOS_FRAME
14 PKTRAP_FRAME TrapFrame
;
22 } HAL_BIOS_FRAME
, *PHAL_BIOS_FRAME
;
26 (*PHAL_SW_INTERRUPT_HANDLER
)(
34 (*PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY
)(
35 IN PKTRAP_FRAME TrapFrame
38 #define HAL_APC_REQUEST 0
39 #define HAL_DPC_REQUEST 1
41 /* CMOS Registers and Ports */
42 #define CMOS_CONTROL_PORT (PUCHAR)0x70
43 #define CMOS_DATA_PORT (PUCHAR)0x71
44 #define RTC_REGISTER_A 0x0A
45 #define RTC_REGISTER_B 0x0B
46 #define RTC_REG_A_UIP 0x80
47 #define RTC_REGISTER_CENTURY 0x32
50 #define IDT_REGISTERED 0x01
51 #define IDT_LATCHED 0x02
52 #define IDT_READ_ONLY 0x04
53 #define IDT_INTERNAL 0x11
54 #define IDT_DEVICE 0x21
56 /* Conversion functions */
57 #define BCD_INT(bcd) \
58 (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
59 #define INT_BCD(int) \
60 (UCHAR)(((int / 10) << 4) + (int % 10))
65 #define VIDEO_SERVICES 0x10
68 // Operations for INT 10h (in AH)
70 #define SET_VIDEO_MODE 0x00
73 // Video Modes for INT10h AH=00 (in AL)
75 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
78 // Commonly stated as being 1.19318MHz
80 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
83 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
84 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
86 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
87 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
88 // infinite series) and divides it by three, one obtains 1.19318167.
90 // It may be that the original NT HAL source code introduced a typo and turned
91 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
92 // number is quite long.
94 #define PIT_FREQUENCY 1193182
97 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
99 #define TIMER_CHANNEL0_DATA_PORT 0x40
100 #define TIMER_CHANNEL1_DATA_PORT 0x41
101 #define TIMER_CHANNEL2_DATA_PORT 0x42
102 #define TIMER_CONTROL_PORT 0x43
105 // Mode 0 - Interrupt On Terminal Count
106 // Mode 1 - Hardware Re-triggerable One-Shot
107 // Mode 2 - Rate Generator
108 // Mode 3 - Square Wave Generator
109 // Mode 4 - Software Triggered Strobe
110 // Mode 5 - Hardware Triggered Strobe
112 typedef enum _TIMER_OPERATING_MODES
120 PitOperatingMode2Reserved
,
121 PitOperatingMode5Reserved
122 } TIMER_OPERATING_MODES
;
124 typedef enum _TIMER_ACCESS_MODES
126 PitAccessModeCounterLatch
,
130 } TIMER_ACCESS_MODES
;
132 typedef enum _TIMER_CHANNELS
140 typedef union _TIMER_CONTROL_PORT_REGISTER
145 TIMER_OPERATING_MODES OperatingMode
:3;
146 TIMER_ACCESS_MODES AccessMode
:2;
147 TIMER_CHANNELS Channel
:2;
150 } TIMER_CONTROL_PORT_REGISTER
, *PTIMER_CONTROL_PORT_REGISTER
;
153 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
156 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
158 #define SYSTEM_CONTROL_PORT_A 0x92
159 #define SYSTEM_CONTROL_PORT_B 0x61
160 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
164 UCHAR Timer2GateToSpeaker
:1;
165 UCHAR SpeakerDataEnable
:1;
166 UCHAR ParityCheckEnable
:1;
167 UCHAR ChannelCheckEnable
:1;
168 UCHAR RefreshRequest
:1;
169 UCHAR Timer2Output
:1;
170 UCHAR ChannelCheck
:1;
174 } SYSTEM_CONTROL_PORT_B_REGISTER
, *PSYSTEM_CONTROL_PORT_B_REGISTER
;
177 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
180 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
182 #define PIC1_CONTROL_PORT 0x20
183 #define PIC1_DATA_PORT 0x21
184 #define PIC2_CONTROL_PORT 0xA0
185 #define PIC2_DATA_PORT 0xA1
188 // Definitions for ICW/OCW Bits
190 typedef enum _I8259_ICW1_OPERATING_MODE
194 } I8259_ICW1_OPERATING_MODE
;
196 typedef enum _I8259_ICW1_INTERRUPT_MODE
200 } I8259_ICW1_INTERRUPT_MODE
;
202 typedef enum _I8259_ICW1_INTERVAL
206 } I8259_ICW1_INTERVAL
;
208 typedef enum _I8259_ICW4_SYSTEM_MODE
212 } I8259_ICW4_SYSTEM_MODE
;
214 typedef enum _I8259_ICW4_EOI_MODE
218 } I8259_ICW4_EOI_MODE
;
220 typedef enum _I8259_ICW4_BUFFERED_MODE
226 } I8259_ICW4_BUFFERED_MODE
;
228 typedef enum _I8259_READ_REQUEST
234 } I8259_READ_REQUEST
;
236 typedef enum _I8259_EOI_MODE
249 // Definitions for ICW Registers
251 typedef union _I8259_ICW1
256 I8259_ICW1_OPERATING_MODE OperatingMode
:1;
257 I8259_ICW1_INTERVAL Interval
:1;
258 I8259_ICW1_INTERRUPT_MODE InterruptMode
:1;
260 UCHAR InterruptVectorAddress
:3;
263 } I8259_ICW1
, *PI8259_ICW1
;
265 typedef union _I8259_ICW2
270 UCHAR InterruptVector
:5;
273 } I8259_ICW2
, *PI8259_ICW2
;
275 typedef union _I8259_ICW3
297 } I8259_ICW3
, *PI8259_ICW3
;
299 typedef union _I8259_ICW4
303 I8259_ICW4_SYSTEM_MODE SystemMode
:1;
304 I8259_ICW4_EOI_MODE EoiMode
:1;
305 I8259_ICW4_BUFFERED_MODE BufferedMode
:2;
306 UCHAR SpecialFullyNestedMode
:1;
310 } I8259_ICW4
, *PI8259_ICW4
;
312 typedef union _I8259_OCW2
318 I8259_EOI_MODE EoiMode
:3;
321 } I8259_OCW2
, *PI8259_OCW2
;
323 typedef union _I8259_OCW3
327 I8259_READ_REQUEST ReadRequest
:2;
331 UCHAR SpecialMaskMode
:2;
335 } I8259_OCW3
, *PI8259_OCW3
;
337 typedef union _I8259_ISR
354 } I8259_ISR
, *PI8259_ISR
;
356 typedef I8259_ISR I8259_IDR
, *PI8259_IDR
;
359 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
362 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
364 #define EISA_ELCR_MASTER 0x4D0
365 #define EISA_ELCR_SLAVE 0x4D1
367 typedef union _EISA_ELCR
395 } EISA_ELCR
, *PEISA_ELCR
;
397 typedef struct _PIC_MASK
408 } PIC_MASK
, *PPIC_MASK
;
412 __attribute__((regparm(3)))
413 (*PHAL_DISMISS_INTERRUPT
)(
420 __attribute__((regparm(3)))
421 HalpDismissIrqGeneric(
428 __attribute__((regparm(3)))
436 __attribute__((regparm(3)))
444 __attribute__((regparm(3)))
452 __attribute__((regparm(3)))
460 __attribute__((regparm(3)))
461 HalpDismissIrq15Level(
468 __attribute__((regparm(3)))
469 HalpDismissIrq13Level(
476 __attribute__((regparm(3)))
477 HalpDismissIrq07Level(
484 HalpHardwareInterruptLevel(
489 // Mm PTE/PDE to Hal PTE/PDE
491 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
492 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
494 typedef struct _IDTUsageFlags
502 UCHAR BusReleativeVector
;
505 typedef struct _HalAddressUsage
507 struct _HalAddressUsage
*Next
;
508 CM_RESOURCE_TYPE Type
;
515 } ADDRESS_USAGE
, *PADDRESS_USAGE
;
518 PADAPTER_OBJECT NTAPI
HalpAllocateAdapterEx(ULONG NumberOfMapRegisters
,BOOLEAN IsMaster
, BOOLEAN Dma32BitAddresses
);
523 HalpRegisterVector(IN UCHAR Flags
,
525 IN ULONG SystemVector
,
530 HalpEnableInterruptHandler(IN UCHAR Flags
,
532 IN ULONG SystemVector
,
535 IN KINTERRUPT_MODE Mode
);
538 VOID NTAPI
HalpInitializePICs(IN BOOLEAN EnableInterrupts
);
539 VOID
HalpApcInterrupt(VOID
);
540 VOID
HalpDispatchInterrupt(VOID
);
541 VOID
HalpDispatchInterrupt2(VOID
);
542 VOID FASTCALL DECLSPEC_NORETURN
HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame
);
543 VOID FASTCALL DECLSPEC_NORETURN
HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame
);
546 VOID NTAPI
HalpInitializeClock(VOID
);
547 VOID
HalpClockInterrupt(VOID
);
548 VOID
HalpProfileInterrupt(VOID
);
552 HalpCalibrateStallExecution(VOID
);
555 VOID
HalpInitPciBus (VOID
);
558 VOID
HalpInitDma (VOID
);
560 /* Non-generic initialization */
561 VOID
HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock
);
562 VOID
HalpInitPhase1(VOID
);
573 HalpCheckPowerButton(
579 HalpRegisterKdSupportFunctions(
585 HalpSetupPciDeviceForDebugging(
586 IN PVOID LoaderBlock
,
587 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
592 HalpReleasePciDeviceForDebugging(
593 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
601 HalpMapPhysicalMemory64(
602 IN PHYSICAL_ADDRESS PhysicalAddress
,
608 HalpUnmapVirtualAddress(
609 IN PVOID VirtualAddress
,
616 HaliQuerySystemInformation(
617 IN HAL_QUERY_INFORMATION_CLASS InformationClass
,
620 OUT PULONG ReturnedLength
625 HaliSetSystemInformation(
626 IN HAL_SET_INFORMATION_CLASS InformationClass
,
636 HalpBiosDisplayReset(
643 PKTRAP_FRAME TrapFrame
653 // Processor Halt Routine
662 // CMOS initialization
671 // Spinlock for protecting CMOS access
675 HalpAcquireSystemHardwareSpinLock(
681 HalpReleaseCmosSpinLock(
687 HalpAllocPhysicalMemory(
688 IN PLOADER_PARAMETER_BLOCK LoaderBlock
,
696 HalpMapPhysicalMemory64(
697 IN PHYSICAL_ADDRESS PhysicalAddress
,
704 IN PHANDLE KeyHandle
,
706 IN PUNICODE_STRING KeyName
,
707 IN ACCESS_MASK DesiredAccess
,
719 HalpGetDebugPortTable(
725 HalpReportSerialNumber(
743 HalpReportResourceUsage(
744 IN PUNICODE_STRING HalName
,
745 IN INTERFACE_TYPE InterfaceType
750 HalpIs16BitPortDecodeSupported(
756 HalpQueryAcpiResourceRequirements(
757 OUT PIO_RESOURCE_REQUIREMENTS_LIST
*Requirements
763 IN PKTRAP_FRAME TrapFrame
,
769 #define KfLowerIrql KeLowerIrql
771 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
772 #define KiAcquireSpinLock(SpinLock)
773 #define KiReleaseSpinLock(SpinLock)
774 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
775 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
776 #endif // !CONFIG_SMP
779 extern BOOLEAN HalpNMIInProgress
;
781 extern ADDRESS_USAGE HalpDefaultIoSpace
;
783 extern KSPIN_LOCK HalpSystemHardwareLock
;
785 extern PADDRESS_USAGE HalpAddressUsageList
;
787 extern LARGE_INTEGER HalpPerfCounter
;
789 extern KAFFINITY HalpActiveProcessors
;
791 extern BOOLEAN HalDisableFirmwareMapper
;
792 extern PWCHAR HalHardwareIdString
;
793 extern PWCHAR HalName
;