hal/halx86/include/halp.h

   1 /*
   2  *
   3  */
   4
   5 #pragma once
   6
   7
   8 #ifdef _MSC_VER
   9 #define REGISTERCALL FASTCALL
  10 #else
  11 #define REGISTERCALL __attribute__((regparm(3)))
  12 #endif
  13
  14 typedef struct _HAL_BIOS_FRAME
  15 {
  16     ULONG SegSs;
  17     ULONG Esp;
  18     ULONG EFlags;
  19     ULONG SegCs;
  20     ULONG Eip;
  21     PKTRAP_FRAME TrapFrame;
  22     ULONG CsLimit;
  23     ULONG CsBase;
  24     ULONG CsFlags;
  25     ULONG SsLimit;
  26     ULONG SsBase;
  27     ULONG SsFlags;
  28     ULONG Prefix;
  29 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
  30
  31 typedef
  32 VOID
  33 (*PHAL_SW_INTERRUPT_HANDLER)(
  34     VOID
  35 );
  36
  37 typedef
  38 VOID
  39 ATTRIB_NORETURN
  40 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
  41     IN PKTRAP_FRAME TrapFrame
  42 );
  43
  44 #define HAL_APC_REQUEST         0
  45 #define HAL_DPC_REQUEST         1
  46
  47 /* CMOS Registers and Ports */
  48 #define CMOS_CONTROL_PORT       (PUCHAR)0x70
  49 #define CMOS_DATA_PORT          (PUCHAR)0x71
  50 #define RTC_REGISTER_A          0x0A
  51 #define RTC_REGISTER_B          0x0B
  52 #define RTC_REG_A_UIP           0x80
  53 #define RTC_REGISTER_CENTURY    0x32
  54
  55 /* Usage flags */
  56 #define IDT_REGISTERED          0x01
  57 #define IDT_LATCHED             0x02
  58 #define IDT_READ_ONLY           0x04
  59 #define IDT_INTERNAL            0x11
  60 #define IDT_DEVICE              0x21
  61
  62 /* Conversion functions */
  63 #define BCD_INT(bcd)            \
  64     (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
  65 #define INT_BCD(int)            \
  66     (UCHAR)(((int / 10) << 4) + (int % 10))
  67
  68 //
  69 // BIOS Interrupts
  70 //
  71 #define VIDEO_SERVICES   0x10
  72
  73 //
  74 // Operations for INT 10h (in AH)
  75 //
  76 #define SET_VIDEO_MODE   0x00
  77
  78 //
  79 // Video Modes for INT10h AH=00 (in AL)
  80 //
  81 #define GRAPHICS_MODE_12 0x12           /* 80x30         8x16  640x480   16/256K */
  82
  83 //
  84 // Commonly stated as being 1.19318MHz
  85 //
  86 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
  87 // P. 471
  88 //
  89 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
  90 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
  91 //
  92 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
  93 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
  94 // infinite series) and divides it by three, one obtains 1.19318167.
  95 //
  96 // It may be that the original NT HAL source code introduced a typo and turned
  97 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
  98 // number is quite long.
  99 //
 100 #define PIT_FREQUENCY 1193182
 101
 102 //
 103 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
 104 //
 105 #define TIMER_CHANNEL0_DATA_PORT 0x40
 106 #define TIMER_CHANNEL1_DATA_PORT 0x41
 107 #define TIMER_CHANNEL2_DATA_PORT 0x42
 108 #define TIMER_CONTROL_PORT       0x43
 109
 110 //
 111 // Mode 0 - Interrupt On Terminal Count
 112 // Mode 1 - Hardware Re-triggerable One-Shot
 113 // Mode 2 - Rate Generator
 114 // Mode 3 - Square Wave Generator
 115 // Mode 4 - Software Triggered Strobe
 116 // Mode 5 - Hardware Triggered Strobe
 117 //
 118 typedef enum _TIMER_OPERATING_MODES
 119 {
 120     PitOperatingMode0,
 121     PitOperatingMode1,
 122     PitOperatingMode2,
 123     PitOperatingMode3,
 124     PitOperatingMode4,
 125     PitOperatingMode5,
 126     PitOperatingMode2Reserved,
 127     PitOperatingMode5Reserved
 128 } TIMER_OPERATING_MODES;
 129
 130 typedef enum _TIMER_ACCESS_MODES
 131 {
 132     PitAccessModeCounterLatch,
 133     PitAccessModeLow,
 134     PitAccessModeHigh,
 135     PitAccessModeLowHigh
 136 } TIMER_ACCESS_MODES;
 137
 138 typedef enum _TIMER_CHANNELS
 139 {
 140     PitChannel0,
 141     PitChannel1,
 142     PitChannel2,
 143     PitReadBack
 144 } TIMER_CHANNELS;
 145
 146 typedef union _TIMER_CONTROL_PORT_REGISTER
 147 {
 148     struct
 149     {
 150         UCHAR BcdMode:1;
 151         TIMER_OPERATING_MODES OperatingMode:3;
 152         TIMER_ACCESS_MODES AccessMode:2;
 153         TIMER_CHANNELS Channel:2;
 154     };
 155     UCHAR Bits;
 156 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
 157
 158 //
 159 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 160 // P. 400
 161 //
 162 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
 163 //
 164 #define SYSTEM_CONTROL_PORT_A   0x92
 165 #define SYSTEM_CONTROL_PORT_B   0x61
 166 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
 167 {
 168     struct
 169     {
 170         UCHAR Timer2GateToSpeaker:1;
 171         UCHAR SpeakerDataEnable:1;
 172         UCHAR ParityCheckEnable:1;
 173         UCHAR ChannelCheckEnable:1;
 174         UCHAR RefreshRequest:1;
 175         UCHAR Timer2Output:1;
 176         UCHAR ChannelCheck:1;
 177         UCHAR ParityCheck:1;
 178     };
 179     UCHAR Bits;
 180 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
 181
 182 //
 183 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
 184 // P. 396, 397
 185 //
 186 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
 187 //
 188 #define PIC1_CONTROL_PORT      0x20
 189 #define PIC1_DATA_PORT         0x21
 190 #define PIC2_CONTROL_PORT      0xA0
 191 #define PIC2_DATA_PORT         0xA1
 192
 193 //
 194 // Definitions for ICW/OCW Bits
 195 //
 196 typedef enum _I8259_ICW1_OPERATING_MODE
 197 {
 198     Cascade,
 199     Single
 200 } I8259_ICW1_OPERATING_MODE;
 201
 202 typedef enum _I8259_ICW1_INTERRUPT_MODE
 203 {
 204     EdgeTriggered,
 205     LevelTriggered
 206 } I8259_ICW1_INTERRUPT_MODE;
 207
 208 typedef enum _I8259_ICW1_INTERVAL
 209 {
 210     Interval8,
 211     Interval4
 212 } I8259_ICW1_INTERVAL;
 213
 214 typedef enum _I8259_ICW4_SYSTEM_MODE
 215 {
 216     Mcs8085Mode,
 217     New8086Mode
 218 } I8259_ICW4_SYSTEM_MODE;
 219
 220 typedef enum _I8259_ICW4_EOI_MODE
 221 {
 222     NormalEoi,
 223     AutomaticEoi
 224 } I8259_ICW4_EOI_MODE;
 225
 226 typedef enum _I8259_ICW4_BUFFERED_MODE
 227 {
 228     NonBuffered,
 229     NonBuffered2,
 230     BufferedSlave,
 231     BufferedMaster
 232 } I8259_ICW4_BUFFERED_MODE;
 233
 234 typedef enum _I8259_READ_REQUEST
 235 {
 236     InvalidRequest,
 237     InvalidRequest2,
 238     ReadIdr,
 239     ReadIsr
 240 } I8259_READ_REQUEST;
 241
 242 typedef enum _I8259_EOI_MODE
 243 {
 244     RotateAutoEoiClear,
 245     NonSpecificEoi,
 246     InvalidEoiMode,
 247     SpecificEoi,
 248     RotateAutoEoiSet,
 249     RotateNonSpecific,
 250     SetPriority,
 251     RotateSpecific
 252 } I8259_EOI_MODE;
 253
 254 //
 255 // Definitions for ICW Registers
 256 //
 257 typedef union _I8259_ICW1
 258 {
 259     struct
 260     {
 261         UCHAR NeedIcw4:1;
 262         I8259_ICW1_OPERATING_MODE OperatingMode:1;
 263         I8259_ICW1_INTERVAL Interval:1;
 264         I8259_ICW1_INTERRUPT_MODE InterruptMode:1;
 265         UCHAR Init:1;
 266         UCHAR InterruptVectorAddress:3;
 267     };
 268     UCHAR Bits;
 269 } I8259_ICW1, *PI8259_ICW1;
 270
 271 typedef union _I8259_ICW2
 272 {
 273     struct
 274     {
 275         UCHAR Sbz:3;
 276         UCHAR InterruptVector:5;
 277     };
 278     UCHAR Bits;
 279 } I8259_ICW2, *PI8259_ICW2;
 280
 281 typedef union _I8259_ICW3
 282 {
 283     union
 284     {
 285         struct
 286         {
 287             UCHAR SlaveIrq0:1;
 288             UCHAR SlaveIrq1:1;
 289             UCHAR SlaveIrq2:1;
 290             UCHAR SlaveIrq3:1;
 291             UCHAR SlaveIrq4:1;
 292             UCHAR SlaveIrq5:1;
 293             UCHAR SlaveIrq6:1;
 294             UCHAR SlaveIrq7:1;
 295         };
 296         struct
 297         {
 298             UCHAR SlaveId:3;
 299             UCHAR Reserved:5;
 300         };
 301     };
 302     UCHAR Bits;
 303 } I8259_ICW3, *PI8259_ICW3;
 304
 305 typedef union _I8259_ICW4
 306 {
 307     struct
 308     {
 309         I8259_ICW4_SYSTEM_MODE SystemMode:1;
 310         I8259_ICW4_EOI_MODE EoiMode:1;
 311         I8259_ICW4_BUFFERED_MODE BufferedMode:2;
 312         UCHAR SpecialFullyNestedMode:1;
 313         UCHAR Reserved:3;
 314     };
 315     UCHAR Bits;
 316 } I8259_ICW4, *PI8259_ICW4;
 317
 318 typedef union _I8259_OCW2
 319 {
 320     struct
 321     {
 322         UCHAR IrqNumber:3;
 323         UCHAR Sbz:2;
 324         I8259_EOI_MODE EoiMode:3;
 325     };
 326     UCHAR Bits;
 327 } I8259_OCW2, *PI8259_OCW2;
 328
 329 typedef union _I8259_OCW3
 330 {
 331     struct
 332     {
 333         I8259_READ_REQUEST ReadRequest:2;
 334         UCHAR PollCommand:1;
 335         UCHAR Sbo:1;
 336         UCHAR Sbz:1;
 337         UCHAR SpecialMaskMode:2;
 338         UCHAR Reserved:1;
 339     };
 340     UCHAR Bits;
 341 } I8259_OCW3, *PI8259_OCW3;
 342
 343 typedef union _I8259_ISR
 344 {
 345     union
 346     {
 347         struct
 348         {
 349             UCHAR Irq0:1;
 350             UCHAR Irq1:1;
 351             UCHAR Irq2:1;
 352             UCHAR Irq3:1;
 353             UCHAR Irq4:1;
 354             UCHAR Irq5:1;
 355             UCHAR Irq6:1;
 356             UCHAR Irq7:1;
 357         };
 358     };
 359     UCHAR Bits;
 360 } I8259_ISR, *PI8259_ISR;
 361
 362 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
 363
 364 //
 365 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
 366 // P. 34, 35
 367 //
 368 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
 369 //
 370 #define EISA_ELCR_MASTER       0x4D0
 371 #define EISA_ELCR_SLAVE        0x4D1
 372
 373 typedef union _EISA_ELCR
 374 {
 375     struct
 376     {
 377         struct
 378         {
 379             UCHAR Irq0Level:1;
 380             UCHAR Irq1Level:1;
 381             UCHAR Irq2Level:1;
 382             UCHAR Irq3Level:1;
 383             UCHAR Irq4Level:1;
 384             UCHAR Irq5Level:1;
 385             UCHAR Irq6Level:1;
 386             UCHAR Irq7Level:1;
 387         } Master;
 388         struct
 389         {
 390             UCHAR Irq8Level:1;
 391             UCHAR Irq9Level:1;
 392             UCHAR Irq10Level:1;
 393             UCHAR Irq11Level:1;
 394             UCHAR Irq12Level:1;
 395             UCHAR Irq13Level:1;
 396             UCHAR Irq14Level:1;
 397             UCHAR Irq15Level:1;
 398         } Slave;
 399     };
 400     USHORT Bits;
 401 } EISA_ELCR, *PEISA_ELCR;
 402
 403 typedef struct _PIC_MASK
 404 {
 405     union
 406     {
 407         struct
 408         {
 409             UCHAR Master;
 410             UCHAR Slave;
 411         };
 412         USHORT Both;
 413     };
 414 } PIC_MASK, *PPIC_MASK;
 415
 416 typedef
 417 BOOLEAN
 418 ( REGISTERCALL *PHAL_DISMISS_INTERRUPT)(
 419     IN KIRQL Irql,
 420     IN ULONG Irq,
 421     OUT PKIRQL OldIrql
 422 );
 423
 424 BOOLEAN
 425 REGISTERCALL
 426 HalpDismissIrqGeneric(
 427     IN KIRQL Irql,
 428     IN ULONG Irq,
 429     OUT PKIRQL OldIrql
 430 );
 431
 432 BOOLEAN
 433 REGISTERCALL
 434 HalpDismissIrq15(
 435     IN KIRQL Irql,
 436     IN ULONG Irq,
 437     OUT PKIRQL OldIrql
 438 );
 439
 440 BOOLEAN
 441 REGISTERCALL
 442 HalpDismissIrq13(
 443     IN KIRQL Irql,
 444     IN ULONG Irq,
 445     OUT PKIRQL OldIrql
 446 );
 447
 448 BOOLEAN
 449 REGISTERCALL
 450 HalpDismissIrq07(
 451     IN KIRQL Irql,
 452     IN ULONG Irq,
 453     OUT PKIRQL OldIrql
 454 );
 455
 456 BOOLEAN
 457 REGISTERCALL
 458 HalpDismissIrqLevel(
 459     IN KIRQL Irql,
 460     IN ULONG Irq,
 461     OUT PKIRQL OldIrql
 462 );
 463
 464 BOOLEAN
 465 REGISTERCALL
 466 HalpDismissIrq15Level(
 467     IN KIRQL Irql,
 468     IN ULONG Irq,
 469     OUT PKIRQL OldIrql
 470 );
 471
 472 BOOLEAN
 473 REGISTERCALL
 474 HalpDismissIrq13Level(
 475     IN KIRQL Irql,
 476     IN ULONG Irq,
 477     OUT PKIRQL OldIrql
 478 );
 479
 480 BOOLEAN
 481 REGISTERCALL
 482 HalpDismissIrq07Level(
 483     IN KIRQL Irql,
 484     IN ULONG Irq,
 485     OUT PKIRQL OldIrql
 486 );
 487
 488 VOID
 489 HalpHardwareInterruptLevel(
 490     VOID
 491 );
 492
 493 //
 494 // Hack Flags
 495 //
 496 #define HALP_REVISION_FROM_HACK_FLAGS(x)    ((x) >> 24)
 497 #define HALP_REVISION_HACK_FLAGS(x)         ((x) >> 12)
 498 #define HALP_HACK_FLAGS(x)                  ((x) & 0xFFF)
 499
 500 //
 501 // Feature flags
 502 //
 503 #define HALP_CARD_FEATURE_FULL_DECODE   0x0001
 504
 505 //
 506 // Match Flags
 507 //
 508 #define HALP_CHECK_CARD_REVISION_ID     0x10000
 509 #define HALP_CHECK_CARD_SUBVENDOR_ID    0x20000
 510 #define HALP_CHECK_CARD_SUBSYSTEM_ID    0x40000
 511
 512 //
 513 // Mm PTE/PDE to Hal PTE/PDE
 514 //
 515 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
 516 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
 517
 518 typedef struct _IDTUsageFlags
 519 {
 520     UCHAR Flags;
 521 } IDTUsageFlags;
 522
 523 typedef struct
 524 {
 525     KIRQL Irql;
 526     UCHAR BusReleativeVector;
 527 } IDTUsage;
 528
 529 typedef struct _HalAddressUsage
 530 {
 531     struct _HalAddressUsage *Next;
 532     CM_RESOURCE_TYPE Type;
 533     UCHAR Flags;
 534     struct
 535     {
 536         ULONG Start;
 537         ULONG Length;
 538     } Element[];
 539 } ADDRESS_USAGE, *PADDRESS_USAGE;
 540
 541 /* adapter.c */
 542 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
 543
 544 /* sysinfo.c */
 545 VOID
 546 NTAPI
 547 HalpRegisterVector(IN UCHAR Flags,
 548                    IN ULONG BusVector,
 549                    IN ULONG SystemVector,
 550                    IN KIRQL Irql);
 551
 552 VOID
 553 NTAPI
 554 HalpEnableInterruptHandler(IN UCHAR Flags,
 555                            IN ULONG BusVector,
 556                            IN ULONG SystemVector,
 557                            IN KIRQL Irql,
 558                            IN PVOID Handler,
 559                            IN KINTERRUPT_MODE Mode);
 560
 561 /* pic.c */
 562 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
 563 VOID HalpApcInterrupt(VOID);
 564 VOID HalpDispatchInterrupt(VOID);
 565 VOID HalpDispatchInterrupt2(VOID);
 566 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 567 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
 568
 569 /* timer.c */
 570 VOID NTAPI HalpInitializeClock(VOID);
 571 VOID HalpClockInterrupt(VOID);
 572 VOID HalpProfileInterrupt(VOID);
 573
 574 VOID
 575 NTAPI
 576 HalpCalibrateStallExecution(VOID);
 577
 578 /* pci.c */
 579 VOID HalpInitPciBus (VOID);
 580
 581 /* dma.c */
 582 VOID HalpInitDma (VOID);
 583
 584 /* Non-generic initialization */
 585 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
 586 VOID HalpInitPhase1(VOID);
 587
 588 VOID
 589 NTAPI
 590 HalpFlushTLB(VOID);
 591
 592 //
 593 // KD Support
 594 //
 595 VOID
 596 NTAPI
 597 HalpCheckPowerButton(
 598     VOID
 599 );
 600
 601 VOID
 602 NTAPI
 603 HalpRegisterKdSupportFunctions(
 604     VOID
 605 );
 606
 607 NTSTATUS
 608 NTAPI
 609 HalpSetupPciDeviceForDebugging(
 610     IN PVOID LoaderBlock,
 611     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 612 );
 613
 614 NTSTATUS
 615 NTAPI
 616 HalpReleasePciDeviceForDebugging(
 617     IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
 618 );
 619
 620 //
 621 // Memory routines
 622 //
 623 PVOID
 624 NTAPI
 625 HalpMapPhysicalMemory64(
 626     IN PHYSICAL_ADDRESS PhysicalAddress,
 627     IN ULONG NumberPage
 628 );
 629
 630 VOID
 631 NTAPI
 632 HalpUnmapVirtualAddress(
 633     IN PVOID VirtualAddress,
 634     IN ULONG NumberPages
 635 );
 636
 637 /* sysinfo.c */
 638 NTSTATUS
 639 NTAPI
 640 HaliQuerySystemInformation(
 641     IN HAL_QUERY_INFORMATION_CLASS InformationClass,
 642     IN ULONG BufferSize,
 643     IN OUT PVOID Buffer,
 644     OUT PULONG ReturnedLength
 645 );
 646
 647 NTSTATUS
 648 NTAPI
 649 HaliSetSystemInformation(
 650     IN HAL_SET_INFORMATION_CLASS InformationClass,
 651     IN ULONG BufferSize,
 652     IN OUT PVOID Buffer
 653 );
 654
 655 //
 656 // BIOS Routines
 657 //
 658 BOOLEAN
 659 NTAPI
 660 HalpBiosDisplayReset(
 661     VOID
 662 );
 663
 664 VOID
 665 FASTCALL
 666 HalpExitToV86(
 667     PKTRAP_FRAME TrapFrame
 668 );
 669
 670 VOID
 671 DECLSPEC_NORETURN
 672 HalpRealModeStart(
 673     VOID
 674 );
 675
 676 //
 677 // Processor Halt Routine
 678 //
 679 VOID
 680 NTAPI
 681 HaliHaltSystem(
 682     VOID
 683 );
 684
 685 //
 686 // CMOS initialization
 687 //
 688 VOID
 689 NTAPI
 690 HalpInitializeCmos(
 691     VOID
 692 );
 693
 694 //
 695 // Spinlock for protecting CMOS access
 696 //
 697 VOID
 698 NTAPI
 699 HalpAcquireSystemHardwareSpinLock(
 700     VOID
 701 );
 702
 703 VOID
 704 NTAPI
 705 HalpReleaseCmosSpinLock(
 706     VOID
 707 );
 708
 709 ULONG
 710 NTAPI
 711 HalpAllocPhysicalMemory(
 712     IN PLOADER_PARAMETER_BLOCK LoaderBlock,
 713     IN ULONG MaxAddress,
 714     IN ULONG PageCount,
 715     IN BOOLEAN Aligned
 716 );
 717
 718 PVOID
 719 NTAPI
 720 HalpMapPhysicalMemory64(
 721     IN PHYSICAL_ADDRESS PhysicalAddress,
 722     IN ULONG PageCount
 723 );
 724
 725 NTSTATUS
 726 NTAPI
 727 HalpOpenRegistryKey(
 728     IN PHANDLE KeyHandle,
 729     IN HANDLE RootKey,
 730     IN PUNICODE_STRING KeyName,
 731     IN ACCESS_MASK DesiredAccess,
 732     IN BOOLEAN Create
 733 );
 734
 735 VOID
 736 NTAPI
 737 HalpGetNMICrashFlag(
 738     VOID
 739 );
 740
 741 BOOLEAN
 742 NTAPI
 743 HalpGetDebugPortTable(
 744     VOID
 745 );
 746
 747 VOID
 748 NTAPI
 749 HalpReportSerialNumber(
 750     VOID
 751 );
 752
 753 NTSTATUS
 754 NTAPI
 755 HalpMarkAcpiHal(
 756     VOID
 757 );
 758
 759 VOID
 760 NTAPI
 761 HalpBuildAddressMap(
 762     VOID
 763 );
 764
 765 VOID
 766 NTAPI
 767 HalpReportResourceUsage(
 768     IN PUNICODE_STRING HalName,
 769     IN INTERFACE_TYPE InterfaceType
 770 );
 771
 772 ULONG
 773 NTAPI
 774 HalpIs16BitPortDecodeSupported(
 775     VOID
 776 );
 777
 778 NTSTATUS
 779 NTAPI
 780 HalpQueryAcpiResourceRequirements(
 781     OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
 782 );
 783
 784 VOID
 785 FASTCALL
 786 KeUpdateSystemTime(
 787     IN PKTRAP_FRAME TrapFrame,
 788     IN ULONG Increment,
 789     IN KIRQL OldIrql
 790 );
 791
 792 VOID
 793 NTAPI
 794 HalpInitBusHandlers(
 795     VOID
 796 );
 797
 798 NTSTATUS
 799 NTAPI
 800 HaliInitPnpDriver(
 801     VOID
 802 );
 803
 804 VOID
 805 NTAPI
 806 HalpDebugPciDumpBus(
 807     IN ULONG i,
 808     IN ULONG j,
 809     IN ULONG k,
 810     IN PPCI_COMMON_CONFIG PciData
 811 );
 812
 813 #ifdef _M_AMD64
 814 #define KfLowerIrql KeLowerIrql
 815 #ifndef CONFIG_SMP
 816 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
 817 #define KiAcquireSpinLock(SpinLock)
 818 #define KiReleaseSpinLock(SpinLock)
 819 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
 820 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
 821 #endif // !CONFIG_SMP
 822 #endif // _M_AMD64
 823
 824 extern BOOLEAN HalpNMIInProgress;
 825
 826 extern ADDRESS_USAGE HalpDefaultIoSpace;
 827
 828 extern KSPIN_LOCK HalpSystemHardwareLock;
 829
 830 extern PADDRESS_USAGE HalpAddressUsageList;
 831
 832 extern LARGE_INTEGER HalpPerfCounter;
 833
 834 extern KAFFINITY HalpActiveProcessors;
 835
 836 extern BOOLEAN HalDisableFirmwareMapper;
 837 extern PWCHAR HalHardwareIdString;
 838 extern PWCHAR HalName;
 839
 840 extern KAFFINITY HalpDefaultInterruptAffinity;
 841
 842 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR];
 843