[REGEDIT] Improve arrow button visual (#2133)
[reactos.git] / hal / halx86 / include / halp.h
1 /*
2 *
3 */
4
5 #pragma once
6
7 #ifdef CONFIG_SMP
8 #define HAL_BUILD_TYPE (DBG ? PRCB_BUILD_DEBUG : 0)
9 #else
10 #define HAL_BUILD_TYPE ((DBG ? PRCB_BUILD_DEBUG : 0) | PRCB_BUILD_UNIPROCESSOR)
11 #endif
12
13 typedef struct _HAL_BIOS_FRAME
14 {
15 ULONG SegSs;
16 ULONG Esp;
17 ULONG EFlags;
18 ULONG SegCs;
19 ULONG Eip;
20 PKTRAP_FRAME TrapFrame;
21 ULONG CsLimit;
22 ULONG CsBase;
23 ULONG CsFlags;
24 ULONG SsLimit;
25 ULONG SsBase;
26 ULONG SsFlags;
27 ULONG Prefix;
28 } HAL_BIOS_FRAME, *PHAL_BIOS_FRAME;
29
30 typedef
31 VOID
32 (__cdecl *PHAL_SW_INTERRUPT_HANDLER)(
33 VOID
34 );
35
36 typedef
37 VOID
38 (FASTCALL *PHAL_SW_INTERRUPT_HANDLER_2ND_ENTRY)(
39 IN PKTRAP_FRAME TrapFrame
40 );
41
42 #define HAL_APC_REQUEST 0
43 #define HAL_DPC_REQUEST 1
44
45 /* HAL profiling offsets in KeGetPcr()->HalReserved[] */
46 #define HAL_PROFILING_INTERVAL 0
47 #define HAL_PROFILING_MULTIPLIER 1
48
49 /* CMOS Registers and Ports */
50 #define CMOS_CONTROL_PORT (PUCHAR)0x70
51 #define CMOS_DATA_PORT (PUCHAR)0x71
52 #define RTC_REGISTER_A 0x0A
53 #define RTC_REG_A_UIP 0x80
54 #define RTC_REGISTER_B 0x0B
55 #define RTC_REG_B_PI 0x40
56 #define RTC_REGISTER_C 0x0C
57 #define RTC_REG_C_IRQ 0x80
58 #define RTC_REGISTER_D 0x0D
59 #define RTC_REGISTER_CENTURY 0x32
60
61 /* Usage flags */
62 #define IDT_REGISTERED 0x01
63 #define IDT_LATCHED 0x02
64 #define IDT_READ_ONLY 0x04
65 #define IDT_INTERNAL 0x11
66 #define IDT_DEVICE 0x21
67
68 /* Conversion functions */
69 #define BCD_INT(bcd) \
70 (((bcd & 0xF0) >> 4) * 10 + (bcd & 0x0F))
71 #define INT_BCD(int) \
72 (UCHAR)(((int / 10) << 4) + (int % 10))
73
74 //
75 // BIOS Interrupts
76 //
77 #define VIDEO_SERVICES 0x10
78
79 //
80 // Operations for INT 10h (in AH)
81 //
82 #define SET_VIDEO_MODE 0x00
83
84 //
85 // Video Modes for INT10h AH=00 (in AL)
86 //
87 #define GRAPHICS_MODE_12 0x12 /* 80x30 8x16 640x480 16/256K */
88
89 //
90 // Commonly stated as being 1.19318MHz
91 //
92 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
93 // P. 471
94 //
95 // However, the true value is closer to 1.19318181[...]81MHz since this is 1/3rd
96 // of the NTSC color subcarrier frequency which runs at 3.57954545[...]45MHz.
97 //
98 // Note that Windows uses 1.193167MHz which seems to have no basis. However, if
99 // one takes the NTSC color subcarrier frequency as being 3.579545 (trimming the
100 // infinite series) and divides it by three, one obtains 1.19318167.
101 //
102 // It may be that the original NT HAL source code introduced a typo and turned
103 // 119318167 into 1193167 by ommitting the "18". This is very plausible as the
104 // number is quite long.
105 //
106 #define PIT_FREQUENCY 1193182
107
108 //
109 // These ports are controlled by the i8254 Programmable Interrupt Timer (PIT)
110 //
111 #define TIMER_CHANNEL0_DATA_PORT 0x40
112 #define TIMER_CHANNEL1_DATA_PORT 0x41
113 #define TIMER_CHANNEL2_DATA_PORT 0x42
114 #define TIMER_CONTROL_PORT 0x43
115
116 //
117 // Mode 0 - Interrupt On Terminal Count
118 // Mode 1 - Hardware Re-triggerable One-Shot
119 // Mode 2 - Rate Generator
120 // Mode 3 - Square Wave Generator
121 // Mode 4 - Software Triggered Strobe
122 // Mode 5 - Hardware Triggered Strobe
123 //
124 typedef enum _TIMER_OPERATING_MODES
125 {
126 PitOperatingMode0,
127 PitOperatingMode1,
128 PitOperatingMode2,
129 PitOperatingMode3,
130 PitOperatingMode4,
131 PitOperatingMode5,
132 PitOperatingMode2Reserved,
133 PitOperatingMode5Reserved
134 } TIMER_OPERATING_MODES;
135
136 typedef enum _TIMER_ACCESS_MODES
137 {
138 PitAccessModeCounterLatch,
139 PitAccessModeLow,
140 PitAccessModeHigh,
141 PitAccessModeLowHigh
142 } TIMER_ACCESS_MODES;
143
144 typedef enum _TIMER_CHANNELS
145 {
146 PitChannel0,
147 PitChannel1,
148 PitChannel2,
149 PitReadBack
150 } TIMER_CHANNELS;
151
152 typedef union _TIMER_CONTROL_PORT_REGISTER
153 {
154 struct
155 {
156 UCHAR BcdMode:1;
157 UCHAR OperatingMode:3;
158 UCHAR AccessMode:2;
159 UCHAR Channel:2;
160 };
161 UCHAR Bits;
162 } TIMER_CONTROL_PORT_REGISTER, *PTIMER_CONTROL_PORT_REGISTER;
163
164 //
165 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
166 // P. 400
167 //
168 // This port is controled by the i8255 Programmable Peripheral Interface (PPI)
169 //
170 #define SYSTEM_CONTROL_PORT_A 0x92
171 #define SYSTEM_CONTROL_PORT_B 0x61
172 typedef union _SYSTEM_CONTROL_PORT_B_REGISTER
173 {
174 struct
175 {
176 UCHAR Timer2GateToSpeaker:1;
177 UCHAR SpeakerDataEnable:1;
178 UCHAR ParityCheckEnable:1;
179 UCHAR ChannelCheckEnable:1;
180 UCHAR RefreshRequest:1;
181 UCHAR Timer2Output:1;
182 UCHAR ChannelCheck:1;
183 UCHAR ParityCheck:1;
184 };
185 UCHAR Bits;
186 } SYSTEM_CONTROL_PORT_B_REGISTER, *PSYSTEM_CONTROL_PORT_B_REGISTER;
187
188 //
189 // See ISA System Architecture 3rd Edition (Tom Shanley, Don Anderson, John Swindle)
190 // P. 396, 397
191 //
192 // These ports are controlled by the i8259 Programmable Interrupt Controller (PIC)
193 //
194 #define PIC1_CONTROL_PORT 0x20
195 #define PIC1_DATA_PORT 0x21
196 #define PIC2_CONTROL_PORT 0xA0
197 #define PIC2_DATA_PORT 0xA1
198
199 //
200 // Definitions for ICW/OCW Bits
201 //
202 typedef enum _I8259_ICW1_OPERATING_MODE
203 {
204 Cascade,
205 Single
206 } I8259_ICW1_OPERATING_MODE;
207
208 typedef enum _I8259_ICW1_INTERRUPT_MODE
209 {
210 EdgeTriggered,
211 LevelTriggered
212 } I8259_ICW1_INTERRUPT_MODE;
213
214 typedef enum _I8259_ICW1_INTERVAL
215 {
216 Interval8,
217 Interval4
218 } I8259_ICW1_INTERVAL;
219
220 typedef enum _I8259_ICW4_SYSTEM_MODE
221 {
222 Mcs8085Mode,
223 New8086Mode
224 } I8259_ICW4_SYSTEM_MODE;
225
226 typedef enum _I8259_ICW4_EOI_MODE
227 {
228 NormalEoi,
229 AutomaticEoi
230 } I8259_ICW4_EOI_MODE;
231
232 typedef enum _I8259_ICW4_BUFFERED_MODE
233 {
234 NonBuffered,
235 NonBuffered2,
236 BufferedSlave,
237 BufferedMaster
238 } I8259_ICW4_BUFFERED_MODE;
239
240 typedef enum _I8259_READ_REQUEST
241 {
242 InvalidRequest,
243 InvalidRequest2,
244 ReadIdr,
245 ReadIsr
246 } I8259_READ_REQUEST;
247
248 typedef enum _I8259_EOI_MODE
249 {
250 RotateAutoEoiClear,
251 NonSpecificEoi,
252 InvalidEoiMode,
253 SpecificEoi,
254 RotateAutoEoiSet,
255 RotateNonSpecific,
256 SetPriority,
257 RotateSpecific
258 } I8259_EOI_MODE;
259
260 //
261 // Definitions for ICW Registers
262 //
263 typedef union _I8259_ICW1
264 {
265 struct
266 {
267 UCHAR NeedIcw4:1;
268 UCHAR OperatingMode:1;
269 UCHAR Interval:1;
270 UCHAR InterruptMode:1;
271 UCHAR Init:1;
272 UCHAR InterruptVectorAddress:3;
273 };
274 UCHAR Bits;
275 } I8259_ICW1, *PI8259_ICW1;
276
277 typedef union _I8259_ICW2
278 {
279 struct
280 {
281 UCHAR Sbz:3;
282 UCHAR InterruptVector:5;
283 };
284 UCHAR Bits;
285 } I8259_ICW2, *PI8259_ICW2;
286
287 typedef union _I8259_ICW3
288 {
289 union
290 {
291 struct
292 {
293 UCHAR SlaveIrq0:1;
294 UCHAR SlaveIrq1:1;
295 UCHAR SlaveIrq2:1;
296 UCHAR SlaveIrq3:1;
297 UCHAR SlaveIrq4:1;
298 UCHAR SlaveIrq5:1;
299 UCHAR SlaveIrq6:1;
300 UCHAR SlaveIrq7:1;
301 };
302 struct
303 {
304 UCHAR SlaveId:3;
305 UCHAR Reserved:5;
306 };
307 };
308 UCHAR Bits;
309 } I8259_ICW3, *PI8259_ICW3;
310
311 typedef union _I8259_ICW4
312 {
313 struct
314 {
315 UCHAR SystemMode:1;
316 UCHAR EoiMode:1;
317 UCHAR BufferedMode:2;
318 UCHAR SpecialFullyNestedMode:1;
319 UCHAR Reserved:3;
320 };
321 UCHAR Bits;
322 } I8259_ICW4, *PI8259_ICW4;
323
324 typedef union _I8259_OCW2
325 {
326 struct
327 {
328 UCHAR IrqNumber:3;
329 UCHAR Sbz:2;
330 UCHAR EoiMode:3;
331 };
332 UCHAR Bits;
333 } I8259_OCW2, *PI8259_OCW2;
334
335 typedef union _I8259_OCW3
336 {
337 struct
338 {
339 UCHAR ReadRequest:2;
340 UCHAR PollCommand:1;
341 UCHAR Sbo:1;
342 UCHAR Sbz:1;
343 UCHAR SpecialMaskMode:2;
344 UCHAR Reserved:1;
345 };
346 UCHAR Bits;
347 } I8259_OCW3, *PI8259_OCW3;
348
349 typedef union _I8259_ISR
350 {
351 union
352 {
353 struct
354 {
355 UCHAR Irq0:1;
356 UCHAR Irq1:1;
357 UCHAR Irq2:1;
358 UCHAR Irq3:1;
359 UCHAR Irq4:1;
360 UCHAR Irq5:1;
361 UCHAR Irq6:1;
362 UCHAR Irq7:1;
363 };
364 };
365 UCHAR Bits;
366 } I8259_ISR, *PI8259_ISR;
367
368 typedef I8259_ISR I8259_IDR, *PI8259_IDR;
369
370 //
371 // See EISA System Architecture 2nd Edition (Tom Shanley, Don Anderson, John Swindle)
372 // P. 34, 35
373 //
374 // These ports are controlled by the i8259A Programmable Interrupt Controller (PIC)
375 //
376 #define EISA_ELCR_MASTER 0x4D0
377 #define EISA_ELCR_SLAVE 0x4D1
378
379 typedef union _EISA_ELCR
380 {
381 struct
382 {
383 struct
384 {
385 UCHAR Irq0Level:1;
386 UCHAR Irq1Level:1;
387 UCHAR Irq2Level:1;
388 UCHAR Irq3Level:1;
389 UCHAR Irq4Level:1;
390 UCHAR Irq5Level:1;
391 UCHAR Irq6Level:1;
392 UCHAR Irq7Level:1;
393 } Master;
394 struct
395 {
396 UCHAR Irq8Level:1;
397 UCHAR Irq9Level:1;
398 UCHAR Irq10Level:1;
399 UCHAR Irq11Level:1;
400 UCHAR Irq12Level:1;
401 UCHAR Irq13Level:1;
402 UCHAR Irq14Level:1;
403 UCHAR Irq15Level:1;
404 } Slave;
405 };
406 USHORT Bits;
407 } EISA_ELCR, *PEISA_ELCR;
408
409 typedef struct _PIC_MASK
410 {
411 union
412 {
413 struct
414 {
415 UCHAR Master;
416 UCHAR Slave;
417 };
418 USHORT Both;
419 };
420 } PIC_MASK, *PPIC_MASK;
421
422 typedef
423 BOOLEAN
424 (NTAPI *PHAL_DISMISS_INTERRUPT)(
425 IN KIRQL Irql,
426 IN ULONG Irq,
427 OUT PKIRQL OldIrql
428 );
429
430 BOOLEAN
431 NTAPI
432 HalpDismissIrqGeneric(
433 IN KIRQL Irql,
434 IN ULONG Irq,
435 OUT PKIRQL OldIrql
436 );
437
438 BOOLEAN
439 NTAPI
440 HalpDismissIrq15(
441 IN KIRQL Irql,
442 IN ULONG Irq,
443 OUT PKIRQL OldIrql
444 );
445
446 BOOLEAN
447 NTAPI
448 HalpDismissIrq13(
449 IN KIRQL Irql,
450 IN ULONG Irq,
451 OUT PKIRQL OldIrql
452 );
453
454 BOOLEAN
455 NTAPI
456 HalpDismissIrq07(
457 IN KIRQL Irql,
458 IN ULONG Irq,
459 OUT PKIRQL OldIrql
460 );
461
462 BOOLEAN
463 NTAPI
464 HalpDismissIrqLevel(
465 IN KIRQL Irql,
466 IN ULONG Irq,
467 OUT PKIRQL OldIrql
468 );
469
470 BOOLEAN
471 NTAPI
472 HalpDismissIrq15Level(
473 IN KIRQL Irql,
474 IN ULONG Irq,
475 OUT PKIRQL OldIrql
476 );
477
478 BOOLEAN
479 NTAPI
480 HalpDismissIrq13Level(
481 IN KIRQL Irql,
482 IN ULONG Irq,
483 OUT PKIRQL OldIrql
484 );
485
486 BOOLEAN
487 NTAPI
488 HalpDismissIrq07Level(
489 IN KIRQL Irql,
490 IN ULONG Irq,
491 OUT PKIRQL OldIrql
492 );
493
494 VOID
495 __cdecl
496 HalpHardwareInterruptLevel(
497 VOID
498 );
499
500 //
501 // Hack Flags
502 //
503 #define HALP_REVISION_FROM_HACK_FLAGS(x) ((x) >> 24)
504 #define HALP_REVISION_HACK_FLAGS(x) ((x) >> 12)
505 #define HALP_HACK_FLAGS(x) ((x) & 0xFFF)
506
507 //
508 // Feature flags
509 //
510 #define HALP_CARD_FEATURE_FULL_DECODE 0x0001
511
512 //
513 // Match Flags
514 //
515 #define HALP_CHECK_CARD_REVISION_ID 0x10000
516 #define HALP_CHECK_CARD_SUBVENDOR_ID 0x20000
517 #define HALP_CHECK_CARD_SUBSYSTEM_ID 0x40000
518
519 //
520 // Mm PTE/PDE to Hal PTE/PDE
521 //
522 #define HalAddressToPde(x) (PHARDWARE_PTE)MiAddressToPde(x)
523 #define HalAddressToPte(x) (PHARDWARE_PTE)MiAddressToPte(x)
524
525 typedef struct _IDTUsageFlags
526 {
527 UCHAR Flags;
528 } IDTUsageFlags;
529
530 typedef struct
531 {
532 KIRQL Irql;
533 UCHAR BusReleativeVector;
534 } IDTUsage;
535
536 typedef struct _HalAddressUsage
537 {
538 struct _HalAddressUsage *Next;
539 CM_RESOURCE_TYPE Type;
540 UCHAR Flags;
541 struct
542 {
543 ULONG Start;
544 ULONG Length;
545 } Element[];
546 } ADDRESS_USAGE, *PADDRESS_USAGE;
547
548 /* adapter.c */
549 PADAPTER_OBJECT NTAPI HalpAllocateAdapterEx(ULONG NumberOfMapRegisters,BOOLEAN IsMaster, BOOLEAN Dma32BitAddresses);
550
551 /* sysinfo.c */
552 INIT_FUNCTION
553 VOID
554 NTAPI
555 HalpRegisterVector(IN UCHAR Flags,
556 IN ULONG BusVector,
557 IN ULONG SystemVector,
558 IN KIRQL Irql);
559
560 INIT_FUNCTION
561 VOID
562 NTAPI
563 HalpEnableInterruptHandler(IN UCHAR Flags,
564 IN ULONG BusVector,
565 IN ULONG SystemVector,
566 IN KIRQL Irql,
567 IN PVOID Handler,
568 IN KINTERRUPT_MODE Mode);
569
570 /* pic.c */
571 VOID NTAPI HalpInitializePICs(IN BOOLEAN EnableInterrupts);
572 VOID __cdecl HalpApcInterrupt(VOID);
573 VOID __cdecl HalpDispatchInterrupt(VOID);
574 PHAL_SW_INTERRUPT_HANDLER __cdecl HalpDispatchInterrupt2(VOID);
575 DECLSPEC_NORETURN VOID FASTCALL HalpApcInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
576 DECLSPEC_NORETURN VOID FASTCALL HalpDispatchInterrupt2ndEntry(IN PKTRAP_FRAME TrapFrame);
577
578 /* profil.c */
579 extern BOOLEAN HalpProfilingStopped;
580
581 /* timer.c */
582 INIT_FUNCTION VOID NTAPI HalpInitializeClock(VOID);
583 VOID __cdecl HalpClockInterrupt(VOID);
584 VOID __cdecl HalpProfileInterrupt(VOID);
585
586 VOID
587 NTAPI
588 HalpCalibrateStallExecution(VOID);
589
590 /* pci.c */
591 VOID HalpInitPciBus (VOID);
592
593 /* dma.c */
594 INIT_FUNCTION VOID HalpInitDma (VOID);
595
596 /* Non-generic initialization */
597 VOID HalpInitPhase0 (PLOADER_PARAMETER_BLOCK LoaderBlock);
598 VOID HalpInitPhase1(VOID);
599
600 VOID
601 NTAPI
602 HalpFlushTLB(VOID);
603
604 //
605 // KD Support
606 //
607 VOID
608 NTAPI
609 HalpCheckPowerButton(
610 VOID
611 );
612
613 INIT_FUNCTION
614 VOID
615 NTAPI
616 HalpRegisterKdSupportFunctions(
617 VOID
618 );
619
620 INIT_FUNCTION
621 NTSTATUS
622 NTAPI
623 HalpSetupPciDeviceForDebugging(
624 IN PVOID LoaderBlock,
625 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
626 );
627
628 INIT_FUNCTION
629 NTSTATUS
630 NTAPI
631 HalpReleasePciDeviceForDebugging(
632 IN OUT PDEBUG_DEVICE_DESCRIPTOR PciDevice
633 );
634
635 //
636 // Memory routines
637 //
638 ULONG64
639 NTAPI
640 HalpAllocPhysicalMemory(
641 IN PLOADER_PARAMETER_BLOCK LoaderBlock,
642 IN ULONG64 MaxAddress,
643 IN PFN_NUMBER PageCount,
644 IN BOOLEAN Aligned
645 );
646
647 PVOID
648 NTAPI
649 HalpMapPhysicalMemory64Vista(
650 IN PHYSICAL_ADDRESS PhysicalAddress,
651 IN PFN_COUNT PageCount,
652 IN BOOLEAN FlushCurrentTLB
653 );
654
655 VOID
656 NTAPI
657 HalpUnmapVirtualAddressVista(
658 IN PVOID VirtualAddress,
659 IN PFN_COUNT NumberPages,
660 IN BOOLEAN FlushCurrentTLB
661 );
662
663 PVOID
664 NTAPI
665 HalpMapPhysicalMemory64(
666 IN PHYSICAL_ADDRESS PhysicalAddress,
667 IN PFN_COUNT PageCount
668 );
669
670 VOID
671 NTAPI
672 HalpUnmapVirtualAddress(
673 IN PVOID VirtualAddress,
674 IN PFN_COUNT NumberPages
675 );
676
677 /* sysinfo.c */
678 NTSTATUS
679 NTAPI
680 HaliQuerySystemInformation(
681 IN HAL_QUERY_INFORMATION_CLASS InformationClass,
682 IN ULONG BufferSize,
683 IN OUT PVOID Buffer,
684 OUT PULONG ReturnedLength
685 );
686
687 NTSTATUS
688 NTAPI
689 HaliSetSystemInformation(
690 IN HAL_SET_INFORMATION_CLASS InformationClass,
691 IN ULONG BufferSize,
692 IN OUT PVOID Buffer
693 );
694
695 //
696 // BIOS Routines
697 //
698 BOOLEAN
699 NTAPI
700 HalpBiosDisplayReset(
701 VOID
702 );
703
704 VOID
705 FASTCALL
706 HalpExitToV86(
707 PKTRAP_FRAME TrapFrame
708 );
709
710 VOID
711 __cdecl
712 HalpRealModeStart(
713 VOID
714 );
715
716 //
717 // Processor Halt Routine
718 //
719 VOID
720 NTAPI
721 HaliHaltSystem(
722 VOID
723 );
724
725 //
726 // CMOS Routines
727 //
728 INIT_FUNCTION
729 VOID
730 NTAPI
731 HalpInitializeCmos(
732 VOID
733 );
734
735 UCHAR
736 NTAPI
737 HalpReadCmos(
738 IN UCHAR Reg
739 );
740
741 VOID
742 NTAPI
743 HalpWriteCmos(
744 IN UCHAR Reg,
745 IN UCHAR Value
746 );
747
748 //
749 // Spinlock for protecting CMOS access
750 //
751 VOID
752 NTAPI
753 HalpAcquireCmosSpinLock(
754 VOID
755 );
756
757 VOID
758 NTAPI
759 HalpReleaseCmosSpinLock(
760 VOID
761 );
762
763 VOID
764 NTAPI
765 HalpInitializeLegacyPICs(
766 VOID
767 );
768
769 NTSTATUS
770 NTAPI
771 HalpOpenRegistryKey(
772 IN PHANDLE KeyHandle,
773 IN HANDLE RootKey,
774 IN PUNICODE_STRING KeyName,
775 IN ACCESS_MASK DesiredAccess,
776 IN BOOLEAN Create
777 );
778
779 INIT_FUNCTION
780 VOID
781 NTAPI
782 HalpGetNMICrashFlag(
783 VOID
784 );
785
786 INIT_FUNCTION
787 BOOLEAN
788 NTAPI
789 HalpGetDebugPortTable(
790 VOID
791 );
792
793 INIT_FUNCTION
794 VOID
795 NTAPI
796 HalpReportSerialNumber(
797 VOID
798 );
799
800 INIT_FUNCTION
801 NTSTATUS
802 NTAPI
803 HalpMarkAcpiHal(
804 VOID
805 );
806
807 INIT_FUNCTION
808 VOID
809 NTAPI
810 HalpBuildAddressMap(
811 VOID
812 );
813
814 INIT_FUNCTION
815 VOID
816 NTAPI
817 HalpReportResourceUsage(
818 IN PUNICODE_STRING HalName,
819 IN INTERFACE_TYPE InterfaceType
820 );
821
822 INIT_FUNCTION
823 ULONG
824 NTAPI
825 HalpIs16BitPortDecodeSupported(
826 VOID
827 );
828
829 NTSTATUS
830 NTAPI
831 HalpQueryAcpiResourceRequirements(
832 OUT PIO_RESOURCE_REQUIREMENTS_LIST *Requirements
833 );
834
835 VOID
836 FASTCALL
837 KeUpdateSystemTime(
838 IN PKTRAP_FRAME TrapFrame,
839 IN ULONG Increment,
840 IN KIRQL OldIrql
841 );
842
843 INIT_FUNCTION
844 VOID
845 NTAPI
846 HalpInitBusHandlers(
847 VOID
848 );
849
850 NTSTATUS
851 NTAPI
852 HaliInitPnpDriver(
853 VOID
854 );
855
856 INIT_FUNCTION
857 VOID
858 NTAPI
859 HalpDebugPciDumpBus(
860 IN ULONG i,
861 IN ULONG j,
862 IN ULONG k,
863 IN PPCI_COMMON_CONFIG PciData
864 );
865
866 VOID
867 NTAPI
868 HalpInitProcessor(
869 IN ULONG ProcessorNumber,
870 IN PLOADER_PARAMETER_BLOCK LoaderBlock
871 );
872
873 #ifdef _M_AMD64
874
875 VOID
876 NTAPI
877 HalInitializeBios(
878 _In_ ULONG Unknown,
879 _In_ PLOADER_PARAMETER_BLOCK LoaderBlock
880 );
881
882 #define KfLowerIrql KeLowerIrql
883 #define KiEnterInterruptTrap(TrapFrame) /* We do all neccessary in asm code */
884 #define KiEoiHelper(TrapFrame) return /* Just return to the caller */
885 #define HalBeginSystemInterrupt(Irql, Vector, OldIrql) ((*(OldIrql) = PASSIVE_LEVEL), TRUE)
886 #ifndef CONFIG_SMP
887 /* On UP builds, spinlocks don't exist at IRQL >= DISPATCH */
888 #define KiAcquireSpinLock(SpinLock)
889 #define KiReleaseSpinLock(SpinLock)
890 #define KfAcquireSpinLock(SpinLock) KfRaiseIrql(DISPATCH_LEVEL);
891 #define KfReleaseSpinLock(SpinLock, OldIrql) KeLowerIrql(OldIrql);
892 #endif // !CONFIG_SMP
893 #endif // _M_AMD64
894
895 extern BOOLEAN HalpNMIInProgress;
896
897 extern ADDRESS_USAGE HalpDefaultIoSpace;
898
899 extern KSPIN_LOCK HalpSystemHardwareLock;
900
901 extern PADDRESS_USAGE HalpAddressUsageList;
902
903 extern LARGE_INTEGER HalpPerfCounter;
904
905 extern KAFFINITY HalpActiveProcessors;
906
907 extern BOOLEAN HalDisableFirmwareMapper;
908 extern PWCHAR HalHardwareIdString;
909 extern PWCHAR HalName;
910
911 extern KAFFINITY HalpDefaultInterruptAffinity;
912
913 extern IDTUsageFlags HalpIDTUsageFlags[MAXIMUM_IDTVECTOR+1];
914
915 extern const USHORT HalpBuildType;