include/psdk/cvconst.h

   1 /*
   2  * File cvconst.h - MS debug information
   3  *
   4  * Copyright (C) 2004, Eric Pouech
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
  19  */
  20
  21 /* information in this file is highly derived from MSDN DIA information pages */
  22
  23 /* symbols & types enumeration */
  24 enum SymTagEnum
  25 {
  26    SymTagNull,
  27    SymTagExe,
  28    SymTagCompiland,
  29    SymTagCompilandDetails,
  30    SymTagCompilandEnv,
  31    SymTagFunction,
  32    SymTagBlock,
  33    SymTagData,
  34    SymTagAnnotation,
  35    SymTagLabel,
  36    SymTagPublicSymbol,
  37    SymTagUDT,
  38    SymTagEnum,
  39    SymTagFunctionType,
  40    SymTagPointerType,
  41    SymTagArrayType,
  42    SymTagBaseType,
  43    SymTagTypedef,
  44    SymTagBaseClass,
  45    SymTagFriend,
  46    SymTagFunctionArgType,
  47    SymTagFuncDebugStart,
  48    SymTagFuncDebugEnd,
  49    SymTagUsingNamespace,
  50    SymTagVTableShape,
  51    SymTagVTable,
  52    SymTagCustom,
  53    SymTagThunk,
  54    SymTagCustomType,
  55    SymTagManagedType,
  56    SymTagDimension,
  57    SymTagMax
  58 };
  59
  60 enum BasicType
  61 {
  62     btNoType = 0,
  63     btVoid = 1,
  64     btChar = 2,
  65     btWChar = 3,
  66     btInt = 6,
  67     btUInt = 7,
  68     btFloat = 8,
  69     btBCD = 9,
  70     btBool = 10,
  71     btLong = 13,
  72     btULong = 14,
  73     btCurrency = 25,
  74     btDate = 26,
  75     btVariant = 27,
  76     btComplex = 28,
  77     btBit = 29,
  78     btBSTR = 30,
  79     btHresult = 31,
  80 };
  81
  82 /* kind of UDT */
  83 enum UdtKind
  84 {
  85     UdtStruct,
  86     UdtClass,
  87     UdtUnion
  88 };
  89
  90 /* where a SymTagData is */
  91 enum LocationType
  92 {
  93     LocIsNull,
  94     LocIsStatic,
  95     LocIsTLS,
  96     LocIsRegRel,
  97     LocIsThisRel,
  98     LocIsEnregistered,
  99     LocIsBitField,
 100     LocIsSlot,
 101     LocIsIlRel,
 102     LocInMetaData,
 103     LocIsConstant
 104 };
 105
 106 /* kind of SymTagData */
 107 enum DataKind
 108 {
 109     DataIsUnknown,
 110     DataIsLocal,
 111     DataIsStaticLocal,
 112     DataIsParam,
 113     DataIsObjectPtr,
 114     DataIsFileStatic,
 115     DataIsGlobal,
 116     DataIsMember,
 117     DataIsStaticMember,
 118     DataIsConstant
 119 };
 120
 121 /* values for registers (on different CPUs) */
 122 enum CV_HREG_e
 123 {
 124     /* those values are common to all supported CPUs (and CPU independent) */
 125     CV_ALLREG_ERR       = 30000,
 126     CV_ALLREG_TEB       = 30001,
 127     CV_ALLREG_TIMER     = 30002,
 128     CV_ALLREG_EFAD1     = 30003,
 129     CV_ALLREG_EFAD2     = 30004,
 130     CV_ALLREG_EFAD3     = 30005,
 131     CV_ALLREG_VFRAME    = 30006,
 132     CV_ALLREG_HANDLE    = 30007,
 133     CV_ALLREG_PARAMS    = 30008,
 134     CV_ALLREG_LOCALS    = 30009,
 135
 136     /* Intel x86 CPU */
 137     CV_REG_NONE         = 0,
 138     CV_REG_AL           = 1,
 139     CV_REG_CL           = 2,
 140     CV_REG_DL           = 3,
 141     CV_REG_BL           = 4,
 142     CV_REG_AH           = 5,
 143     CV_REG_CH           = 6,
 144     CV_REG_DH           = 7,
 145     CV_REG_BH           = 8,
 146     CV_REG_AX           = 9,
 147     CV_REG_CX           = 10,
 148     CV_REG_DX           = 11,
 149     CV_REG_BX           = 12,
 150     CV_REG_SP           = 13,
 151     CV_REG_BP           = 14,
 152     CV_REG_SI           = 15,
 153     CV_REG_DI           = 16,
 154     CV_REG_EAX          = 17,
 155     CV_REG_ECX          = 18,
 156     CV_REG_EDX          = 19,
 157     CV_REG_EBX          = 20,
 158     CV_REG_ESP          = 21,
 159     CV_REG_EBP          = 22,
 160     CV_REG_ESI          = 23,
 161     CV_REG_EDI          = 24,
 162     CV_REG_ES           = 25,
 163     CV_REG_CS           = 26,
 164     CV_REG_SS           = 27,
 165     CV_REG_DS           = 28,
 166     CV_REG_FS           = 29,
 167     CV_REG_GS           = 30,
 168     CV_REG_IP           = 31,
 169     CV_REG_FLAGS        = 32,
 170     CV_REG_EIP          = 33,
 171     CV_REG_EFLAGS       = 34,
 172
 173     /* <pcode> */
 174     CV_REG_TEMP         = 40,
 175     CV_REG_TEMPH        = 41,
 176     CV_REG_QUOTE        = 42,
 177     CV_REG_PCDR3        = 43,   /* this includes PCDR4 to PCDR7 */
 178     CV_REG_CR0          = 80,   /* this includes CR1 to CR4 */
 179     CV_REG_DR0          = 90,   /* this includes DR1 to DR7 */
 180     /* </pcode> */
 181
 182     CV_REG_GDTR         = 110,
 183     CV_REG_GDTL         = 111,
 184     CV_REG_IDTR         = 112,
 185     CV_REG_IDTL         = 113,
 186     CV_REG_LDTR         = 114,
 187     CV_REG_TR           = 115,
 188
 189     CV_REG_PSEUDO1      = 116, /* this includes Pseudo02 to Pseudo09 */
 190     CV_REG_ST0          = 128, /* this includes ST1 to ST7 */
 191     CV_REG_CTRL         = 136,
 192     CV_REG_STAT         = 137,
 193     CV_REG_TAG          = 138,
 194     CV_REG_FPIP         = 139,
 195     CV_REG_FPCS         = 140,
 196     CV_REG_FPDO         = 141,
 197     CV_REG_FPDS         = 142,
 198     CV_REG_ISEM         = 143,
 199     CV_REG_FPEIP        = 144,
 200     CV_REG_FPEDO        = 145,
 201     CV_REG_MM0          = 146, /* this includes MM1 to MM7 */
 202     CV_REG_XMM0         = 154, /* this includes XMM1 to XMM7 */
 203     CV_REG_XMM00        = 162,
 204     CV_REG_XMM0L        = 194, /* this includes XMM1L to XMM7L */
 205     CV_REG_XMM0H        = 202, /* this includes XMM1H to XMM7H */
 206     CV_REG_MXCSR        = 211,
 207     CV_REG_EDXEAX       = 212,
 208     CV_REG_EMM0L        = 220,
 209     CV_REG_EMM0H        = 228,
 210     CV_REG_MM00         = 236,
 211     CV_REG_MM01         = 237,
 212     CV_REG_MM10         = 238,
 213     CV_REG_MM11         = 239,
 214     CV_REG_MM20         = 240,
 215     CV_REG_MM21         = 241,
 216     CV_REG_MM30         = 242,
 217     CV_REG_MM31         = 243,
 218     CV_REG_MM40         = 244,
 219     CV_REG_MM41         = 245,
 220     CV_REG_MM50         = 246,
 221     CV_REG_MM51         = 247,
 222     CV_REG_MM60         = 248,
 223     CV_REG_MM61         = 249,
 224     CV_REG_MM70         = 250,
 225     CV_REG_MM71         = 251,
 226
 227     /* Motorola 68K CPU */
 228     CV_R68_D0           = 0, /* this includes D1 to D7 too */
 229     CV_R68_A0           = 8, /* this includes A1 to A7 too */
 230     CV_R68_CCR          = 16,
 231     CV_R68_SR           = 17,
 232     CV_R68_USP          = 18,
 233     CV_R68_MSP          = 19,
 234     CV_R68_SFC          = 20,
 235     CV_R68_DFC          = 21,
 236     CV_R68_CACR         = 22,
 237     CV_R68_VBR          = 23,
 238     CV_R68_CAAR         = 24,
 239     CV_R68_ISP          = 25,
 240     CV_R68_PC           = 26,
 241     CV_R68_FPCR         = 28,
 242     CV_R68_FPSR         = 29,
 243     CV_R68_FPIAR        = 30,
 244     CV_R68_FP0          = 32, /* this includes FP1 to FP7 */
 245     CV_R68_MMUSR030     = 41,
 246     CV_R68_MMUSR        = 42,
 247     CV_R68_URP          = 43,
 248     CV_R68_DTT0         = 44,
 249     CV_R68_DTT1         = 45,
 250     CV_R68_ITT0         = 46,
 251     CV_R68_ITT1         = 47,
 252     CV_R68_PSR          = 51,
 253     CV_R68_PCSR         = 52,
 254     CV_R68_VAL          = 53,
 255     CV_R68_CRP          = 54,
 256     CV_R68_SRP          = 55,
 257     CV_R68_DRP          = 56,
 258     CV_R68_TC           = 57,
 259     CV_R68_AC           = 58,
 260     CV_R68_SCC          = 59,
 261     CV_R68_CAL          = 60,
 262     CV_R68_TT0          = 61,
 263     CV_R68_TT1          = 62,
 264     CV_R68_BAD0         = 64, /* this includes BAD1 to BAD7 */
 265     CV_R68_BAC0         = 72, /* this includes BAC1 to BAC7 */
 266
 267     /* MIPS 4000 CPU */
 268     CV_M4_NOREG         = CV_REG_NONE,
 269     CV_M4_IntZERO       = 10,
 270     CV_M4_IntAT         = 11,
 271     CV_M4_IntV0         = 12,
 272     CV_M4_IntV1         = 13,
 273     CV_M4_IntA0         = 14, /* this includes IntA1 to IntA3 */
 274     CV_M4_IntT0         = 18, /* this includes IntT1 to IntT7 */
 275     CV_M4_IntS0         = 26, /* this includes IntS1 to IntS7 */
 276     CV_M4_IntT8         = 34,
 277     CV_M4_IntT9         = 35,
 278     CV_M4_IntKT0        = 36,
 279     CV_M4_IntKT1        = 37,
 280     CV_M4_IntGP         = 38,
 281     CV_M4_IntSP         = 39,
 282     CV_M4_IntS8         = 40,
 283     CV_M4_IntRA         = 41,
 284     CV_M4_IntLO         = 42,
 285     CV_M4_IntHI         = 43,
 286     CV_M4_Fir           = 50,
 287     CV_M4_Psr           = 51,
 288     CV_M4_FltF0         = 60, /* this includes FltF1 to Flt31 */
 289     CV_M4_FltFsr        = 92,
 290
 291     /* Alpha AXP CPU */
 292     CV_ALPHA_NOREG      = CV_REG_NONE,
 293     CV_ALPHA_FltF0      = 10, /* this includes FltF1 to FltF31 */
 294     CV_ALPHA_IntV0      = 42,
 295     CV_ALPHA_IntT0      = 43, /* this includes T1 to T7 */
 296     CV_ALPHA_IntS0      = 51, /* this includes S1 to S5 */
 297     CV_ALPHA_IntFP      = 57,
 298     CV_ALPHA_IntA0      = 58, /* this includes A1 to A5 */
 299     CV_ALPHA_IntT8      = 64,
 300     CV_ALPHA_IntT9      = 65,
 301     CV_ALPHA_IntT10     = 66,
 302     CV_ALPHA_IntT11     = 67,
 303     CV_ALPHA_IntRA      = 68,
 304     CV_ALPHA_IntT12     = 69,
 305     CV_ALPHA_IntAT      = 70,
 306     CV_ALPHA_IntGP      = 71,
 307     CV_ALPHA_IntSP      = 72,
 308     CV_ALPHA_IntZERO    = 73,
 309     CV_ALPHA_Fpcr       = 74,
 310     CV_ALPHA_Fir        = 75,
 311     CV_ALPHA_Psr        = 76,
 312     CV_ALPHA_FltFsr     = 77,
 313     CV_ALPHA_SoftFpcr   = 78,
 314
 315     /* Motorola & IBM PowerPC CPU */
 316     CV_PPC_GPR0         = 1, /* this includes GPR1 to GPR31 */
 317     CV_PPC_CR           = 33,
 318     CV_PPC_CR0          = 34, /* this includes CR1 to CR7 */
 319     CV_PPC_FPR0         = 42, /* this includes FPR1 to FPR31 */
 320
 321     CV_PPC_FPSCR        = 74,
 322     CV_PPC_MSR          = 75,
 323     CV_PPC_SR0          = 76, /* this includes SR1 to SR15 */
 324     /* some PPC registers missing */
 325
 326     /* Hitachi SH3 CPU */
 327     CV_SH3_NOREG        = CV_REG_NONE,
 328     CV_SH3_IntR0        = 10, /* this include R1 to R13 */
 329     CV_SH3_IntFp        = 24,
 330     CV_SH3_IntSp        = 25,
 331     CV_SH3_Gbr          = 38,
 332     CV_SH3_Pr           = 39,
 333     CV_SH3_Mach         = 40,
 334     CV_SH3_Macl         = 41,
 335     CV_SH3_Pc           = 50,
 336     CV_SH3_Sr           = 51,
 337     CV_SH3_BarA         = 60,
 338     CV_SH3_BasrA        = 61,
 339     CV_SH3_BamrA        = 62,
 340     CV_SH3_BbrA         = 63,
 341     CV_SH3_BarB         = 64,
 342     CV_SH3_BasrB        = 65,
 343     CV_SH3_BamrB        = 66,
 344     CV_SH3_BbrB         = 67,
 345     CV_SH3_BdrB         = 68,
 346     CV_SH3_BdmrB        = 69,
 347     CV_SH3_Brcr         = 70,
 348     CV_SH_Fpscr         = 75,
 349     CV_SH_Fpul          = 76,
 350     CV_SH_FpR0          = 80, /* this includes FpR1 to FpR15 */
 351     CV_SH_XFpR0         = 96, /* this includes XFpR1 to XXFpR15 */
 352
 353     /* ARM CPU */
 354     CV_ARM_NOREG        = CV_REG_NONE,
 355     CV_ARM_R0           = 10, /* this includes R1 to R12 */
 356     CV_ARM_SP           = 23,
 357     CV_ARM_LR           = 24,
 358     CV_ARM_PC           = 25,
 359     CV_ARM_CPSR         = 26,
 360
 361     /* Intel IA64 CPU */
 362     CV_IA64_NOREG       = CV_REG_NONE,
 363     CV_IA64_Br0         = 512, /* this includes Br1 to Br7 */
 364     CV_IA64_P0          = 704, /* this includes P1 to P63 */
 365     CV_IA64_Preds       = 768,
 366     CV_IA64_IntH0       = 832, /* this includes H1 to H15 */
 367     CV_IA64_Ip          = 1016,
 368     CV_IA64_Umask       = 1017,
 369     CV_IA64_Cfm         = 1018,
 370     CV_IA64_Psr         = 1019,
 371     CV_IA64_Nats        = 1020,
 372     CV_IA64_Nats2       = 1021,
 373     CV_IA64_Nats3       = 1022,
 374     CV_IA64_IntR0       = 1024, /* this includes R1 to R127 */
 375     CV_IA64_FltF0       = 2048, /* this includes FltF1 to FltF127 */
 376     /* some IA64 registers missing */
 377
 378     /* TriCore CPU */
 379     CV_TRI_NOREG        = CV_REG_NONE,
 380     CV_TRI_D0           = 10, /* includes D1 to D15 */
 381     CV_TRI_A0           = 26, /* includes A1 to A15 */
 382     CV_TRI_E0           = 42,
 383     CV_TRI_E2           = 43,
 384     CV_TRI_E4           = 44,
 385     CV_TRI_E6           = 45,
 386     CV_TRI_E8           = 46,
 387     CV_TRI_E10          = 47,
 388     CV_TRI_E12          = 48,
 389     CV_TRI_E14          = 49,
 390     CV_TRI_EA0          = 50,
 391     CV_TRI_EA2          = 51,
 392     CV_TRI_EA4          = 52,
 393     CV_TRI_EA6          = 53,
 394     CV_TRI_EA8          = 54,
 395     CV_TRI_EA10         = 55,
 396     CV_TRI_EA12         = 56,
 397     CV_TRI_EA14         = 57,
 398     /* some TriCode registers missing */
 399
 400     /* AM33 (and the likes) CPU */
 401     CV_AM33_NOREG       = CV_REG_NONE,
 402     CV_AM33_E0          = 10, /* this includes E1 to E7 */
 403     CV_AM33_A0          = 20, /* this includes A1 to A3 */
 404     CV_AM33_D0          = 30, /* this includes D1 to D3 */
 405     CV_AM33_FS0         = 40, /* this includes FS1 to FS31 */
 406
 407     /* Mitsubishi M32R CPU */
 408     CV_M32R_NOREG       = CV_REG_NONE,
 409     CV_M32R_R0          = 10, /* this includes R1 to R11 */
 410     CV_M32R_R12         = 22,
 411     CV_M32R_R13         = 23,
 412     CV_M32R_R14         = 24,
 413     CV_M32R_R15         = 25,
 414     CV_M32R_PSW         = 26,
 415     CV_M32R_CBR         = 27,
 416     CV_M32R_SPI         = 28,
 417     CV_M32R_SPU         = 29,
 418     CV_M32R_SPO         = 30,
 419     CV_M32R_BPC         = 31,
 420     CV_M32R_ACHI        = 32,
 421     CV_M32R_ACLO        = 33,
 422     CV_M32R_PC          = 34,
 423
 424     /* AMD/Intel x86_64 CPU */
 425     CV_AMD64_NONE       = CV_REG_NONE,
 426     CV_AMD64_AL         = CV_REG_AL,
 427     CV_AMD64_CL         = CV_REG_CL,
 428     CV_AMD64_DL         = CV_REG_DL,
 429     CV_AMD64_BL         = CV_REG_BL,
 430     CV_AMD64_AH         = CV_REG_AH,
 431     CV_AMD64_CH         = CV_REG_CH,
 432     CV_AMD64_DH         = CV_REG_DH,
 433     CV_AMD64_BH         = CV_REG_BH,
 434     CV_AMD64_AX         = CV_REG_AX,
 435     CV_AMD64_CX         = CV_REG_CX,
 436     CV_AMD64_DX         = CV_REG_DX,
 437     CV_AMD64_BX         = CV_REG_BX,
 438     CV_AMD64_SP         = CV_REG_SP,
 439     CV_AMD64_BP         = CV_REG_BP,
 440     CV_AMD64_SI         = CV_REG_SI,
 441     CV_AMD64_DI         = CV_REG_DI,
 442     CV_AMD64_EAX        = CV_REG_EAX,
 443     CV_AMD64_ECX        = CV_REG_ECX,
 444     CV_AMD64_EDX        = CV_REG_EDX,
 445     CV_AMD64_EBX        = CV_REG_EBX,
 446     CV_AMD64_ESP        = CV_REG_ESP,
 447     CV_AMD64_EBP        = CV_REG_EBP,
 448     CV_AMD64_ESI        = CV_REG_ESI,
 449     CV_AMD64_EDI        = CV_REG_EDI,
 450     CV_AMD64_ES         = CV_REG_ES,
 451     CV_AMD64_CS         = CV_REG_CS,
 452     CV_AMD64_SS         = CV_REG_SS,
 453     CV_AMD64_DS         = CV_REG_DS,
 454     CV_AMD64_FS         = CV_REG_FS,
 455     CV_AMD64_GS         = CV_REG_GS,
 456     CV_AMD64_FLAGS      = CV_REG_FLAGS,
 457     CV_AMD64_RIP        = CV_REG_EIP,
 458     CV_AMD64_EFLAGS     = CV_REG_EFLAGS,
 459
 460     /* <pcode> */
 461     CV_AMD64_TEMP       = CV_REG_TEMP,
 462     CV_AMD64_TEMPH      = CV_REG_TEMPH,
 463     CV_AMD64_QUOTE      = CV_REG_QUOTE,
 464     CV_AMD64_PCDR3      = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */
 465     CV_AMD64_CR0        = CV_REG_CR0,   /* this includes CR1 to CR4 */
 466     CV_AMD64_DR0        = CV_REG_DR0,   /* this includes DR1 to DR7 */
 467     /* </pcode> */
 468
 469     CV_AMD64_GDTR       = CV_REG_GDTR,
 470     CV_AMD64_GDTL       = CV_REG_GDTL,
 471     CV_AMD64_IDTR       = CV_REG_IDTR,
 472     CV_AMD64_IDTL       = CV_REG_IDTL,
 473     CV_AMD64_LDTR       = CV_REG_LDTR,
 474     CV_AMD64_TR         = CV_REG_TR,
 475
 476     CV_AMD64_PSEUDO1    = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */
 477     CV_AMD64_ST0        = CV_REG_ST0,     /* this includes ST1 to ST7 */
 478     CV_AMD64_CTRL       = CV_REG_CTRL,
 479     CV_AMD64_STAT       = CV_REG_STAT,
 480     CV_AMD64_TAG        = CV_REG_TAG,
 481     CV_AMD64_FPIP       = CV_REG_FPIP,
 482     CV_AMD64_FPCS       = CV_REG_FPCS,
 483     CV_AMD64_FPDO       = CV_REG_FPDO,
 484     CV_AMD64_FPDS       = CV_REG_FPDS,
 485     CV_AMD64_ISEM       = CV_REG_ISEM,
 486     CV_AMD64_FPEIP      = CV_REG_FPEIP,
 487     CV_AMD64_FPEDO      = CV_REG_FPEDO,
 488     CV_AMD64_MM0        = CV_REG_MM0,     /* this includes MM1 to MM7 */
 489     CV_AMD64_XMM0       = CV_REG_XMM0,    /* this includes XMM1 to XMM7 */
 490     CV_AMD64_XMM00      = CV_REG_XMM00,
 491     CV_AMD64_XMM0L      = CV_REG_XMM0L,   /* this includes XMM1L to XMM7L */
 492     CV_AMD64_XMM0H      = CV_REG_XMM0H,   /* this includes XMM1H to XMM7H */
 493     CV_AMD64_MXCSR      = CV_REG_MXCSR,
 494     CV_AMD64_EDXEAX     = CV_REG_EDXEAX,
 495     CV_AMD64_EMM0L      = CV_REG_EMM0L,
 496     CV_AMD64_EMM0H      = CV_REG_EMM0H,
 497     CV_AMD64_MM00       = CV_REG_MM00,
 498     CV_AMD64_MM01       = CV_REG_MM01,
 499     CV_AMD64_MM10       = CV_REG_MM10,
 500     CV_AMD64_MM11       = CV_REG_MM11,
 501     CV_AMD64_MM20       = CV_REG_MM20,
 502     CV_AMD64_MM21       = CV_REG_MM21,
 503     CV_AMD64_MM30       = CV_REG_MM30,
 504     CV_AMD64_MM31       = CV_REG_MM31,
 505     CV_AMD64_MM40       = CV_REG_MM40,
 506     CV_AMD64_MM41       = CV_REG_MM41,
 507     CV_AMD64_MM50       = CV_REG_MM50,
 508     CV_AMD64_MM51       = CV_REG_MM51,
 509     CV_AMD64_MM60       = CV_REG_MM60,
 510     CV_AMD64_MM61       = CV_REG_MM61,
 511     CV_AMD64_MM70       = CV_REG_MM70,
 512     CV_AMD64_MM71       = CV_REG_MM71,
 513
 514     CV_AMD64_XMM8       = 252,           /* this includes XMM9 to XMM15 */
 515
 516     CV_AMD64_RAX        = 328,
 517     CV_AMD64_RBX        = 329,
 518     CV_AMD64_RCX        = 330,
 519     CV_AMD64_RDX        = 331,
 520     CV_AMD64_RSI        = 332,
 521     CV_AMD64_RDI        = 333,
 522     CV_AMD64_RBP        = 334,
 523     CV_AMD64_RSP        = 335,
 524
 525     CV_AMD64_R8         = 336,
 526     CV_AMD64_R9         = 337,
 527     CV_AMD64_R10        = 338,
 528     CV_AMD64_R11        = 339,
 529     CV_AMD64_R12        = 340,
 530     CV_AMD64_R13        = 341,
 531     CV_AMD64_R14        = 342,
 532     CV_AMD64_R15        = 343,
 533 };
 534
 535 typedef enum
 536 {
 537    THUNK_ORDINAL_NOTYPE,
 538    THUNK_ORDINAL_ADJUSTOR,
 539    THUNK_ORDINAL_VCALL,
 540    THUNK_ORDINAL_PCODE,
 541    THUNK_ORDINAL_LOAD
 542 } THUNK_ORDINAL;
 543
 544 typedef enum CV_call_e
 545 {
 546     CV_CALL_NEAR_C,
 547     CV_CALL_FAR_C,
 548     CV_CALL_NEAR_PASCAL,
 549     CV_CALL_FAR_PASCAL,
 550     CV_CALL_NEAR_FAST,
 551     CV_CALL_FAR_FAST,
 552     CV_CALL_SKIPPED,
 553     CV_CALL_NEAR_STD,
 554     CV_CALL_FAR_STD,
 555     CV_CALL_NEAR_SYS,
 556     CV_CALL_FAR_SYS,
 557     CV_CALL_THISCALL,
 558     CV_CALL_MIPSCALL,
 559     CV_CALL_GENERIC,
 560     CV_CALL_ALPHACALL,
 561     CV_CALL_PPCCALL,
 562     CV_CALL_RESERVED,
 563 } CV_call_e;