2 * Fast486 386/486 CPU Emulation Library
5 * Copyright (C) 2013 Aleksandar Andrejevic <theflash AT sdf DOT lonestar DOT org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 /* DEFINES ********************************************************************/
30 #define FASTCALL __fastcall
33 #define FAST486_NUM_GEN_REGS 8
34 #define FAST486_NUM_SEG_REGS 6
35 #define FAST486_NUM_CTRL_REGS 3
36 #define FAST486_NUM_DBG_REGS 6
37 #define FAST486_NUM_FPU_REGS 8
39 #define FAST486_CR0_PE (1 << 0)
40 #define FAST486_CR0_MP (1 << 1)
41 #define FAST486_CR0_EM (1 << 2)
42 #define FAST486_CR0_TS (1 << 3)
43 #define FAST486_CR0_ET (1 << 4)
44 #define FAST486_CR0_NE (1 << 5)
45 #define FAST486_CR0_WP (1 << 16)
46 #define FAST486_CR0_AM (1 << 18)
47 #define FAST486_CR0_NW (1 << 29)
48 #define FAST486_CR0_CD (1 << 30)
49 #define FAST486_CR0_PG (1 << 31)
51 #define FAST486_DR4_B0 (1 << 0)
52 #define FAST486_DR4_B1 (1 << 1)
53 #define FAST486_DR4_B2 (1 << 2)
54 #define FAST486_DR4_B3 (1 << 3)
55 #define FAST486_DR4_BD (1 << 13)
56 #define FAST486_DR4_BS (1 << 14)
57 #define FAST486_DR4_BT (1 << 15)
59 #define FAST486_DR5_L0 (1 << 0)
60 #define FAST486_DR5_G0 (1 << 1)
61 #define FAST486_DR5_L1 (1 << 2)
62 #define FAST486_DR5_G1 (1 << 3)
63 #define FAST486_DR5_L2 (1 << 4)
64 #define FAST486_DR5_G2 (1 << 5)
65 #define FAST486_DR5_L3 (1 << 6)
66 #define FAST486_DR5_G3 (1 << 7)
67 #define FAST486_DR5_LE (1 << 8)
68 #define FAST486_DR5_GE (1 << 9)
69 #define FAST486_DR5_GD (1 << 13)
71 #define FAST486_DBG_BREAK_EXEC 0
72 #define FAST486_DBG_BREAK_WRITE 1
73 #define FAST486_DBG_BREAK_READWRITE 3
75 #define FAST486_DR4_RESERVED 0xFFFF1FF0
76 #define FAST486_DR5_RESERVED 0x0000DC00
78 #define FAST486_IDT_TASK_GATE 0x5
79 #define FAST486_IDT_INT_GATE 0x6
80 #define FAST486_IDT_TRAP_GATE 0x7
81 #define FAST486_IDT_INT_GATE_32 0xE
82 #define FAST486_IDT_TRAP_GATE_32 0xF
84 #define FAST486_TSS_SIGNATURE 0x09
86 #define FAST486_PREFIX_SEG (1 << 0)
87 #define FAST486_PREFIX_OPSIZE (1 << 1)
88 #define FAST486_PREFIX_ADSIZE (1 << 2)
89 #define FAST486_PREFIX_LOCK (1 << 3)
90 #define FAST486_PREFIX_REPNZ (1 << 4)
91 #define FAST486_PREFIX_REP (1 << 5)
93 struct _FAST486_STATE
;
94 typedef struct _FAST486_STATE FAST486_STATE
, *PFAST486_STATE
;
96 typedef enum _FAST486_GEN_REGS
106 } FAST486_GEN_REGS
, *PFAST486_GEN_REGS
;
108 typedef enum _FAST486_SEG_REGS
116 } FAST486_SEG_REGS
, *PFAST486_SEG_REGS
;
118 typedef enum _FAST486_CTRL_REGS
123 } FAST486_CTRL_REGS
, *PFAST486_CTRL_REGS
;
125 typedef enum _FAST486_DBG_REGS
133 FAST486_REG_DR6
= 4, // alias to DR4
134 FAST486_REG_DR7
= 5 // alias to DR5
135 } FAST486_DBG_REGS
, *PFAST486_DBG_REGS
;
137 typedef enum _FAST486_EXCEPTIONS
139 FAST486_EXCEPTION_DE
= 0x00,
140 FAST486_EXCEPTION_DB
= 0x01,
141 FAST486_EXCEPTION_BP
= 0x03,
142 FAST486_EXCEPTION_OF
= 0x04,
143 FAST486_EXCEPTION_BR
= 0x05,
144 FAST486_EXCEPTION_UD
= 0x06,
145 FAST486_EXCEPTION_NM
= 0x07,
146 FAST486_EXCEPTION_DF
= 0x08,
147 FAST486_EXCEPTION_TS
= 0x0A,
148 FAST486_EXCEPTION_NP
= 0x0B,
149 FAST486_EXCEPTION_SS
= 0x0C,
150 FAST486_EXCEPTION_GP
= 0x0D,
151 FAST486_EXCEPTION_PF
= 0x0E,
152 FAST486_EXCEPTION_MF
= 0x10,
153 FAST486_EXCEPTION_AC
= 0x11,
154 FAST486_EXCEPTION_MC
= 0x12
155 } FAST486_EXCEPTIONS
, *PFAST486_EXCEPTIONS
;
157 typedef enum _FAST486_INT_STATUS
159 FAST486_INT_NONE
= 0,
160 FAST486_INT_EXECUTE
= 1,
161 FAST486_INT_SIGNAL
= 2
162 } FAST486_INT_STATUS
, *PFAST486_INT_STATUS
;
166 (NTAPI
*FAST486_MEM_READ_PROC
)
168 PFAST486_STATE State
,
176 (NTAPI
*FAST486_MEM_WRITE_PROC
)
178 PFAST486_STATE State
,
186 (NTAPI
*FAST486_IO_READ_PROC
)
188 PFAST486_STATE State
,
197 (NTAPI
*FAST486_IO_WRITE_PROC
)
199 PFAST486_STATE State
,
208 (NTAPI
*FAST486_IDLE_PROC
)
215 (NTAPI
*FAST486_BOP_PROC
)
217 PFAST486_STATE State
,
223 (NTAPI
*FAST486_INT_ACK_PROC
)
228 typedef union _FAST486_REG
240 } FAST486_REG
, *PFAST486_REG
;
242 typedef struct _FAST486_SEG_REG
246 /* Descriptor cache */
250 ULONG Executable
: 1;
251 ULONG SystemType
: 1;
257 } FAST486_SEG_REG
, *PFAST486_SEG_REG
;
265 } FAST486_TASK_REG
, *PFAST486_TASK_REG
;
267 #pragma pack(push, 1)
277 ULONG Executable
: 1;
278 ULONG SystemType
: 1;
285 ULONG Granularity
: 1;
287 } FAST486_GDT_ENTRY
, *PFAST486_GDT_ENTRY
;
289 /* Verify the structure size */
290 C_ASSERT(sizeof(FAST486_GDT_ENTRY
) == sizeof(ULONGLONG
));
303 ULONG Granularity
: 1;
305 } FAST486_TSS_DESCRIPTOR
, *PFAST486_TSS_DESCRIPTOR
;
307 /* Verify the structure size */
308 C_ASSERT(sizeof(FAST486_TSS_DESCRIPTOR
) == sizeof(ULONGLONG
));
314 ULONG ParamCount
: 5;
317 ULONG SystemType
: 1;
320 ULONG OffsetHigh
: 16;
321 } FAST486_CALL_GATE
, *PFAST486_CALL_GATE
;
323 /* Verify the structure size */
324 C_ASSERT(sizeof(FAST486_CALL_GATE
) == sizeof(ULONGLONG
));
335 ULONG OffsetHigh
: 16;
336 } FAST486_IDT_ENTRY
, *PFAST486_IDT_ENTRY
;
338 /* Verify the structure size */
339 C_ASSERT(sizeof(FAST486_IDT_ENTRY
) == sizeof(ULONGLONG
));
343 typedef struct _FAST486_TABLE_REG
347 } FAST486_TABLE_REG
, *PFAST486_TABLE_REG
;
349 typedef union _FAST486_FLAGS_REG
374 // ULONG Reserved : 14;
376 } FAST486_FLAGS_REG
, *PFAST486_FLAGS_REG
;
378 typedef struct _FAST486_TSS
406 } FAST486_TSS
, *PFAST486_TSS
;
408 typedef struct _FAST486_FPU_DATA_REG
412 } FAST486_FPU_DATA_REG
, *PFAST486_FPU_DATA_REG
;
414 typedef union _FAST486_FPU_STATUS_REG
435 } FAST486_FPU_STATUS_REG
, *PFAST486_FPU_STATUS_REG
;
437 typedef union _FAST486_FPU_CONTROL_REG
453 // ULONG Reserved1 : 3;
455 } FAST486_FPU_CONTROL_REG
, *PFAST486_FPU_CONTROL_REG
;
457 struct _FAST486_STATE
459 FAST486_MEM_READ_PROC MemReadCallback
;
460 FAST486_MEM_WRITE_PROC MemWriteCallback
;
461 FAST486_IO_READ_PROC IoReadCallback
;
462 FAST486_IO_WRITE_PROC IoWriteCallback
;
463 FAST486_IDLE_PROC IdleCallback
;
464 FAST486_BOP_PROC BopCallback
;
465 FAST486_INT_ACK_PROC IntAckCallback
;
466 FAST486_REG GeneralRegs
[FAST486_NUM_GEN_REGS
];
467 FAST486_SEG_REG SegmentRegs
[FAST486_NUM_SEG_REGS
];
468 FAST486_REG InstPtr
, SavedInstPtr
;
469 FAST486_FLAGS_REG Flags
;
470 FAST486_TABLE_REG Gdtr
, Idtr
, Ldtr
;
471 FAST486_TASK_REG TaskReg
;
473 ULONG ControlRegisters
[FAST486_NUM_CTRL_REGS
];
474 ULONG DebugRegisters
[FAST486_NUM_DBG_REGS
];
475 ULONG ExceptionCount
;
477 FAST486_SEG_REGS SegmentOverride
;
478 FAST486_INT_STATUS IntStatus
;
481 FAST486_FPU_DATA_REG FpuRegisters
[FAST486_NUM_FPU_REGS
];
482 FAST486_FPU_STATUS_REG FpuStatus
;
483 FAST486_FPU_CONTROL_REG FpuControl
;
487 /* FUNCTIONS ******************************************************************/
491 Fast486Initialize(PFAST486_STATE State
,
492 FAST486_MEM_READ_PROC MemReadCallback
,
493 FAST486_MEM_WRITE_PROC MemWriteCallback
,
494 FAST486_IO_READ_PROC IoReadCallback
,
495 FAST486_IO_WRITE_PROC IoWriteCallback
,
496 FAST486_IDLE_PROC IdleCallback
,
497 FAST486_BOP_PROC BopCallback
,
498 FAST486_INT_ACK_PROC IntAckCallback
,
503 Fast486Reset(PFAST486_STATE State
);
507 Fast486Continue(PFAST486_STATE State
);
511 Fast486StepInto(PFAST486_STATE State
);
515 Fast486StepOver(PFAST486_STATE State
);
519 Fast486StepOut(PFAST486_STATE State
);
523 Fast486DumpState(PFAST486_STATE State
);
527 Fast486Interrupt(PFAST486_STATE State
, UCHAR Number
);
531 Fast486InterruptSignal(PFAST486_STATE State
);
535 Fast486ExecuteAt(PFAST486_STATE State
, USHORT Segment
, ULONG Offset
);
539 Fast486SetStack(PFAST486_STATE State
, USHORT Segment
, ULONG Offset
);
545 PFAST486_STATE State
,
546 FAST486_SEG_REGS Segment
,
550 #endif // _FAST486_H_