ntoskrnl/include/internal/amd64/ke.h

   1 #ifndef __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
   2 #define __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H
   3
   4 #define X86_EFLAGS_TF           0x00000100 /* Trap flag */
   5 #define X86_EFLAGS_IF           0x00000200 /* Interrupt Enable flag */
   6 #define X86_EFLAGS_IOPL         0x00003000 /* I/O Privilege Level bits */
   7 #define X86_EFLAGS_NT           0x00004000 /* Nested Task flag */
   8 #define X86_EFLAGS_RF           0x00010000 /* Resume flag */
   9 #define X86_EFLAGS_VM           0x00020000 /* Virtual Mode */
  10 #define X86_EFLAGS_ID           0x00200000 /* CPUID detection flag */
  11
  12 #define X86_CR0_PE              0x00000001 /* enable Protected Mode */
  13 #define X86_CR0_NE              0x00000020 /* enable native FPU error reporting */
  14 #define X86_CR0_TS              0x00000008 /* enable exception on FPU instruction for task switch */
  15 #define X86_CR0_EM              0x00000004 /* enable FPU emulation (disable FPU) */
  16 #define X86_CR0_MP              0x00000002 /* enable FPU monitoring */
  17 #define X86_CR0_WP              0x00010000 /* enable Write Protect (copy on write) */
  18 #define X86_CR0_PG              0x80000000 /* enable Paging */
  19
  20 #define X86_CR4_PAE             0x00000020 /* enable physical address extensions */
  21 #define X86_CR4_PGE             0x00000080 /* enable global pages */
  22 #define X86_CR4_OSFXSR          0x00000200 /* enable FXSAVE/FXRSTOR instructions */
  23 #define X86_CR4_OSXMMEXCPT      0x00000400 /* enable #XF exception */
  24
  25 #define X86_FEATURE_VME         0x00000002 /* Virtual 8086 Extensions are present */
  26 #define X86_FEATURE_TSC         0x00000010 /* time stamp counters are present */
  27 #define X86_FEATURE_PAE         0x00000040 /* physical address extension is present */
  28 #define X86_FEATURE_CX8         0x00000100 /* CMPXCHG8B instruction present */
  29 #define X86_FEATURE_SYSCALL     0x00000800 /* SYSCALL/SYSRET support present */
  30 #define X86_FEATURE_PGE         0x00002000 /* Page Global Enable */
  31 #define X86_FEATURE_MMX         0x00800000 /* MMX extension present */
  32 #define X86_FEATURE_FXSR        0x01000000 /* FXSAVE/FXRSTOR instructions present */
  33 #define X86_FEATURE_SSE         0x02000000 /* SSE extension present */
  34 #define X86_FEATURE_SSE2        0x04000000 /* SSE2 extension present */
  35 #define X86_FEATURE_HT          0x10000000 /* Hyper-Threading present */
  36
  37 #define X86_EXT_FEATURE_SSE3    0x00000001 /* SSE3 extension present */
  38 #define X86_EXT_FEATURE_3DNOW   0x40000000 /* 3DNOW! extension present */
  39
  40 #define FRAME_EDITED        0xFFF8
  41
  42 #define X86_MSR_GSBASE          0xC0000101
  43 #define X86_MSR_KERNEL_GSBASE   0xC0000102
  44 #define X86_MSR_EFER            0xC0000080
  45 #define X86_MSR_STAR            0xC0000081
  46 #define X86_MSR_LSTAR           0xC0000082
  47 #define X86_MSR_CSTAR           0xC0000083
  48 #define X86_MSR_SFMASK          0xC0000084
  49
  50 #define EFER_SCE 0x01
  51 #define EFER_LME 0x10
  52 #define EFER_LMA 0x40
  53 #define EFER_NXE 0x80
  54 #define EFER_SVME 0x100
  55 #define EFER_FFXSR 0x400
  56
  57 #define AMD64_TSS 9
  58
  59 #define APIC_EOI_REGISTER 0xFFFFFFFFFFFE00B0ULL
  60
  61 #ifndef __ASM__
  62
  63 #include "intrin_i.h"
  64
  65 typedef struct _KIDT_INIT
  66 {
  67     UCHAR InterruptId;
  68     UCHAR Dpl;
  69     UCHAR IstIndex;
  70     PVOID ServiceRoutine;
  71 } KIDT_INIT, *PKIDT_INIT;
  72
  73 #include <pshpack1.h>
  74 typedef struct _KI_INTERRUPT_DISPATCH_ENTRY
  75 {
  76     UCHAR _Op_nop;
  77     UCHAR _Op_push;
  78     UCHAR _Vector;
  79     UCHAR _Op_jmp;
  80     ULONG RelativeAddress;
  81 } KI_INTERRUPT_DISPATCH_ENTRY, *PKI_INTERRUPT_DISPATCH_ENTRY;
  82 #include <poppack.h>
  83
  84 extern ULONG Ke386CacheAlignment;
  85 extern ULONG KeI386NpxPresent;
  86 extern ULONG KeI386XMMIPresent;
  87 extern ULONG KeI386FxsrPresent;
  88 extern ULONG KeI386CpuType;
  89 extern ULONG KeI386CpuStep;
  90
  91 //
  92 // INT3 is 1 byte long
  93 //
  94 #define KD_BREAKPOINT_TYPE        UCHAR
  95 #define KD_BREAKPOINT_SIZE        sizeof(UCHAR)
  96 #define KD_BREAKPOINT_VALUE       0xCC
  97
  98 //
  99 // Macros for getting and setting special purpose registers in portable code
 100 //
 101 #define KeGetContextPc(Context) \
 102     ((Context)->Rip)
 103
 104 #define KeSetContextPc(Context, ProgramCounter) \
 105     ((Context)->Rip = (ProgramCounter))
 106
 107 #define KeGetTrapFramePc(TrapFrame) \
 108     ((TrapFrame)->Rip)
 109
 110 #define KiGetLinkedTrapFrame(x) \
 111     (PKTRAP_FRAME)((x)->TrapFrame)
 112
 113 #define KeGetContextReturnRegister(Context) \
 114     ((Context)->Rax)
 115
 116 #define KeSetContextReturnRegister(Context, ReturnValue) \
 117     ((Context)->Rax = (ReturnValue))
 118
 119 //
 120 // Macro to get trap and exception frame from a thread stack
 121 //
 122 #define KeGetTrapFrame(Thread) \
 123     (PKTRAP_FRAME)((ULONG_PTR)((Thread)->InitialStack) - \
 124                    sizeof(KTRAP_FRAME))
 125
 126 //
 127 // Macro to get context switches from the PRCB
 128 // All architectures but x86 have it in the PRCB's KeContextSwitches
 129 //
 130 #define KeGetContextSwitches(Prcb)  \
 131     (Prcb->KeContextSwitches)
 132
 133 //
 134 // Macro to get the second level cache size field name which differs between
 135 // CISC and RISC architectures, as the former has unified I/D cache
 136 //
 137 #define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
 138
 139 #define KeGetExceptionFrame(Thread) \
 140     (PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
 141                         sizeof(KEXCEPTION_FRAME))
 142
 143 //
 144 // Returns the Interrupt State from a Trap Frame.
 145 // ON = TRUE, OFF = FALSE
 146 //
 147 #define KeGetTrapFrameInterruptState(TrapFrame) \
 148         BooleanFlagOn((TrapFrame)->EFlags, EFLAGS_INTERRUPT_MASK)
 149
 150 /* Diable interrupts and return whether they were enabled before */
 151 FORCEINLINE
 152 BOOLEAN
 153 KeDisableInterrupts(VOID)
 154 {
 155     ULONG_PTR Flags;
 156
 157     /* Get EFLAGS and check if the interrupt bit is set */
 158     Flags = __readeflags();
 159
 160     /* Disable interrupts */
 161     _disable();
 162     return (Flags & EFLAGS_INTERRUPT_MASK) ? TRUE : FALSE;
 163 }
 164
 165 /* Restore previous interrupt state */
 166 FORCEINLINE
 167 VOID
 168 KeRestoreInterrupts(BOOLEAN WereEnabled)
 169 {
 170     if (WereEnabled) _enable();
 171 }
 172
 173 //
 174 // Invalidates the TLB entry for a specified address
 175 //
 176 FORCEINLINE
 177 VOID
 178 KeInvalidateTlbEntry(IN PVOID Address)
 179 {
 180     /* Invalidate the TLB entry for this address */
 181     __invlpg(Address);
 182 }
 183
 184 FORCEINLINE
 185 VOID
 186 KeFlushProcessTb(VOID)
 187 {
 188     /* Flush the TLB by resetting CR3 */
 189     __writecr3(__readcr3());
 190 }
 191
 192 FORCEINLINE
 193 VOID
 194 KiRundownThread(IN PKTHREAD Thread)
 195 {
 196 #ifndef CONFIG_SMP
 197     DbgPrint("KiRundownThread is unimplemented\n");
 198 #else
 199     /* Nothing to do */
 200 #endif
 201 }
 202
 203 /* Registers an interrupt handler with an IDT vector */
 204 FORCEINLINE
 205 VOID
 206 KeRegisterInterruptHandler(IN ULONG Vector,
 207                            IN PVOID Handler)
 208 {
 209     UCHAR Entry;
 210     PKIDTENTRY64 Idt;
 211
 212     /* Get the entry from the HAL */
 213     Entry = HalVectorToIDTEntry(Vector);
 214
 215     /* Now set the data */
 216     Idt = &KeGetPcr()->IdtBase[Entry];
 217     Idt->OffsetLow = (ULONG_PTR)Handler & 0xffff;
 218     Idt->OffsetMiddle = ((ULONG_PTR)Handler >> 16) & 0xffff;
 219     Idt->OffsetHigh = (ULONG_PTR)Handler >> 32;
 220     Idt->Selector = KGDT64_R0_CODE;
 221     Idt->IstIndex = 0;
 222     Idt->Type = 0x0e;
 223     Idt->Dpl = 0;
 224     Idt->Present = 1;
 225     Idt->Reserved0 = 0;
 226     Idt->Reserved1 = 0;
 227 }
 228
 229 /* Returns the registered interrupt handler for a given IDT vector */
 230 FORCEINLINE
 231 PVOID
 232 KeQueryInterruptHandler(IN ULONG Vector)
 233 {
 234     UCHAR Entry;
 235     PKIDTENTRY64 Idt;
 236
 237     /* Get the entry from the HAL */
 238     Entry = HalVectorToIDTEntry(Vector);
 239
 240     /* Get the IDT entry */
 241     Idt = &KeGetPcr()->IdtBase[Entry];
 242
 243     /* Return the address */
 244     return (PVOID)((ULONG64)Idt->OffsetHigh << 32 |
 245                    (ULONG64)Idt->OffsetMiddle << 16 |
 246                    (ULONG64)Idt->OffsetLow);
 247 }
 248
 249 VOID
 250 FORCEINLINE
 251 KiSendEOI()
 252 {
 253     /* Write 0 to the apic EOI register */
 254     *((volatile ULONG*)APIC_EOI_REGISTER) = 0;
 255 }
 256
 257 VOID
 258 FORCEINLINE
 259 KiEndInterrupt(IN KIRQL Irql,
 260                IN PKTRAP_FRAME TrapFrame)
 261 {
 262     /* Make sure this is from the clock handler */
 263     ASSERT(TrapFrame->ErrorCode == 0xc10c4);
 264     //KeLowerIrql(Irql);
 265 }
 266
 267 BOOLEAN
 268 FORCEINLINE
 269 KiUserTrap(IN PKTRAP_FRAME TrapFrame)
 270 {
 271     /* Anything else but Ring 0 is Ring 3 */
 272     return !!(TrapFrame->SegCs & MODE_MASK);
 273 }
 274
 275 #define Ki386PerfEnd()
 276
 277 struct _KPCR;
 278
 279 //VOID KiInitializeTss(IN PKTSS Tss, IN UINT64 Stack);
 280
 281 VOID KiSwitchToBootStack(IN ULONG_PTR InitialStack);
 282 VOID KiDivideErrorFault(VOID);
 283 VOID KiDebugTrapOrFault(VOID);
 284 VOID KiNmiInterrupt(VOID);
 285 VOID KiBreakpointTrap(VOID);
 286 VOID KiOverflowTrap(VOID);
 287 VOID KiBoundFault(VOID);
 288 VOID KiInvalidOpcodeFault(VOID);
 289 VOID KiNpxNotAvailableFault(VOID);
 290 VOID KiDoubleFaultAbort(VOID);
 291 VOID KiNpxSegmentOverrunAbort(VOID);
 292 VOID KiInvalidTssFault(VOID);
 293 VOID KiSegmentNotPresentFault(VOID);
 294 VOID KiStackFault(VOID);
 295 VOID KiGeneralProtectionFault(VOID);
 296 VOID KiPageFault(VOID);
 297 VOID KiFloatingErrorFault(VOID);
 298 VOID KiAlignmentFault(VOID);
 299 VOID KiMcheckAbort(VOID);
 300 VOID KiXmmException(VOID);
 301 VOID KiApcInterrupt(VOID);
 302 VOID KiRaiseAssertion(VOID);
 303 VOID KiDebugServiceTrap(VOID);
 304 VOID KiDpcInterrupt(VOID);
 305 VOID KiIpiInterrupt(VOID);
 306
 307 VOID KiGdtPrepareForApplicationProcessorInit(ULONG Id);
 308 VOID Ki386InitializeLdt(VOID);
 309 VOID Ki386SetProcessorFeatures(VOID);
 310 VOID KiGetCacheInformation(VOID);
 311 VOID KiSetProcessorType(VOID);
 312 ULONG KiGetFeatureBits(VOID);
 313 VOID KiInitializeCpuFeatures(VOID);
 314
 315 ULONG KeAllocateGdtSelector(ULONG Desc[2]);
 316 VOID KeFreeGdtSelector(ULONG Entry);
 317 VOID NtEarlyInitVdm(VOID);
 318 VOID KeApplicationProcessorInitDispatcher(VOID);
 319 VOID KeCreateApplicationProcessorIdleThread(ULONG Id);
 320
 321 VOID
 322 Ke386InitThreadWithContext(PKTHREAD Thread,
 323                            PKSYSTEM_ROUTINE SystemRoutine,
 324                            PKSTART_ROUTINE StartRoutine,
 325                            PVOID StartContext,
 326                            PCONTEXT Context);
 327 #define KeArchInitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context) \
 328   Ke386InitThreadWithContext(Thread,SystemRoutine,StartRoutine,StartContext,Context)
 329
 330 #ifdef _NTOSKRNL_ /* FIXME: Move flags above to NDK instead of here */
 331 VOID
 332 KiThreadStartup(PKSYSTEM_ROUTINE SystemRoutine,
 333                 PKSTART_ROUTINE StartRoutine,
 334                 PVOID StartContext,
 335                 BOOLEAN UserThread,
 336                 KTRAP_FRAME TrapFrame);
 337 #endif
 338
 339 #endif /* __ASM__ */
 340
 341 // HACK
 342 extern NTKERNELAPI volatile KSYSTEM_TIME KeTickCount;
 343
 344 // win64 uses DMA macros, this one is not defined
 345 NTHALAPI
 346 NTSTATUS
 347 NTAPI
 348 HalAllocateAdapterChannel(
 349   IN PADAPTER_OBJECT  AdapterObject,
 350   IN PWAIT_CONTEXT_BLOCK  Wcb,
 351   IN ULONG  NumberOfMapRegisters,
 352   IN PDRIVER_CONTROL  ExecutionRoutine);
 353
 354 #endif /* __NTOSKRNL_INCLUDE_INTERNAL_AMD64_KE_H */
 355
 356 /* EOF */