[NTOS:MM] Pass page fault code to MmAccessFault
[reactos.git] / ntoskrnl / include / internal / amd64 / mm.h
1 /*
2 * kernel internal memory management definitions for amd64
3 */
4 #pragma once
5
6 #define _MI_PAGING_LEVELS 4
7
8 /* Memory layout base addresses */
9 #define MI_USER_PROBE_ADDRESS (PVOID)0x000007FFFFFF0000ULL
10 #define MI_DEFAULT_SYSTEM_RANGE_START (PVOID)0xFFFF080000000000ULL
11 #define MI_REAL_SYSTEM_RANGE_START 0xFFFF800000000000ULL
12 #define HYPER_SPACE 0xFFFFF70000000000ULL
13 #define HYPER_SPACE_END 0xFFFFF77FFFFFFFFFULL
14 #define MI_SYSTEM_CACHE_WS_START 0xFFFFF78000001000ULL
15 #define MI_PAGED_POOL_START (PVOID)0xFFFFF8A000000000ULL
16 //#define MI_PAGED_POOL_END 0xFFFFF8BFFFFFFFFFULL
17 //#define MI_SESSION_SPACE_START 0xFFFFF90000000000ULL
18 #define MI_SESSION_VIEW_END 0xFFFFF97FFF000000ULL
19 #define MI_SESSION_SPACE_END 0xFFFFF97FFFFFFFFFULL
20 #define MM_SYSTEM_SPACE_START 0xFFFFF98000000000ULL
21 #define MI_PFN_DATABASE 0xFFFFFA8000000000ULL
22 #define MI_DEBUG_MAPPING (PVOID)0xFFFFFFFF80000000ULL // FIXME
23 #define MI_NONPAGED_POOL_END (PVOID)0xFFFFFFFFFFBFFFFFULL
24 #define MI_HIGHEST_SYSTEM_ADDRESS (PVOID)0xFFFFFFFFFFFFFFFFULL
25 #define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
26
27 /* WOW64 address definitions */
28 #define MM_HIGHEST_USER_ADDRESS_WOW64 0x7FFEFFFF
29 #define MM_SYSTEM_RANGE_START_WOW64 0x80000000
30
31 /* Misc address definitions */
32 //#define MI_NON_PAGED_SYSTEM_START_MIN MM_SYSTEM_SPACE_START // FIXME
33 //#define MI_SYSTEM_PTE_START MM_SYSTEM_SPACE_START
34 //#define MI_SYSTEM_PTE_END (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
35 #define MI_SYSTEM_PTE_BASE (PVOID)MiAddressToPte(KSEG0_BASE)
36 #define MM_HIGHEST_VAD_ADDRESS (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
37 #define MI_MAPPING_RANGE_START HYPER_SPACE
38 #define MI_MAPPING_RANGE_END (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
39 #define MI_DUMMY_PTE (MI_MAPPING_RANGE_END + PAGE_SIZE)
40 #define MI_VAD_BITMAP (MI_DUMMY_PTE + PAGE_SIZE)
41 #define MI_WORKING_SET_LIST (MI_VAD_BITMAP + PAGE_SIZE)
42
43 /* Memory sizes */
44 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255 * _1MB) >> PAGE_SHIFT)
45 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING ((19 * _1MB) >> PAGE_SHIFT)
46 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST ((32 * _1MB) >> PAGE_SHIFT)
47 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST ((256 * _1MB) >> PAGE_SHIFT)
48 #define MI_MIN_INIT_PAGED_POOLSIZE (32 * _1MB)
49 #define MI_MAX_INIT_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
50 #define MI_MAX_NONPAGED_POOL_SIZE (128ULL * 1024 * 1024 * 1024)
51 #define MI_SYSTEM_VIEW_SIZE (16 * _1MB)
52 #define MI_SESSION_VIEW_SIZE (20 * _1MB)
53 #define MI_SESSION_POOL_SIZE (16 * _1MB)
54 #define MI_SESSION_IMAGE_SIZE (8 * _1MB)
55 #define MI_SESSION_WORKING_SET_SIZE (4 * _1MB)
56 #define MI_SESSION_SIZE (MI_SESSION_VIEW_SIZE + \
57 MI_SESSION_POOL_SIZE + \
58 MI_SESSION_IMAGE_SIZE + \
59 MI_SESSION_WORKING_SET_SIZE)
60 #define MI_MIN_ALLOCATION_FRAGMENT (4 * _1KB)
61 #define MI_ALLOCATION_FRAGMENT (64 * _1KB)
62 #define MI_MAX_ALLOCATION_FRAGMENT (2 * _1MB)
63
64 /* Misc constants */
65 #define MM_PTE_SOFTWARE_PROTECTION_BITS 5
66 #define MI_MIN_SECONDARY_COLORS 8
67 #define MI_SECONDARY_COLORS 64
68 #define MI_MAX_SECONDARY_COLORS 1024
69 #define MI_NUMBER_SYSTEM_PTES 22000
70 #define MI_MAX_FREE_PAGE_LISTS 4
71 #define MI_HYPERSPACE_PTES (256 - 1)
72 #define MI_ZERO_PTES (32)
73 #define MI_MAX_ZERO_BITS 53
74 #define SESSION_POOL_LOOKASIDES 21
75
76 /* MMPTE related defines */
77 #define MM_EMPTY_PTE_LIST ((ULONG64)0xFFFFFFFF)
78 #define MM_EMPTY_LIST ((ULONG_PTR)-1)
79
80
81 /* Easy accessing PFN in PTE */
82 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
83 #define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
84 #define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
85 #define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
86
87 /* Macros for portable PTE modification */
88 #define MI_MAKE_DIRTY_PAGE(x) ((x)->u.Hard.Dirty = 1)
89 #define MI_MAKE_CLEAN_PAGE(x) ((x)->u.Hard.Dirty = 0)
90 #define MI_MAKE_ACCESSED_PAGE(x) ((x)->u.Hard.Accessed = 1)
91 #define MI_PAGE_DISABLE_CACHE(x) ((x)->u.Hard.CacheDisable = 1)
92 #define MI_PAGE_WRITE_THROUGH(x) ((x)->u.Hard.WriteThrough = 1)
93 #define MI_PAGE_WRITE_COMBINED(x) ((x)->u.Hard.WriteThrough = 0)
94 #define MI_IS_PAGE_LARGE(x) ((x)->u.Hard.LargePage == 1)
95 #if !defined(CONFIG_SMP)
96 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Write == 1)
97 #else
98 #define MI_IS_PAGE_WRITEABLE(x) ((x)->u.Hard.Writable == 1)
99 #endif
100 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
101 #define MI_IS_PAGE_DIRTY(x) ((x)->u.Hard.Dirty == 1)
102 #define MI_MAKE_OWNER_PAGE(x) ((x)->u.Hard.Owner = 1)
103 #if !defined(CONFIG_SMP)
104 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Write = 1)
105 #else
106 #define MI_MAKE_WRITE_PAGE(x) ((x)->u.Hard.Writable = 1)
107 #endif
108
109 /* Macros to identify the page fault reason from the error code */
110 #define MI_IS_NOT_PRESENT_FAULT(FaultCode) !BooleanFlagOn(FaultCode, 0x1)
111
112 /* On x64, these are the same */
113 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
114 #define ValidKernelPpe ValidKernelPde
115
116 /* Convert an address to a corresponding PTE */
117 PMMPTE
118 FORCEINLINE
119 _MiAddressToPte(PVOID Address)
120 {
121 ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
122 Offset &= 0xFFFFFFFFFULL << 3;
123 return (PMMPTE)(PTE_BASE + Offset);
124 }
125 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
126
127 /* Convert an address to a corresponding PDE */
128 PMMPTE
129 FORCEINLINE
130 _MiAddressToPde(PVOID Address)
131 {
132 ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
133 Offset &= 0x7FFFFFF << 3;
134 return (PMMPTE)(PDE_BASE + Offset);
135 }
136 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
137
138 /* Convert an address to a corresponding PPE */
139 PMMPTE
140 FORCEINLINE
141 MiAddressToPpe(PVOID Address)
142 {
143 ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
144 Offset &= 0x3FFFF << 3;
145 return (PMMPTE)(PPE_BASE + Offset);
146 }
147
148 /* Convert an address to a corresponding PXE */
149 PMMPTE
150 FORCEINLINE
151 MiAddressToPxe(PVOID Address)
152 {
153 ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
154 Offset &= PXI_MASK << 3;
155 return (PMMPTE)(PXE_BASE + Offset);
156 }
157
158 /* Convert an address to a corresponding PTE offset/index */
159 ULONG
160 FORCEINLINE
161 MiAddressToPti(PVOID Address)
162 {
163 return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
164 }
165 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
166
167 /* Convert an address to a corresponding PDE offset/index */
168 ULONG
169 FORCEINLINE
170 MiAddressToPdi(PVOID Address)
171 {
172 return ((((ULONG64)Address) >> PDI_SHIFT) & 0x1FF);
173 }
174 #define MiAddressToPdeOffset(x) MiAddressToPdi(x)
175 #define MiGetPdeOffset(x) MiAddressToPdi(x)
176
177 /* Convert an address to a corresponding PXE offset/index */
178 ULONG
179 FORCEINLINE
180 MiAddressToPxi(PVOID Address)
181 {
182 return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
183 }
184
185 /* Convert a PTE into a corresponding address */
186 PVOID
187 FORCEINLINE
188 MiPteToAddress(PMMPTE PointerPte)
189 {
190 /* Use signed math */
191 return (PVOID)(((LONG64)PointerPte << 25) >> 16);
192 }
193
194 /* Convert a PDE into a corresponding address */
195 PVOID
196 FORCEINLINE
197 MiPdeToAddress(PMMPTE PointerPde)
198 {
199 /* Use signed math */
200 return (PVOID)(((LONG64)PointerPde << 34) >> 16);
201 }
202
203 /* Convert a PPE into a corresponding address */
204 PVOID
205 FORCEINLINE
206 MiPpeToAddress(PMMPTE PointerPpe)
207 {
208 /* Use signed math */
209 return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
210 }
211
212 /* Convert a PXE into a corresponding address */
213 PVOID
214 FORCEINLINE
215 MiPxeToAddress(PMMPTE PointerPxe)
216 {
217 /* Use signed math */
218 return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
219 }
220
221 /* Translate between P*Es */
222 #define MiPdeToPte(_Pde) ((PMMPTE)MiPteToAddress(_Pde))
223 #define MiPteToPde(_Pte) ((PMMPDE)MiAddressToPte(_Pte))
224 #define MiPdeToPpe(_Pde) ((PMMPPE)MiAddressToPte(_Pde))
225
226 /* Check P*E boundaries */
227 #define MiIsPteOnPdeBoundary(PointerPte) \
228 ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
229 #define MiIsPteOnPpeBoundary(PointerPte) \
230 ((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
231 #define MiIsPteOnPxeBoundary(PointerPte) \
232 ((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
233
234 //
235 // Decodes a Prototype PTE into the underlying PTE
236 //
237 #define MiProtoPteToPte(x) \
238 (PMMPTE)(((LONG64)(x)->u.Long) >> 16) /* Sign extend 48 bits */
239
240 //
241 // Decodes a Prototype PTE into the underlying PTE
242 //
243 #define MiSubsectionPteToSubsection(x) \
244 (PMMPTE)((x)->u.Subsect.SubsectionAddress >> 16)
245
246 FORCEINLINE
247 VOID
248 MI_MAKE_SUBSECTION_PTE(
249 _Out_ PMMPTE NewPte,
250 _In_ PVOID Segment)
251 {
252 ULONG_PTR Offset;
253
254 /* Mark this as a prototype */
255 NewPte->u.Long = 0;
256 NewPte->u.Subsect.Prototype = 1;
257
258 /* Store the lower 48 bits of the Segment address */
259 NewPte->u.Subsect.SubsectionAddress = ((ULONG_PTR)Segment & 0x0000FFFFFFFFFFFF);
260 }
261
262 FORCEINLINE
263 VOID
264 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
265 IN PMMPTE PointerPte)
266 {
267 /* Store the Address */
268 NewPte->u.Long = (ULONG64)PointerPte << 16;
269
270 /* Mark this as a prototype PTE */
271 NewPte->u.Proto.Prototype = 1;
272
273 ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
274 }
275
276 FORCEINLINE
277 BOOLEAN
278 MI_IS_MAPPED_PTE(PMMPTE PointerPte)
279 {
280 /// FIXME
281 __debugbreak();
282 return ((PointerPte->u.Long & 0xFFFFFC01) != 0);
283 }
284
285 VOID
286 FORCEINLINE
287 MmInitGlobalKernelPageDirectory(VOID)
288 {
289 /* Nothing to do */
290 }
291
292 BOOLEAN
293 FORCEINLINE
294 MiIsPdeForAddressValid(PVOID Address)
295 {
296 return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
297 (MiAddressToPpe(Address)->u.Hard.Valid) &&
298 (MiAddressToPde(Address)->u.Hard.Valid));
299 }
300