ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * kernel internal memory managment definitions for amd64
   3  */
   4 #pragma once
   5
   6 /* Memory layout base addresses */
   7 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x000000007FF00000ULL
   8 #define MI_HIGHEST_USER_ADDRESS         (PVOID)0x000007FFFFFEFFFFULL
   9 #define MI_USER_PROBE_ADDRESS           (PVOID)0x000007FFFFFF0000ULL
  10 #define MI_DEFAULT_SYSTEM_RANGE_START   (PVOID)0xFFFF080000000000ULL
  11 #define MI_REAL_SYSTEM_RANGE_START             0xFFFF800000000000ULL
  12 #define MI_PAGE_TABLE_BASE                     0xFFFFF68000000000ULL
  13 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  14 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  15 #define MI_SHARED_SYSTEM_PAGE                  0xFFFFF78000000000ULL
  16 #define MI_SYSTEM_CACHE_WS_START               0xFFFFF78000001000ULL
  17 #define MI_LOADER_MAPPINGS                     0xFFFFF80000000000ULL
  18 #define MI_PAGED_SYSTEM_START                  0xFFFFF88000000000ULL
  19 #define MI_PAGED_POOL_START             (PVOID)0xFFFFF8A000000000ULL
  20 #define MI_PAGED_POOL_END                      0xFFFFF8BFFFFFFFFFULL
  21 #define MI_SESSION_SPACE_START                 0xFFFFF90000000000ULL
  22 #define MI_SESSION_VIEW_END                    0xFFFFF97FFF000000ULL
  23 #define MI_SESSION_SPACE_END                   0xFFFFF97FFFFFFFFFULL
  24 #define MM_SYSTEM_SPACE_START                  0xFFFFF98000000000ULL
  25 #define MI_PFN_DATABASE                        0xFFFFFA8000000000ULL
  26 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  27
  28 /* WOW64 address definitions */
  29 #define MM_HIGHEST_USER_ADDRESS_WOW64   0x7FFEFFFF
  30 #define MM_SYSTEM_RANGE_START_WOW64     0x80000000
  31
  32 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  33 #define MI_NON_PAGED_SYSTEM_START_MIN   MM_SYSTEM_SPACE_START // FIXME
  34 #define MI_SYSTEM_PTE_START             MM_SYSTEM_SPACE_START
  35 #define MI_SYSTEM_PTE_END               (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
  36 #define MI_SYSTEM_PTE_BASE              (PVOID)MiAddressToPte(KSEG0_BASE)
  37 #define MM_HIGHEST_VAD_ADDRESS          (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  38 #define MI_MAPPING_RANGE_START          HYPER_SPACE
  39 #define MI_MAPPING_RANGE_END            (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
  40 #define MI_DUMMY_PTE                        (MI_MAPPING_RANGE_END + PAGE_SIZE)
  41 #define MI_VAD_BITMAP                       (MI_DUMMY_PTE + PAGE_SIZE)
  42 #define MI_WORKING_SET_LIST                 (MI_VAD_BITMAP + PAGE_SIZE)
  43 #define MI_NONPAGED_POOL_END 0
  44
  45 /* Memory sizes */
  46 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  47 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING        ((19*1024*1024) >> PAGE_SHIFT)
  48 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST         ((32*1024*1024) >> PAGE_SHIFT)
  49 #define MI_MIN_INIT_PAGED_POOLSIZE            (32 * 1024 * 1024)
  50 #define MI_MAX_INIT_NONPAGED_POOL_SIZE        (128ULL * 1024 * 1024 * 1024)
  51 #define MI_MAX_NONPAGED_POOL_SIZE             (128ULL * 1024 * 1024 * 1024)
  52 #define MI_SYSTEM_VIEW_SIZE                   (16 * 1024 * 1024)
  53 #define MI_MIN_SECONDARY_COLORS               8
  54 #define MI_SECONDARY_COLORS                   64
  55 #define MI_MAX_SECONDARY_COLORS               1024
  56 #define MI_MIN_ALLOCATION_FRAGMENT            (4 * _1KB)
  57 #define MI_ALLOCATION_FRAGMENT                (64 * _1KB)
  58 #define MI_MAX_ALLOCATION_FRAGMENT            (2  * _1MB)
  59 #define MI_SESSION_WORKING_SET_SIZE           (4 * 1024 * 1024)
  60 #define MI_SESSION_VIEW_SIZE                  (20 * 1024 * 1024)
  61 #define MI_SESSION_POOL_SIZE                  (16 * 1024 * 1024)
  62 #define MI_SESSION_IMAGE_SIZE                 (8 * 1024 * 1024)
  63 #define MI_SESSION_SIZE                       (MI_SESSION_VIEW_SIZE + \
  64                                                MI_SESSION_POOL_SIZE + \
  65                                                MI_SESSION_IMAGE_SIZE + \
  66                                                MI_SESSION_WORKING_SET_SIZE)
  67
  68 #define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
  69
  70 /* Misc constants */
  71 #define _MI_PAGING_LEVELS                   4
  72 #define MI_NUMBER_SYSTEM_PTES               22000
  73 #define MI_MAX_FREE_PAGE_LISTS              4
  74 #define NR_SECTION_PAGE_TABLES              1024
  75 #define NR_SECTION_PAGE_ENTRIES             1024
  76 #define MI_HYPERSPACE_PTES                  (256 - 1)
  77 #define MI_ZERO_PTES                        (32)
  78 /* FIXME - different architectures have different cache line sizes... */
  79 #define MM_CACHE_LINE_SIZE                  32
  80
  81 /* Helper macros */
  82 #define PAGE_MASK(x)            ((x)&(~0xfff))
  83 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  84 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
  85 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
  86
  87 #define MiIsPteOnPdeBoundary(PointerPte) \
  88     ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
  89 #define MiIsPteOnPpeBoundary(PointerPte) \
  90     ((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
  91 #define MiIsPteOnPxeBoundary(PointerPte) \
  92     ((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
  93
  94 /* MMPTE related defines */
  95 #define MM_EMPTY_PTE_LIST  ((ULONG64)0xFFFFFFFF)
  96 #define MM_EMPTY_LIST  ((ULONG_PTR)-1)
  97
  98 #define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
  99 #define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
 100 #define ADDR_TO_PTE_OFFSET(v)  ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
 101
 102 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
 103
 104 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 105 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 106 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 107 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 108
 109 /* Easy accessing PFN in PTE */
 110 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 111 #define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
 112 #define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
 113 #define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
 114
 115 // FIXME, only copied from x86
 116 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 117 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 118 #define MI_MAKE_ACCESSED_PAGE(x)   ((x)->u.Hard.Accessed = 1)
 119 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 120 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 121 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 122 #define MI_IS_PAGE_LARGE(x)        ((x)->u.Hard.LargePage == 1)
 123 #if !defined(CONFIG_SMP)
 124 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 125 #else
 126 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 127 #endif
 128 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 129 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 130 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 131 #if !defined(CONFIG_SMP)
 132 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 133 #else
 134 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 135 #endif
 136
 137 // FIXME!!!
 138 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 139     ((x) / (4*1024*1024))
 140 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 141     ((((x)) % (4*1024*1024)) / (4*1024))
 142
 143 //#define TEB_BASE                            0x7FFDE000
 144
 145 /* On x86, these two are the same */
 146 #define MMPDE MMPTE
 147 #define PMMPDE PMMPTE
 148 #define MMPPE MMPTE
 149 #define PMMPPE PMMPTE
 150 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
 151
 152 #define ValidKernelPpe ValidKernelPde
 153
 154 PULONG64
 155 FORCEINLINE
 156 MmGetPageDirectory(VOID)
 157 {
 158     return (PULONG64)__readcr3();
 159 }
 160
 161 PMMPTE
 162 FORCEINLINE
 163 MiAddressToPxe(PVOID Address)
 164 {
 165     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
 166     Offset &= PXI_MASK << 3;
 167     return (PMMPTE)(PXE_BASE + Offset);
 168 }
 169
 170 PMMPTE
 171 FORCEINLINE
 172 MiAddressToPpe(PVOID Address)
 173 {
 174     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
 175     Offset &= 0x3FFFF << 3;
 176     return (PMMPTE)(PPE_BASE + Offset);
 177 }
 178
 179 PMMPTE
 180 FORCEINLINE
 181 _MiAddressToPde(PVOID Address)
 182 {
 183     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
 184     Offset &= 0x7FFFFFF << 3;
 185     return (PMMPTE)(PDE_BASE + Offset);
 186 }
 187 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
 188
 189 PMMPTE
 190 FORCEINLINE
 191 _MiAddressToPte(PVOID Address)
 192 {
 193     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
 194     Offset &= 0xFFFFFFFFFULL << 3;
 195     return (PMMPTE)(PTE_BASE + Offset);
 196 }
 197 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
 198
 199 ULONG
 200 FORCEINLINE
 201 MiAddressToPti(PVOID Address)
 202 {
 203     return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
 204 }
 205 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
 206
 207 ULONG
 208 FORCEINLINE
 209 MiAddressToPxi(PVOID Address)
 210 {
 211     return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
 212 }
 213
 214
 215 /* Convert a PTE into a corresponding address */
 216 PVOID
 217 FORCEINLINE
 218 MiPteToAddress(PMMPTE PointerPte)
 219 {
 220     /* Use signed math */
 221     return (PVOID)(((LONG64)PointerPte << 25) >> 16);
 222 }
 223
 224 PVOID
 225 FORCEINLINE
 226 MiPdeToAddress(PMMPTE PointerPde)
 227 {
 228     /* Use signed math */
 229     return (PVOID)(((LONG64)PointerPde << 34) >> 16);
 230 }
 231
 232 PVOID
 233 FORCEINLINE
 234 MiPpeToAddress(PMMPTE PointerPpe)
 235 {
 236     /* Use signed math */
 237     return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
 238 }
 239
 240 PVOID
 241 FORCEINLINE
 242 MiPxeToAddress(PMMPTE PointerPxe)
 243 {
 244     /* Use signed math */
 245     return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
 246 }
 247
 248 BOOLEAN
 249 FORCEINLINE
 250 MiIsPdeForAddressValid(PVOID Address)
 251 {
 252     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 253             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 254             (MiAddressToPde(Address)->u.Hard.Valid));
 255 }
 256
 257 #define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
 258 #define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
 259
 260 FORCEINLINE
 261 VOID
 262 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 263                       IN PMMPTE PointerPte)
 264 {
 265     /* Store the Address */
 266     NewPte->u.Long = (ULONG64)PointerPte;
 267
 268     /* Mark this as a prototype PTE */
 269     NewPte->u.Proto.Prototype = 1;
 270     NewPte->u.Proto.Valid  = 1;
 271     NewPte->u.Proto.ReadOnly = 0;
 272     NewPte->u.Proto.Protection = 0;
 273 }
 274
 275 /* Sign extend 48 bits */
 276 #define MiProtoPteToPte(x) (PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress)
 277
 278 VOID
 279 FORCEINLINE
 280 MmInitGlobalKernelPageDirectory(VOID)
 281 {
 282     /* Nothing to do */
 283 }
 284