ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * kernel internal memory managment definitions for amd64
   3  */
   4 #pragma once
   5
   6 /* Memory layout base addresses */
   7 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x000000007FF00000ULL
   8 #define MI_HIGHEST_USER_ADDRESS         (PVOID)0x000007FFFFFEFFFFULL
   9 #define MI_USER_PROBE_ADDRESS           (PVOID)0x000007FFFFFF0000ULL
  10 #define MI_DEFAULT_SYSTEM_RANGE_START   (PVOID)0xFFFF080000000000ULL
  11 #define MI_REAL_SYSTEM_RANGE_START             0xFFFF800000000000ULL
  12 #define MI_PAGE_TABLE_BASE                     0xFFFFF68000000000ULL
  13 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  14 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  15 #define MI_SHARED_SYSTEM_PAGE                  0xFFFFF78000000000ULL
  16 #define MI_SYSTEM_CACHE_WS_START               0xFFFFF78000001000ULL
  17 #define MI_LOADER_MAPPINGS                     0xFFFFF80000000000ULL
  18 #define MI_PAGED_SYSTEM_START                  0xFFFFF88000000000ULL
  19 #define MI_PAGED_POOL_START             (PVOID)0xFFFFF8A000000000ULL
  20 #define MI_PAGED_POOL_END                      0xFFFFF8BFFFFFFFFFULL
  21 #define MI_SESSION_SPACE_START                 0xFFFFF90000000000ULL
  22 #define MI_SESSION_VIEW_END                    0xFFFFF97FFF000000ULL
  23 #define MI_SESSION_SPACE_END                   0xFFFFF97FFFFFFFFFULL
  24 #define MM_SYSTEM_SPACE_START                  0xFFFFF98000000000ULL
  25 #define MI_PFN_DATABASE                        0xFFFFFA8000000000ULL
  26 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  27
  28 /* WOW64 address definitions */
  29 #define MM_HIGHEST_USER_ADDRESS_WOW64   0x7FFEFFFF
  30 #define MM_SYSTEM_RANGE_START_WOW64     0x80000000
  31
  32 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  33 #define MI_NON_PAGED_SYSTEM_START_MIN   MM_SYSTEM_SPACE_START // FIXME
  34 #define MI_SYSTEM_PTE_START             MM_SYSTEM_SPACE_START
  35 #define MI_SYSTEM_PTE_END               (MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
  36 #define MI_SYSTEM_PTE_BASE              (PVOID)MiAddressToPte(KSEG0_BASE)
  37 #define MM_HIGHEST_VAD_ADDRESS          (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  38 #define MI_MAPPING_RANGE_START          HYPER_SPACE
  39 #define MI_MAPPING_RANGE_END            (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
  40 #define MI_DUMMY_PTE                        (MI_MAPPING_RANGE_END + PAGE_SIZE)
  41 #define MI_VAD_BITMAP                       (MI_DUMMY_PTE + PAGE_SIZE)
  42 #define MI_WORKING_SET_LIST                 (MI_VAD_BITMAP + PAGE_SIZE)
  43 #define MI_NONPAGED_POOL_END 0
  44
  45 /* Memory sizes */
  46 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  47 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING        ((19*1024*1024) >> PAGE_SHIFT)
  48 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST         ((32*1024*1024) >> PAGE_SHIFT)
  49 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST_BOOST   ((256*1024*1024) >> PAGE_SHIFT)
  50 #define MI_MIN_INIT_PAGED_POOLSIZE            (32 * 1024 * 1024)
  51 #define MI_MAX_INIT_NONPAGED_POOL_SIZE        (128ULL * 1024 * 1024 * 1024)
  52 #define MI_MAX_NONPAGED_POOL_SIZE             (128ULL * 1024 * 1024 * 1024)
  53 #define MI_SYSTEM_VIEW_SIZE                   (16 * 1024 * 1024)
  54 #define MI_MIN_SECONDARY_COLORS               8
  55 #define MI_SECONDARY_COLORS                   64
  56 #define MI_MAX_SECONDARY_COLORS               1024
  57 #define MI_MIN_ALLOCATION_FRAGMENT            (4 * _1KB)
  58 #define MI_ALLOCATION_FRAGMENT                (64 * _1KB)
  59 #define MI_MAX_ALLOCATION_FRAGMENT            (2  * _1MB)
  60 #define MI_SESSION_WORKING_SET_SIZE           (4 * 1024 * 1024)
  61 #define MI_SESSION_VIEW_SIZE                  (20 * 1024 * 1024)
  62 #define MI_SESSION_POOL_SIZE                  (16 * 1024 * 1024)
  63 #define MI_SESSION_IMAGE_SIZE                 (8 * 1024 * 1024)
  64 #define MI_SESSION_SIZE                       (MI_SESSION_VIEW_SIZE + \
  65                                                MI_SESSION_POOL_SIZE + \
  66                                                MI_SESSION_IMAGE_SIZE + \
  67                                                MI_SESSION_WORKING_SET_SIZE)
  68
  69 #define MmSystemRangeStart ((PVOID)MI_REAL_SYSTEM_RANGE_START)
  70
  71 /* Misc constants */
  72 #define _MI_PAGING_LEVELS                   4
  73 #define MI_NUMBER_SYSTEM_PTES               22000
  74 #define MI_MAX_FREE_PAGE_LISTS              4
  75 #define NR_SECTION_PAGE_TABLES              1024
  76 #define NR_SECTION_PAGE_ENTRIES             1024
  77 #define MI_HYPERSPACE_PTES                  (256 - 1)
  78 #define MI_ZERO_PTES                        (32)
  79 /* FIXME - different architectures have different cache line sizes... */
  80 #define MM_CACHE_LINE_SIZE                  32
  81 #define MI_MAX_ZERO_BITS                    53
  82
  83 /* Helper macros */
  84 #define PAGE_MASK(x)            ((x)&(~0xfff))
  85 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  86 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
  87 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
  88
  89 #define MiIsPteOnPdeBoundary(PointerPte) \
  90     ((((ULONG_PTR)PointerPte) & (PAGE_SIZE - 1)) == 0)
  91 #define MiIsPteOnPpeBoundary(PointerPte) \
  92     ((((ULONG_PTR)PointerPte) & (PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
  93 #define MiIsPteOnPxeBoundary(PointerPte) \
  94     ((((ULONG_PTR)PointerPte) & (PPE_PER_PAGE * PDE_PER_PAGE * PAGE_SIZE - 1)) == 0)
  95
  96 /* MMPTE related defines */
  97 #define MM_EMPTY_PTE_LIST  ((ULONG64)0xFFFFFFFF)
  98 #define MM_EMPTY_LIST  ((ULONG_PTR)-1)
  99
 100 #define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
 101 #define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
 102 #define ADDR_TO_PTE_OFFSET(v)  ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
 103
 104 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
 105
 106 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
 107 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
 108 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
 109 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
 110
 111 /* Easy accessing PFN in PTE */
 112 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 113 #define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
 114 #define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
 115 #define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
 116
 117 // FIXME, only copied from x86
 118 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 119 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 120 #define MI_MAKE_ACCESSED_PAGE(x)   ((x)->u.Hard.Accessed = 1)
 121 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 122 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 123 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 124 #define MI_IS_PAGE_LARGE(x)        ((x)->u.Hard.LargePage == 1)
 125 #if !defined(CONFIG_SMP)
 126 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 127 #else
 128 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 129 #endif
 130 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 131 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 132 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 133 #if !defined(CONFIG_SMP)
 134 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 135 #else
 136 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 137 #endif
 138
 139 // FIXME!!!
 140 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 141     ((x) / (4*1024*1024))
 142 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 143     ((((x)) % (4*1024*1024)) / (4*1024))
 144
 145 //#define TEB_BASE                            0x7FFDE000
 146
 147 /* On x64, these are the same */
 148 #define MMPDE MMPTE
 149 #define PMMPDE PMMPTE
 150 #define MMPPE MMPTE
 151 #define PMMPPE PMMPTE
 152 #define MMPXE MMPTE
 153 #define PMMPXE PMMPTE
 154 #define MI_WRITE_VALID_PPE MI_WRITE_VALID_PTE
 155
 156 #define ValidKernelPpe ValidKernelPde
 157
 158 PULONG64
 159 FORCEINLINE
 160 MmGetPageDirectory(VOID)
 161 {
 162     return (PULONG64)__readcr3();
 163 }
 164
 165 PMMPTE
 166 FORCEINLINE
 167 MiAddressToPxe(PVOID Address)
 168 {
 169     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
 170     Offset &= PXI_MASK << 3;
 171     return (PMMPTE)(PXE_BASE + Offset);
 172 }
 173
 174 PMMPTE
 175 FORCEINLINE
 176 MiAddressToPpe(PVOID Address)
 177 {
 178     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
 179     Offset &= 0x3FFFF << 3;
 180     return (PMMPTE)(PPE_BASE + Offset);
 181 }
 182
 183 PMMPTE
 184 FORCEINLINE
 185 _MiAddressToPde(PVOID Address)
 186 {
 187     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
 188     Offset &= 0x7FFFFFF << 3;
 189     return (PMMPTE)(PDE_BASE + Offset);
 190 }
 191 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
 192
 193 PMMPTE
 194 FORCEINLINE
 195 _MiAddressToPte(PVOID Address)
 196 {
 197     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
 198     Offset &= 0xFFFFFFFFFULL << 3;
 199     return (PMMPTE)(PTE_BASE + Offset);
 200 }
 201 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
 202
 203 ULONG
 204 FORCEINLINE
 205 MiAddressToPti(PVOID Address)
 206 {
 207     return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
 208 }
 209 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
 210
 211 ULONG
 212 FORCEINLINE
 213 MiAddressToPxi(PVOID Address)
 214 {
 215     return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
 216 }
 217
 218
 219 /* Convert a PTE into a corresponding address */
 220 PVOID
 221 FORCEINLINE
 222 MiPteToAddress(PMMPTE PointerPte)
 223 {
 224     /* Use signed math */
 225     return (PVOID)(((LONG64)PointerPte << 25) >> 16);
 226 }
 227
 228 PVOID
 229 FORCEINLINE
 230 MiPdeToAddress(PMMPTE PointerPde)
 231 {
 232     /* Use signed math */
 233     return (PVOID)(((LONG64)PointerPde << 34) >> 16);
 234 }
 235
 236 PVOID
 237 FORCEINLINE
 238 MiPpeToAddress(PMMPTE PointerPpe)
 239 {
 240     /* Use signed math */
 241     return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
 242 }
 243
 244 PVOID
 245 FORCEINLINE
 246 MiPxeToAddress(PMMPTE PointerPxe)
 247 {
 248     /* Use signed math */
 249     return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
 250 }
 251
 252 BOOLEAN
 253 FORCEINLINE
 254 MiIsPdeForAddressValid(PVOID Address)
 255 {
 256     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 257             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 258             (MiAddressToPde(Address)->u.Hard.Valid));
 259 }
 260
 261 #define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
 262 #define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
 263 #define MiPdeToPpe(Pde) ((PMMPPE)MiAddressToPte(Pde))
 264
 265 /* Sign extend 48 bits */
 266 #define MiProtoPteToPte(x) (PMMPTE)(((LONG64)(x)->u.Long) >> 16)
 267
 268 //
 269 // Decodes a Prototype PTE into the underlying PTE
 270 //
 271 #define MiSubsectionPteToSubsection(x)                              \
 272         (PMMPTE)((x)->u.Subsect.SubsectionAddress >> 16)
 273
 274 FORCEINLINE
 275 VOID
 276 MI_MAKE_SUBSECTION_PTE(IN PMMPTE NewPte,
 277                        IN PVOID Segment)
 278 {
 279     ASSERT(FALSE);
 280 }
 281
 282 FORCEINLINE
 283 VOID
 284 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 285                       IN PMMPTE PointerPte)
 286 {
 287     /* Store the Address */
 288     NewPte->u.Long = (ULONG64)PointerPte << 16;
 289
 290     /* Mark this as a prototype PTE */
 291     NewPte->u.Proto.Prototype = 1;
 292
 293     ASSERT(MiProtoPteToPte(NewPte) == PointerPte);
 294 }
 295
 296 FORCEINLINE
 297 BOOLEAN
 298 MI_IS_MAPPED_PTE(PMMPTE PointerPte)
 299 {
 300     /// FIXME
 301     __debugbreak();
 302     return ((PointerPte->u.Long & 0xFFFFFC01) != 0);
 303 }
 304
 305 VOID
 306 FORCEINLINE
 307 MmInitGlobalKernelPageDirectory(VOID)
 308 {
 309     /* Nothing to do */
 310 }
 311