ntoskrnl/include/internal/amd64/mm.h

   1 /*
   2  * kernel internal memory managment definitions for amd64
   3  */
   4 #pragma once
   5
   6 /* Memory layout base addresses */
   7 #define MI_LOWEST_VAD_ADDRESS           (PVOID)0x000000007FF00000ULL
   8 #define MI_HIGHEST_USER_ADDRESS         (PVOID)0x000007FFFFFEFFFFULL
   9 #define MI_USER_PROBE_ADDRESS           (PVOID)0x000007FFFFFF0000ULL
  10 #define MI_DEFAULT_SYSTEM_RANGE_START   (PVOID)0xFFFF080000000000ULL
  11 #define HYPER_SPACE                            0xFFFFF70000000000ULL
  12 #define HYPER_SPACE_END                        0xFFFFF77FFFFFFFFFULL
  13 #define MI_SESSION_SPACE_MINIMUM        (PVOID)0xFFFFF90000000000ULL
  14 #define MI_SESSION_VIEW_END             (PVOID)0xFFFFF97FFF000000ULL
  15 #define MI_SESSION_SPACE_END            (PVOID)0xFFFFF98000000000ULL
  16 #define MI_SYSTEM_PTE_START             (PVOID)0xFFFFFAA000000000ULL
  17 #define MI_PAGED_POOL_START             (PVOID)0xFFFFFA8000000000ULL
  18 #define MI_NON_PAGED_SYSTEM_START_MIN          0xFFFFFAA000000000ULL
  19 #define MI_PFN_DATABASE                 (PVOID)0xFFFFFAC000000000ULL
  20 #define MI_NONPAGED_POOL_END            (PVOID)0xFFFFFAE000000000ULL
  21 #define MI_DEBUG_MAPPING                (PVOID)0xFFFFFFFF80000000ULL // FIXME
  22 #define MI_HIGHEST_SYSTEM_ADDRESS       (PVOID)0xFFFFFFFFFFFFFFFFULL
  23 #define MI_SYSTEM_CACHE_WS_START        (PVOID)0xFFFFF78000001000ULL // CHECKME
  24
  25 #define MM_HIGHEST_USER_ADDRESS_WOW64   0x7FFEFFFF
  26 #define MM_SYSTEM_RANGE_START_WOW64     0x80000000
  27
  28
  29 #define MI_SYSTEM_PTE_END               (PVOID)((ULONG64)MI_SYSTEM_PTE_START + MI_NUMBER_SYSTEM_PTES * PAGE_SIZE - 1)
  30 #define MI_SYSTEM_PTE_BASE              (PVOID)MiAddressToPte(KSEG0_BASE)
  31 #define MM_HIGHEST_VAD_ADDRESS          (PVOID)((ULONG_PTR)MM_HIGHEST_USER_ADDRESS - (16 * PAGE_SIZE))
  32 #define MI_MAPPING_RANGE_START          (ULONG64)HYPER_SPACE
  33 #define MI_MAPPING_RANGE_END            (MI_MAPPING_RANGE_START + MI_HYPERSPACE_PTES * PAGE_SIZE)
  34
  35 /* Memory sizes */
  36 #define MI_MIN_PAGES_FOR_NONPAGED_POOL_TUNING ((255*1024*1024) >> PAGE_SHIFT)
  37 #define MI_MIN_PAGES_FOR_SYSPTE_TUNING        ((19*1024*1024) >> PAGE_SHIFT)
  38 #define MI_MIN_PAGES_FOR_SYSPTE_BOOST         ((32*1024*1024) >> PAGE_SHIFT)
  39 #define MI_MIN_INIT_PAGED_POOLSIZE            (32 * 1024 * 1024)
  40 #define MI_MAX_INIT_NONPAGED_POOL_SIZE        (128ULL * 1024 * 1024 * 1024)
  41 #define MI_MAX_NONPAGED_POOL_SIZE             (128ULL * 1024 * 1024 * 1024)
  42 #define MI_SYSTEM_VIEW_SIZE                   (16 * 1024 * 1024)
  43 #define MI_MIN_SECONDARY_COLORS               8
  44 #define MI_SECONDARY_COLORS                   64
  45 #define MI_MAX_SECONDARY_COLORS               1024
  46 #define MI_MIN_ALLOCATION_FRAGMENT            (4 * _1KB)
  47 #define MI_ALLOCATION_FRAGMENT                (64 * _1KB)
  48 #define MI_MAX_ALLOCATION_FRAGMENT            (2  * _1MB)
  49 #define MI_SESSION_WORKING_SET_SIZE           (4 * 1024 * 1024)
  50 #define MI_SESSION_VIEW_SIZE                  (20 * 1024 * 1024)
  51 #define MI_SESSION_POOL_SIZE                  (16 * 1024 * 1024)
  52 #define MI_SESSION_IMAGE_SIZE                 (8 * 1024 * 1024)
  53 #define MI_SESSION_SIZE                       (MI_SESSION_VIEW_SIZE + \
  54                                                MI_SESSION_POOL_SIZE + \
  55                                                MI_SESSION_IMAGE_SIZE + \
  56                                                MI_SESSION_WORKING_SET_SIZE)
  57
  58 /* Misc constants */
  59 #define _MI_PAGING_LEVELS                   4
  60 #define MI_NUMBER_SYSTEM_PTES               22000
  61 #define MI_MAX_FREE_PAGE_LISTS              4
  62 #define NR_SECTION_PAGE_TABLES              1024
  63 #define NR_SECTION_PAGE_ENTRIES             1024
  64 #define MI_HYPERSPACE_PTES                  (256 - 1)
  65 #define MI_ZERO_PTES                        (32)
  66 #define MI_DUMMY_PTE                        (PMMPTE)(MI_MAPPING_RANGE_END + PAGE_SIZE)
  67 #define MI_VAD_BITMAP                       (PMMPTE)(MI_DUMMY_PTE + PAGE_SIZE)
  68 #define MI_WORKING_SET_LIST                 (PMMPTE)(MI_VAD_BITMAP + PAGE_SIZE)
  69 /* FIXME - different architectures have different cache line sizes... */
  70 #define MM_CACHE_LINE_SIZE                  32
  71
  72 /* Helper macros */
  73 #define PAGE_MASK(x)            ((x)&(~0xfff))
  74 #define PAE_PAGE_MASK(x)        ((x)&(~0xfffLL))
  75 #define IS_ALIGNED(addr, align) (((ULONG64)(addr) & (align - 1)) == 0)
  76 #define IS_PAGE_ALIGNED(addr) IS_ALIGNED(addr, PAGE_SIZE)
  77
  78 /* MMPTE related defines */
  79 #define MM_EMPTY_PTE_LIST  ((ULONG64)0xFFFFFFFF)
  80 #define MM_EMPTY_LIST  ((ULONG_PTR)-1)
  81
  82 #define ADDR_TO_PAGE_TABLE(v) ((ULONG)(((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
  83 #define ADDR_TO_PDE_OFFSET(v) ((ULONG)((((ULONG_PTR)(v)) / (512 * PAGE_SIZE))))
  84 #define ADDR_TO_PTE_OFFSET(v)  ((ULONG)((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE))
  85
  86 #define MiGetPdeOffset ADDR_TO_PDE_OFFSET
  87
  88 #define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
  89 #define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
  90 #define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
  91 #define VAtoPTI(va) ((((ULONG64)va) >> PTI_SHIFT) & 0x1FF)
  92
  93 /* Easy accessing PFN in PTE */
  94 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
  95 #define PFN_FROM_PDE(v) ((v)->u.Hard.PageFrameNumber)
  96 #define PFN_FROM_PPE(v) ((v)->u.Hard.PageFrameNumber)
  97 #define PFN_FROM_PXE(v) ((v)->u.Hard.PageFrameNumber)
  98
  99 // FIXME, only copied from x86
 100 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.Global = 0)
 101 #define MI_MAKE_DIRTY_PAGE(x)      ((x)->u.Hard.Dirty = 1)
 102 #define MI_MAKE_ACCESSED_PAGE(x)   ((x)->u.Hard.Accessed = 1)
 103 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.CacheDisable = 1)
 104 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.WriteThrough = 1)
 105 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.WriteThrough = 0)
 106 #define MI_IS_PAGE_LARGE(x)        ((x)->u.Hard.LargePage == 1)
 107 #if !defined(CONFIG_SMP)
 108 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Write == 1)
 109 #else
 110 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.Writable == 1)
 111 #endif
 112 #define MI_IS_PAGE_COPY_ON_WRITE(x)((x)->u.Hard.CopyOnWrite == 1)
 113 #define MI_IS_PAGE_DIRTY(x)        ((x)->u.Hard.Dirty == 1)
 114 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 115 #if !defined(CONFIG_SMP)
 116 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Write = 1)
 117 #else
 118 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.Writable = 1)
 119 #endif
 120
 121 // FIXME!!!
 122 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 123     ((x) / (4*1024*1024))
 124 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 125     ((((x)) % (4*1024*1024)) / (4*1024))
 126
 127 //#define TEB_BASE                            0x7FFDE000
 128
 129 /* On x86, these two are the same */
 130 #define MMPDE MMPTE
 131 #define PMMPDE PMMPTE
 132
 133 PULONG64
 134 FORCEINLINE
 135 MmGetPageDirectory(VOID)
 136 {
 137     return (PULONG64)__readcr3();
 138 }
 139
 140 PMMPTE
 141 FORCEINLINE
 142 MiAddressToPxe(PVOID Address)
 143 {
 144     ULONG64 Offset = (ULONG64)Address >> (PXI_SHIFT - 3);
 145     Offset &= PXI_MASK << 3;
 146     return (PMMPTE)(PXE_BASE + Offset);
 147 }
 148
 149 PMMPTE
 150 FORCEINLINE
 151 MiAddressToPpe(PVOID Address)
 152 {
 153     ULONG64 Offset = (ULONG64)Address >> (PPI_SHIFT - 3);
 154     Offset &= 0x3FFFF << 3;
 155     return (PMMPTE)(PPE_BASE + Offset);
 156 }
 157
 158 PMMPTE
 159 FORCEINLINE
 160 _MiAddressToPde(PVOID Address)
 161 {
 162     ULONG64 Offset = (ULONG64)Address >> (PDI_SHIFT - 3);
 163     Offset &= 0x7FFFFFF << 3;
 164     return (PMMPTE)(PDE_BASE + Offset);
 165 }
 166 #define MiAddressToPde(x) _MiAddressToPde((PVOID)(x))
 167
 168 PMMPTE
 169 FORCEINLINE
 170 _MiAddressToPte(PVOID Address)
 171 {
 172     ULONG64 Offset = (ULONG64)Address >> (PTI_SHIFT - 3);
 173     Offset &= 0xFFFFFFFFFULL << 3;
 174     return (PMMPTE)(PTE_BASE + Offset);
 175 }
 176 #define MiAddressToPte(x) _MiAddressToPte((PVOID)(x))
 177
 178 ULONG
 179 FORCEINLINE
 180 MiAddressToPti(PVOID Address)
 181 {
 182     return ((((ULONG64)Address) >> PTI_SHIFT) & 0x1FF);
 183 }
 184 #define MiAddressToPteOffset(x) MiAddressToPti(x) // FIXME: bad name
 185
 186 ULONG
 187 FORCEINLINE
 188 MiAddressToPxi(PVOID Address)
 189 {
 190     return ((((ULONG64)Address) >> PXI_SHIFT) & 0x1FF);
 191 }
 192
 193
 194 /* Convert a PTE into a corresponding address */
 195 PVOID
 196 FORCEINLINE
 197 MiPteToAddress(PMMPTE PointerPte)
 198 {
 199     /* Use signed math */
 200     return (PVOID)(((LONG64)PointerPte << 25) >> 16);
 201 }
 202
 203 PVOID
 204 FORCEINLINE
 205 MiPdeToAddress(PMMPTE PointerPde)
 206 {
 207     /* Use signed math */
 208     return (PVOID)(((LONG64)PointerPde << 34) >> 16);
 209 }
 210
 211 PVOID
 212 FORCEINLINE
 213 MiPpeToAddress(PMMPTE PointerPpe)
 214 {
 215     /* Use signed math */
 216     return (PVOID)(((LONG64)PointerPpe << 43) >> 16);
 217 }
 218
 219 PVOID
 220 FORCEINLINE
 221 MiPxeToAddress(PMMPTE PointerPxe)
 222 {
 223     /* Use signed math */
 224     return (PVOID)(((LONG64)PointerPxe << 52) >> 16);
 225 }
 226
 227 BOOLEAN
 228 FORCEINLINE
 229 MiIsPdeForAddressValid(PVOID Address)
 230 {
 231     return ((MiAddressToPxe(Address)->u.Hard.Valid) &&
 232             (MiAddressToPpe(Address)->u.Hard.Valid) &&
 233             (MiAddressToPde(Address)->u.Hard.Valid));
 234 }
 235
 236 #define MiPdeToPte(PDE) ((PMMPTE)MiPteToAddress(PDE))
 237 #define MiPteToPde(PTE) ((PMMPDE)MiAddressToPte(PTE))
 238
 239 FORCEINLINE
 240 VOID
 241 MI_MAKE_PROTOTYPE_PTE(IN PMMPTE NewPte,
 242                       IN PMMPTE PointerPte)
 243 {
 244     /* Store the Address */
 245     NewPte->u.Long = (ULONG64)PointerPte;
 246
 247     /* Mark this as a prototype PTE */
 248     NewPte->u.Proto.Prototype = 1;
 249     NewPte->u.Proto.Valid  = 1;
 250     NewPte->u.Proto.ReadOnly = 0;
 251     NewPte->u.Proto.Protection = 0;
 252 }
 253
 254 /* Sign extend 48 bits */
 255 #define MiProtoPteToPte(x) (PMMPTE)((LONG64)(x)->u.Proto.ProtoAddress)
 256
 257 VOID
 258 FORCEINLINE
 259 MmInitGlobalKernelPageDirectory(VOID)
 260 {
 261     /* Nothing to do */
 262 }
 263