ntoskrnl/include/internal/arm/mm.h

   1 #pragma once
   2
   3 #define _MI_PAGING_LEVELS 2
   4
   5 #define PDE_SHIFT 20
   6
   7 //
   8 // Number of bits corresponding to the area that a coarse page table entry represents (4KB)
   9 //
  10 #define PTE_SHIFT 12
  11 #define PTE_SIZE (1 << PTE_SHIFT)
  12
  13 //
  14 // Number of bits corresponding to the area that a coarse page table occupies (1KB)
  15 //
  16 #define CPT_SHIFT 10
  17 #define CPT_SIZE  (1 << CPT_SHIFT)
  18
  19 //
  20 // Base Addresses
  21 //
  22 #define PTE_BASE    0xC0000000
  23 #define PTE_TOP     0xC03FFFFF
  24 #define PDE_BASE    0xC0400000
  25 #define PDE_TOP     0xC04FFFFF
  26 #define HYPER_SPACE 0xC0500000
  27
  28 #if 0
  29 typedef struct _HARDWARE_PDE_ARMV6
  30 {
  31     ULONG Valid:1;     // Only for small pages
  32     ULONG LargePage:1; // Note, if large then Valid = 0
  33     ULONG Buffered:1;
  34     ULONG Cached:1;
  35     ULONG NoExecute:1;
  36     ULONG Domain:4;
  37     ULONG Ecc:1;
  38     ULONG PageFrameNumber:22;
  39 } HARDWARE_PDE_ARMV6, *PHARDWARE_PDE_ARMV6;
  40
  41 typedef struct _HARDWARE_LARGE_PTE_ARMV6
  42 {
  43     ULONG Valid:1;     // Only for small pages
  44     ULONG LargePage:1; // Note, if large then Valid = 0
  45     ULONG Buffered:1;
  46     ULONG Cached:1;
  47     ULONG NoExecute:1;
  48     ULONG Domain:4;
  49     ULONG Ecc:1;
  50     ULONG Accessed:1;
  51     ULONG Owner:1;
  52     ULONG CacheAttributes:3;
  53     ULONG ReadOnly:1;
  54     ULONG Shared:1;
  55     ULONG NonGlobal:1;
  56     ULONG SuperLagePage:1;
  57     ULONG Reserved:1;
  58     ULONG PageFrameNumber:12;
  59 } HARDWARE_LARGE_PTE_ARMV6, *PHARDWARE_LARGE_PTE_ARMV6;
  60
  61 typedef struct _HARDWARE_PTE_ARMV6
  62 {
  63     ULONG NoExecute:1;
  64     ULONG Valid:1;
  65     ULONG Buffered:1;
  66     ULONG Cached:1;
  67     ULONG Accessed:1;
  68     ULONG Owner:1;
  69     ULONG CacheAttributes:3;
  70     ULONG ReadOnly:1;
  71     ULONG Shared:1;
  72     ULONG NonGlobal:1;
  73     ULONG PageFrameNumber:20;
  74 } HARDWARE_PTE_ARMV6, *PHARDWARE_PTE_ARMV6;
  75
  76 C_ASSERT(sizeof(HARDWARE_PDE_ARMV6) == sizeof(ULONG));
  77 C_ASSERT(sizeof(HARDWARE_LARGE_PTE_ARMV6) == sizeof(ULONG));
  78 C_ASSERT(sizeof(HARDWARE_PTE_ARMV6) == sizeof(ULONG));
  79 #endif
  80
  81 /* For FreeLDR */
  82 typedef struct _PAGE_TABLE_ARM
  83 {
  84     HARDWARE_PTE_ARMV6 Pte[1024];
  85 } PAGE_TABLE_ARM, *PPAGE_TABLE_ARM;
  86
  87 typedef struct _PAGE_DIRECTORY_ARM
  88 {
  89     union
  90     {
  91         HARDWARE_PDE_ARMV6 Pde[4096];
  92         HARDWARE_LARGE_PTE_ARMV6 Pte[4096];
  93     };
  94 } PAGE_DIRECTORY_ARM, *PPAGE_DIRECTORY_ARM;
  95
  96 C_ASSERT(sizeof(PAGE_TABLE_ARM) == PAGE_SIZE);
  97 C_ASSERT(sizeof(PAGE_DIRECTORY_ARM) == (4 * PAGE_SIZE));
  98
  99 typedef enum _ARM_DOMAIN
 100 {
 101     FaultDomain,
 102     ClientDomain,
 103     InvalidDomain,
 104     ManagerDomain
 105 } ARM_DOMAIN;
 106
 107 struct _EPROCESS;
 108 PULONG MmGetPageDirectory(VOID);
 109
 110 #define MI_MAKE_LOCAL_PAGE(x)      ((x)->u.Hard.NonGlobal = 1)
 111 #define MI_MAKE_DIRTY_PAGE(x)
 112 #define MI_MAKE_ACCESSED_PAGE(x)
 113 #define MI_MAKE_OWNER_PAGE(x)      ((x)->u.Hard.Owner = 1)
 114 #define MI_MAKE_WRITE_PAGE(x)      ((x)->u.Hard.ReadOnly = 0)
 115 #define MI_PAGE_DISABLE_CACHE(x)   ((x)->u.Hard.Cached = 0)
 116 #define MI_PAGE_WRITE_THROUGH(x)   ((x)->u.Hard.Buffered = 0)
 117 #define MI_PAGE_WRITE_COMBINED(x)  ((x)->u.Hard.Buffered = 1)
 118 #define MI_IS_PAGE_WRITEABLE(x)    ((x)->u.Hard.ReadOnly == 0)
 119 #define MI_IS_PAGE_COPY_ON_WRITE(x)FALSE
 120 #define MI_IS_PAGE_DIRTY(x)        TRUE
 121 #define MI_IS_PAGE_LARGE(x)        FALSE
 122
 123 /* Easy accessing PFN in PTE */
 124 #define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
 125
 126 #define NR_SECTION_PAGE_TABLES              1024
 127 #define NR_SECTION_PAGE_ENTRIES             256
 128
 129 /* See PDR definition */
 130 #define MI_HYPERSPACE_PTES                  (256 - 1)
 131 #define MI_ZERO_PTES                        (32)
 132 #define MI_MAPPING_RANGE_START              ((ULONG)HYPER_SPACE)
 133 #define MI_MAPPING_RANGE_END                (MI_MAPPING_RANGE_START + \
 134                                              MI_HYPERSPACE_PTES * PAGE_SIZE)
 135 #define MI_ZERO_PTE                         (PMMPTE)(MI_MAPPING_RANGE_END + \
 136                                              PAGE_SIZE)
 137 #define MI_DUMMY_PTE                        (PMMPTE)(MI_MAPPING_RANGE_END + \
 138                                              PAGE_SIZE)
 139 #define MI_VAD_BITMAP                       (PMMPTE)(MI_DUMMY_PTE + \
 140                                              PAGE_SIZE)
 141 #define MI_WORKING_SET_LIST                 (PMMPTE)(MI_VAD_BITMAP + \
 142                                              PAGE_SIZE)
 143
 144 /* Retrives the PDE entry for the given VA */
 145 #define MiGetPdeAddress(x) ((PMMPDE)(PDE_BASE + (((ULONG)(x) >> 20) << 2)))
 146 #define MiAddressToPde(x)  MiGetPdeAddress(x)
 147
 148 /* Retrieves the PTE entry for the given VA */
 149 #define MiGetPteAddress(x) ((PMMPTE)(PTE_BASE + (((ULONG)(x) >> 12) << 2)))
 150 #define MiAddressToPte(x)  MiGetPteAddress(x)
 151
 152 /* Retrives the PDE offset for the given VA */
 153 #define MiGetPdeOffset(x)       (((ULONG)(x)) >> 20)
 154 #define MiGetPteOffset(x)       ((((ULONG)(x)) << 12) >> 24)
 155 #define MiAddressToPteOffset(x) MiGetPteOffset(x)
 156
 157 /* Convert a PTE into a corresponding address */
 158 #define MiPteToAddress(x) ((PVOID)((ULONG)(x) << 10))
 159 #define MiPdeToAddress(x) ((PVOID)((ULONG)(x) << 18))
 160
 161 #define PAGE_TO_SECTION_PAGE_DIRECTORY_OFFSET(x) \
 162     ((x) / (4*1024*1024))
 163
 164 #define PAGE_TO_SECTION_PAGE_TABLE_OFFSET(x) \
 165     ((((x)) % (4*1024*1024)) / (4*1024))
 166
 167 #define MM_CACHE_LINE_SIZE 64